USRE48111E1 - Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect - Google Patents
Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect Download PDFInfo
- Publication number
- USRE48111E1 USRE48111E1 US15/473,447 US201715473447A USRE48111E US RE48111 E1 USRE48111 E1 US RE48111E1 US 201715473447 A US201715473447 A US 201715473447A US RE48111 E USRE48111 E US RE48111E
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- United States
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- semiconductor die
- interposer frame
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- encapsulant
- carrier
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Definitions
- the present invention relates in general to semiconductor devices and, more particularly, to a semiconductor device and method of forming an interposer frame over a semiconductor die to provide vertical electrical interconnect.
- Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charged-coupled devices (CCDs), solar cells, and digital micro-mirror devices (DMDs).
- LED light emitting diode
- MOSFET power metal oxide semiconductor field effect transistor
- Semiconductor devices perform a wide range of functions such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual projections for television displays.
- Semiconductor devices are found in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.
- Semiconductor devices exploit the electrical properties of semiconductor materials.
- the atomic structure of semiconductor material allows its electrical conductivity to be manipulated by the application of an electric field or base current or through the process of doping. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.
- a semiconductor device contains active and passive electrical structures.
- Active structures including bipolar and field effect transistors, control the flow of electrical current. By varying levels of doping and application of an electric field or base current, the transistor either promotes or restricts the flow of electrical current.
- Passive structures including resistors, capacitors, and inductors, create a relationship between voltage and current necessary to perform a variety of electrical functions.
- the passive and active structures are electrically connected to form circuits, which enable the semiconductor device to perform high-speed calculations and other useful functions.
- Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die is typically identical and contains circuits formed by electrically connecting active and passive components.
- Back-end manufacturing involves singulating individual die from the finished wafer and packaging the die to provide structural support and environmental isolation.
- One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products.
- a smaller die size may be achieved by improvements in the front-end process resulting in die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.
- a semiconductor die is typically enclosed by an encapsulant.
- a top and bottom build-up interconnect structure are formed over opposite surfaces of the encapsulant.
- a redistribution layer (RDL) and insulating layer are commonly formed within the top and bottom build-up interconnect structures.
- a conductive pillar is typically formed through the encapsulant for z-direction vertical electrical interconnect between the top and bottom interconnect structures.
- the conductive pillar and RDL formation are known to use complicated, expensive, and time-consuming processes involving lithography, etching, and metal deposition.
- the present invention is a method of making a semiconductor device comprising the steps of providing a carrier, mounting a first semiconductor die over the carrier, providing an interposer frame having an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame, mounting the interposer over the carrier and first semiconductor die with the conductive pillars disposed around the first semiconductor die, depositing an encapsulant through the opening in the interposer frame over the carrier and first semiconductor die, removing the carrier, and forming an interconnect structure over the encapsulant and first semiconductor die.
- the present invention is a method of making a semiconductor device comprising the steps of providing a carrier, mounting a first semiconductor die over the carrier, depositing an encapsulant over the carrier and first semiconductor die, providing an interposer frame having an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame, mounting the interposer over the carrier and first semiconductor die by pressing the interposer frame against the encapsulant, removing the carrier, and forming an interconnect structure over the encapsulant and first semiconductor die.
- the present invention is a method of making a semiconductor device comprising the steps of providing a first semiconductor die, providing an interposer frame having an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame, mounting the interposer over the first semiconductor die with the conductive pillars disposed around the first semiconductor die, depositing an encapsulant over the first semiconductor die, and forming an interconnect structure over the encapsulant and first semiconductor die.
- the present invention is a semiconductor device comprising a first semiconductor die and interposer frame mounted over the first semiconductor die.
- the interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame.
- An encapsulant is deposited over the first semiconductor die.
- An interconnect structure is formed over the encapsulant and first semiconductor die.
- FIG. 1 illustrates a PCB with different types of packages mounted to its surface
- FIGS. 2a-2c illustrate further detail of the representative semiconductor packages mounted to the PCB
- FIGS. 3a-3c illustrate a semiconductor wafer with a plurality of semiconductor die separated by saw streets
- FIGS. 4a-4f illustrate a pre-formed interposer frame with conductive pillars formed over the interposer frame
- FIGS. 5a-5h illustrate a process of forming a Fo-WLCSP with an interposer frame and conductive pillars providing vertical interconnect for a semiconductor die
- FIG. 6 illustrates the Fo-WLCSP with the interposer frame and conductive pillars providing vertical interconnect for the semiconductor die
- FIG. 7 illustrates a plurality of stack Fo-WLCSP each with an interposer frame and conductive pillars providing vertical interconnect for the semiconductor die;
- FIGS. 8a-8g illustrate mounting the interposer frame over an encapsulant slurry
- FIG. 9 illustrates the Fo-WLCSP with the interposer frame mounted over the encapsulant slurry
- FIGS. 10a-10e illustrate forming the interposer frame with cavities to partially contain the semiconductor die
- FIG. 11 illustrates the Fo-WLCSP with the semiconductor die partially contained within the cavities of the interposer frame
- FIG. 12 illustrates the Fo-WLCSP with a bond wire type semiconductor die mounted over the interposer frame
- FIG. 13 illustrates the Fo-WLCSP with an ISM mounted over the semiconductor die.
- Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer.
- Each die on the wafer contains active and passive electrical components, which are electrically connected to form functional electrical circuits.
- Active electrical components such as transistors and diodes, have the ability to control the flow of electrical current.
- Passive electrical components such as capacitors, inductors, resistors, and transformers, create a relationship between voltage and current necessary to perform electrical circuit functions.
- Passive and active components are formed over the surface of the semiconductor wafer by a series of process steps including doping, deposition, photolithography, etching, and planarization.
- Doping introduces impurities into the semiconductor material by techniques such as ion implantation or thermal diffusion.
- the doping process modifies the electrical conductivity of semiconductor material in active devices, transforming the semiconductor material into an insulator, conductor, or dynamically changing the semiconductor material conductivity in response to an electric field or base current.
- Transistors contain regions of varying types and degrees of doping arranged as necessary to enable the transistor to promote or restrict the flow of electrical current upon the application of the electric field or base current.
- Active and passive components are formed by layers of materials with different electrical properties.
- the layers can be formed by a variety of deposition techniques determined in part by the type of material being deposited. For example, thin film deposition may involve chemical vapor deposition (CVD), physical vapor deposition (PVD), electrolytic plating, and electroless plating processes.
- CVD chemical vapor deposition
- PVD physical vapor deposition
- electrolytic plating electroless plating processes.
- Each layer is generally patterned to form portions of active components, passive components, or electrical connections between components.
- the layers can be patterned using photolithography, which involves the deposition of light sensitive material, e.g., photoresist, over the layer to be patterned.
- a pattern is transferred from a photomask to the photoresist using light.
- the portion of the photoresist pattern subjected to light is removed using a solvent, exposing portions of the underlying layer to be patterned.
- the remainder of the photoresist is removed, leaving behind a patterned layer.
- some types of materials are patterned by directly depositing the material into the areas or voids formed by a previous deposition/etch process using techniques such as electroless and electrolytic plating.
- Planarization can be used to remove material from the surface of the wafer and produce a uniformly flat surface. Planarization involves polishing the surface of the wafer with a polishing pad. An abrasive material and corrosive chemical are added to the surface of the wafer during polishing. The combined mechanical action of the abrasive and corrosive action of the chemical removes any irregular topography, resulting in a uniformly flat surface.
- Back-end manufacturing refers to cutting or singulating the finished wafer into the individual die and then packaging the die for structural support and environmental isolation.
- the wafer is scored and broken along non-functional regions of the wafer called saw streets or scribes.
- the wafer is singulated using a laser cutting tool or saw blade.
- the individual die are mounted to a package substrate that includes pins or contact pads for interconnection with other system components.
- Contact pads formed over the semiconductor die are then connected to contact pads within the package.
- the electrical connections can be made with solder bumps, stud bumps, conductive paste, or wirebonds.
- An encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation.
- the finished package is then inserted into an electrical system and the functionality of the semiconductor device is made available to the other system components.
- FIG. 1 illustrates electronic device 50 having a chip carrier substrate or printed circuit board (PCB) 52 with a plurality of semiconductor packages mounted on its surface.
- Electronic device 50 may have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application. The different types of semiconductor packages are shown in FIG. 1 for purposes of illustration.
- Electronic device 50 may be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions.
- electronic device 50 may be a subcomponent of a larger system.
- electronic device 50 may be part of a cellular phone, personal digital assistant (PDA), digital video camera (DVC), or other electronic communication device.
- PDA personal digital assistant
- DVC digital video camera
- electronic device 50 can be a graphics card, network interface card, or other signal processing card that can be inserted into a computer.
- the semiconductor package can include microprocessors, memories, application specific integrated circuits (ASIC), logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components.
- ASIC application specific integrated circuits
- the miniaturization and the weight reduction are essential for these products to be accepted by the market.
- the distance between semiconductor devices must be decreased to achieve higher density.
- PCB 52 provides a general substrate for structural support and electrical interconnect of the semiconductor packages mounted on the PCB.
- Conductive signal traces 54 are formed over a surface or within layers of PCB 52 using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process. Signal traces 54 provide for electrical communication between each of the semiconductor packages, mounted components, and other external system components. Traces 54 also provide power and ground connections to each of the semiconductor packages.
- a semiconductor device has two packaging levels.
- First level packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate carrier.
- Second level packaging involves mechanically and electrically attaching the intermediate carrier to the PCB.
- a semiconductor device may only have the first level packaging where the die is mechanically and electrically mounted directly to the PCB.
- first level packaging including wire bond package 56 and flip chip 58
- second level packaging including ball grid array (BGA) 60 , bump chip carrier (BCC) 62 , dual in-line package (DIP) 64 , land grid array (LGA) 66 , multi-chip module (MCM) 68 , quad flat non-leaded package (QFN) 70 , and quad flat package 72 .
- BGA ball grid array
- BCC bump chip carrier
- DIP dual in-line package
- LGA land grid array
- MCM multi-chip module
- QFN quad flat non-leaded package
- quad flat package 72 quad flat package
- electronic device 50 includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages.
- manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using cheaper components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers.
- FIGS. 2a-2c show exemplary semiconductor packages.
- FIG. 2a illustrates further detail of DIP 64 mounted on PCB 52 .
- Semiconductor die 74 includes an active region containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and are electrically interconnected according to the electrical design of the die.
- the circuit may include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements formed within the active region of semiconductor die 74 .
- Contact pads 76 are one or more layers of conductive material, such as aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag), and are electrically connected to the circuit elements formed within semiconductor die 74 .
- semiconductor die 74 is mounted to an intermediate carrier 78 using a gold-silicon eutectic layer or adhesive material such as thermal epoxy or epoxy resin.
- the package body includes an insulative packaging material such as polymer or ceramic.
- Conductor leads 80 and wire bonds 82 provide electrical interconnect between semiconductor die 74 and PCB 52 .
- Encapsulant 84 is deposited over the package for environmental protection by preventing moisture and particles from entering the package and contaminating die 74 or wire bonds 82 .
- FIG. 2b illustrates further detail of BCC 62 mounted on PCB 52 .
- Semiconductor die 88 is mounted over carrier 90 using an underfill or epoxy-resin adhesive material 92 .
- Wire bonds 94 provide first level packaging interconnect between contact pads 96 and 98 .
- Molding compound or encapsulant 100 is deposited over semiconductor die 88 and wire bonds 94 to provide physical support and electrical isolation for the device.
- Contact pads 102 are formed over a surface of PCB 52 using a suitable metal deposition process such as electrolytic plating or electroless plating to prevent oxidation.
- Contact pads 102 are electrically connected to one or more conductive signal traces 54 in PCB 52 .
- Bumps 104 are formed between contact pads 98 of BCC 62 and contact pads 102 of PCB 52 .
- semiconductor die 58 is mounted face down to intermediate carrier 106 with a flip chip style first level packaging.
- Active region 108 of semiconductor die 58 contains analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed according to the electrical design of the die.
- the circuit may include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements within active region 108 .
- Semiconductor die 58 is electrically and mechanically connected to carrier 106 through bumps 110 .
- BGA 60 is electrically and mechanically connected to PCB 52 with a BGA style second level packaging using bumps 112 .
- Semiconductor die 58 is electrically connected to conductive signal traces 54 in PCB 52 through bumps 110 , signal lines 114 , and bumps 112 .
- a molding compound or encapsulant 116 is deposited over semiconductor die 58 and carrier 106 to provide physical support and electrical isolation for the device.
- the flip chip semiconductor device provides a short electrical conduction path from the active devices on semiconductor die 58 to conduction tracks on PCB 52 in order to reduce signal propagation distance, lower capacitance, and improve overall circuit performance.
- the semiconductor die 58 can be mechanically and electrically connected directly to PCB 52 using flip chip style first level packaging without intermediate carrier 106 .
- FIG. 3a shows a semiconductor wafer 120 with a base substrate material 122 , such as silicon, germanium, gallium arsenide, indium phosphide, or silicon carbide, for structural support.
- a plurality of semiconductor die or components 124 is formed on wafer 120 separated by saw streets 126 as described above.
- FIG. 3b shows a cross-sectional view of a portion of semiconductor wafer 120 .
- Each semiconductor die 124 has a back surface 128 and an active surface 130 containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die.
- the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface 130 to implement analog circuits or digital circuits, such as digital signal processor (DSP), ASIC, memory, or other signal processing circuit.
- DSP digital signal processor
- Semiconductor die 124 may also contain integrated passive devices (IPD), such as inductors, capacitors, and resistors, for RF signal processing.
- IPD integrated passive devices
- semiconductor die 124 is a flipchip type semiconductor die.
- An electrically conductive layer 132 is formed over active surface 130 using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process.
- Conductive layer 132 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material.
- Conductive layer 132 operates as contact pads electrically connected to the circuits on active surface 130 .
- semiconductor wafer 120 is singulated through saw street 126 using a saw blade or laser cutting tool 134 into individual semiconductor die 124 .
- FIG. 4a-4f shows formation of a wafer-form, strip interposer with conductive pillars.
- a substrate or carrier 140 contains temporary or sacrificial base material such as silicon, polymer, beryllium oxide, or other suitable low-cost, rigid material for structural support.
- An interface layer or double-sided tape 142 is formed over carrier 140 as a temporary adhesive bonding film or etch-stop layer.
- a semiconductor wafer or substrate 144 contains a base material, such as silicon, germanium, gallium arsenide, indium phosphide, or silicon carbide, for structural support.
- substrate 144 can contain embedded semiconductor die or passive devices.
- Substrate 144 can also be a multi-layer laminate, ceramic, or leadframe. Substrate 144 is mounted to interface layer 142 over carrier 140 .
- a plurality of vias is formed through substrate 144 using laser drilling, mechanical drilling, or deep reactive ion etching (DRIE).
- the vias are filled with Al, Cu, Sn, Ni, Au, Ag, titanium (Ti), tungsten (W), poly-silicon, or other suitable electrically conductive material using electrolytic plating, electroless plating process, or other suitable metal deposition process to form z-direction vertical interconnect conductive vias 146 .
- An insulating or passivation layer 148 is formed over a surface of substrate 144 and conductive vias 146 using PVD, CVD, printing, spin coating, spray coating, sintering or thermal oxidation.
- the insulating layer 148 contains one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), or other material having similar insulating and structural properties.
- a portion of insulating layer 148 is removed by an etching process to expose substrate 144 and conductive vias 146 .
- An electrically conductive layer or RDL 150 is formed over the exposed substrate 144 and conductive vias 146 using a patterning and metal deposition process such as printing, PVD, CVD, sputtering, electrolytic plating, and electroless plating.
- Conductive layer 150 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material.
- Conductive layer 150 is electrically connected to conductive vias 146 .
- a substrate or carrier 154 contains temporary or sacrificial base material such as silicon, polymer, beryllium oxide, or other suitable low-cost, rigid material for structural support.
- An interface layer or double-sided tape 156 is formed over carrier 154 as a temporary adhesive bonding film or etch-stop layer.
- substrate 144 is mounted to interface layer 156 over carrier 154 .
- Carrier 140 and interface layer 142 are removed by chemical etching, mechanical peeling, CMP, mechanical grinding, thermal bake, UV light, laser scanning, or wet stripping to expose a surface of substrate 144 and conductive vias 146 opposite conductive layer 150 .
- An insulating or passivation layer 158 is formed over substrate 144 and conductive vias 146 using PVD, CVD, printing, spin coating, spray coating, sintering or thermal oxidation.
- the insulating layer 158 contains one or more layers of Si)2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties. A portion of insulating layer 158 is removed by an etching process to expose substrate 144 and conductive vias 146 .
- An electrically conductive layer or RDL 160 is formed over the exposed substrate 144 and conductive vias 146 using a patterning and metal deposition process such as printing, PVD, CVD, sputtering, electrolytic plating, and electroless plating.
- Conductive layer 160 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material.
- Conductive layer 160 is electrically connected to conductive vias 146 .
- conductive vias 146 are formed through substrate 144 after forming conductive layers 150 and/or 160 .
- a photoresist layer 162 is formed over insulating layer 158 and conductive layer 160 .
- a plurality of vias is formed through photoresist layer 162 over conductive layer 160 using a patterning and etching process.
- the vias are filled with Al, Cu, Sn, Ni, Au, Ag, Ti, W, poly-silicon, or other suitable electrically conductive material using electrolytic plating, electroless plating process, or other suitable metal deposition process. Stacked bumps and stud bumps can also be formed in the vias.
- photoresist layer 162 is removed leaving z-direction vertical interconnect conductive pillars 164 over conductive layer 160 .
- Carrier 154 and interface layer 156 are removed by chemical etching, mechanical peeling, CMP, mechanical grinding, thermal bake, UV light, laser scanning, or wet stripping leaving the pre-formed interposer frame 166 with conductive pillars 164 .
- Conductive layers 150 and 160 and conductive vias 146 constitute a vertical interconnect formed through interposer frame 166 .
- One or more openings 168 are formed through interposer frame 166 .
- FIG. 4f shows a top view of interposer frame 166 with conductive pillars 164 and openings 168 .
- FIGS. 5a-5h illustrate, in relation to FIGS. 1 and 2a-2c , a process of forming a Fo-WLCSP with an interposer frame and conductive pillars providing vertical interconnect for a semiconductor die.
- a substrate or carrier 170 contains temporary or sacrificial base material such as silicon, polymer, beryllium oxide, or other suitable low-cost, rigid material for structural support.
- An interface layer or double-sided tape 171 is formed over carrier 170 as a temporary adhesive bonding film or etch-stop layer.
- semiconductor die 124 from FIGS. 3a-3c are mounted over interface layer 171 .
- semiconductor die 124 are mounted to interface layer 171 with active surface 130 oriented toward carrier 170 .
- the pre-formed interposer frame 166 is positioned over carrier 170 .
- the interposer frame 166 is mounted to interface layer 171 with conductive pillars 164 disposed around semiconductor die 124 , as shown in FIG. 5d .
- Alignment marks 173 can be made on interface layer 171 to assist with mounting interposer frame 166 .
- Solder paste can also be deposited on carrier 170 to assist with alignment and bonding of interposer frame 166 to the carrier.
- the height of conductive pillars 164 is greater than a thickness of semiconductor die 124 . Accordingly, a gap remains between back surface 128 of semiconductor die 124 and interposer frame 166 .
- an encapsulant or molding compound 172 is injected or deposited through openings 168 around semiconductor die 124 and in the gap between interposer frame 166 and the die using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator.
- Encapsulant 172 can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler.
- Encapsulant 172 is non-conductive and environmentally protects the semiconductor device from external elements and contaminants.
- Semiconductor die 124 can be mounted to wettable contact pads formed over carrier 170 to reduce die shifting during encapsulation.
- carrier 170 and interface layer 171 are removed by chemical etching, mechanical peeling, CMP, mechanical grinding, thermal bake, UV light, laser scanning, or wet stripping to expose encapsulant 172 , semiconductor die 124 , and conductive pillars 164 .
- a build-up interconnect structure 174 is formed over semiconductor die 124 , conductive pillars 164 , and encapsulant 172 .
- the build-up interconnect structure 174 includes an electrically conductive layer or RDL 176 formed using a patterning and metal deposition process such as sputtering, electrolytic plating, and electroless plating.
- Conductive layer 176 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material.
- One portion of conductive layer 176 is electrically connected to contact pads 132 of semiconductor die 124 .
- Another portion of conductive layer 176 is electrically connected to conductive pillars 164 .
- Other portions of conductive layer 176 can be electrically common or electrically isolated depending on the design and function of semiconductor die 124 .
- An insulating or passivation layer 178 is formed around conductive layer 176 for electrical isolation using PVD, CVD, printing, spin coating, spray coating, sintering or thermal oxidation.
- the insulating layer 178 contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties. A portion of insulating layer 178 can be removed by an etching process to expose conductive layer 176 for additional electrical interconnect.
- an electrically conductive bump material is deposited over build-up interconnect structure 174 and electrically connected to the exposed portion of conductive layer 176 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process.
- the bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution.
- the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder.
- the bump material is bonded to conductive layer 176 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form spherical balls or bumps 180 .
- bumps 180 are reflowed a second time to improve electrical contact to conductive layer 176 .
- An under bump metallization (UBM) can be formed under bumps 180 .
- the bumps can also be compression bonded to conductive layer 176 .
- Bumps 180 represent one type of interconnect structure that can be formed over conductive layer 176 .
- the interconnect structure can also use stud bump, micro bump, or other electrical interconnect.
- Semiconductor die 124 are singulated through interposer frame 166 , encapsulant 172 , and build-up interconnect structure 174 with saw blade or laser cutting tool 182 into individual Fo-WLCSP 184 .
- FIG. 6 shows Fo-WLCSP 184 after singulation.
- Semiconductor die 124 is electrically connected through contact pads 132 and build-up interconnect structure 174 to conductive pillars 164 and interposer frame 166 .
- the pre-formed interposer frame 166 simplifies the assembly process by negating the need for RDL patterning over at least one surface of encapsulant 172 , or forming conductive pillars through the encapsulant.
- FIG. 7 shows a plurality of stacked Fo-WLCSP 184 electrically connected through interposer frame 166 , build-up interconnect structure 174 , bumps 180 , and conductive vias 164 .
- FIGS. 8a-8g illustrate, in relation to FIGS. 1 and 2a-2c , another process of forming a Fo-WLCSP with an interposer frame and conductive pillars providing vertical interconnect for a semiconductor die.
- a substrate or carrier 190 contains temporary or sacrificial base material such as silicon, polymer, beryllium oxide, or other suitable low-cost, rigid material for structural support.
- An interface layer or double-sided tape 192 is formed over carrier 190 as a temporary adhesive bonding film or etch-stop layer.
- Semiconductor die 124 from FIG. 3a-3c are mounted over interface layer 192 .
- semiconductor die 124 are mounted to interface layer 192 with active surface 130 oriented toward carrier 190 .
- an encapsulant or molding compound 194 is deposited over carrier 190 and semiconductor die 124 as a slurry.
- Encapsulant slurry 194 can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler.
- the pre-formed interposer frame 166 from FIGS. 4a-4f is positioned over carrier 190 .
- the interposer frame 166 is mounted to interface layer 192 by pressing the interposer frame onto encapsulant slurry 194 with force F.
- the pressure from force F causes encapsulant slurry 194 to flatten and completely fill the area under interposer frame 166 around semiconductor die 124 and conductive pillars 164 . Excess encapsulant slurry 194 exits through openings 168 .
- conductive pillars 164 are disposed around semiconductor die 124 and contacting interface layer 192 , as shown in FIG. 8d .
- Encapsulant 194 surrounds semiconductor die 124 and conductive pillars 164 .
- the height of conductive pillars 164 is greater than a thickness of semiconductor die 124 . Accordingly, back surface 128 of semiconductor die 124 is covered by encapsulant 194 .
- Semiconductor die 124 can be mounted to wettable contact pads formed over carrier 190 to reduce die shifting during encapsulation.
- carrier 190 and interface layer 192 are removed by chemical etching, mechanical peeling, CMP, mechanical grinding, thermal bake, UV light, laser scanning, or wet stripping to expose encapsulant 194 , semiconductor die 124 , and conductive pillars 164 .
- a build-up interconnect structure 196 is formed over semiconductor die 124 , conductive pillars 164 , and encapsulant 194 .
- the build-up interconnect structure 196 includes an electrically conductive layer or RDL 198 formed using a patterning and metal deposition process such as sputtering, electrolytic plating, and electroless plating.
- Conductive layer 198 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material.
- One portion of conductive layer 198 is electrically connected to contact pads 132 of semiconductor die 124 .
- Another portion of conductive layer 198 is electrically connected to conductive pillars 164 .
- Other portions of conductive layer 198 can be electrically common or electrically isolated depending on the design and function of semiconductor die 124 .
- An insulating or passivation layer 200 is formed around conductive layer 198 for electrical isolation using PVD, CVD, printing, spin coating, spray coating, sintering or thermal oxidation.
- the insulating layer 200 contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties. A portion of insulating layer 200 can be removed by an etching process to expose conductive layer 198 for additional electrical interconnect.
- an electrically conductive bump material is deposited over build-up interconnect structure 196 and electrically connected to the exposed portion of conductive layer 198 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process.
- the bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution.
- the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder.
- the bump material is bonded to conductive layer 198 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form spherical balls or bumps 202 .
- bumps 202 are reflowed a second time to improve electrical contact to conductive layer 198 .
- a UBM can be formed under bumps 202 .
- the bumps can also be compression bonded to conductive layer 198 .
- Bumps 202 represent one type of interconnect structure that can be formed over conductive layer 198 .
- the interconnect structure can also use stud bump, micro bump, or other electrical interconnect.
- Semiconductor die 124 are singulated through interposer frame 166 , encapsulant 194 , and build-up interconnect structure 196 with saw blade or laser cutting tool 204 into individual Fo-WLCSP 206 .
- FIG. 9 shows Fo-WLCSP 206 after singulation.
- Semiconductor die 124 is electrically connected through contact pads 132 and build-up interconnect structure 196 to conductive pillars 164 and interposer frame 166 .
- the pre-formed interposer frame 166 simplifies the assembly process by negating the need for RDL patterning over at least one surface of encapsulant 194 , or forming conductive pillars through the encapsulant.
- Depositing encapsulant slurry 194 prior to mounting interposer frame 166 and then pressing the interposer frame over the encapsulant slurry provides uniform coverage of the encapsulant around semiconductor die 124 and conductive pillars 164 .
- FIGS. 10a-10e illustrate, in relation to FIGS. 1 and 2a-2c , another process of forming a Fo-WLCSP with an interposer frame and conductive pillars providing vertical interconnect for a semiconductor die.
- a pre-formed interposer frame 210 is positioned over carrier 190 , as shown in FIG. 10a .
- interposer frame 210 has cavities or recesses 212 formed in substrate 214 in areas designated for alignment with semiconductor die 124 .
- Conductive vias and layers 215 are formed through substrate 214 and insulating layer 217 similar to FIGS. 4a-4f .
- One or more openings 216 are formed through interposer frame 210 .
- the interposer frame 210 is mounted to interface layer 192 by pressing the interposer frame onto encapsulant slurry 194 with force F.
- the pressure from force F causes encapsulant slurry 194 to flatten and completely fill the area under interposer frame 210 and around semiconductor die 124 and conductive pillars 218 . Excess encapsulant slurry 194 exits through openings 216 .
- semiconductor die 124 When properly seated, semiconductor die 124 are partially disposed within cavities 212 . Conductive pillars 218 are disposed around semiconductor die 124 and contacting interface layer 192 , as shown in FIG. 10b . Encapsulant 194 surrounds semiconductor die 124 and conductive pillars 164 . Semiconductor die 124 can be mounted to wettable contact pads formed over carrier 190 to reduce die shifting during encapsulation.
- carrier 190 and interface layer 192 are removed by chemical etching, mechanical peeling, CMP, mechanical grinding, thermal bake, UV light, laser scanning, or wet stripping to expose encapsulant 194 , semiconductor die 124 , and conductive pillars 218 .
- a build-up interconnect structure 222 is formed over semiconductor die 124 , conductive pillars 218 , and encapsulant 194 .
- the build-up interconnect structure 222 includes an electrically conductive layer or RDL 224 formed using a patterning and metal deposition process such as sputtering, electrolytic plating, and electroless plating.
- Conductive layer 224 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material.
- One portion of conductive layer 224 is electrically connected to contact pads 132 of semiconductor die 124 .
- Another portion of conductive layer 224 is electrically connected to conductive pillars 218 .
- Other portions of conductive layer 224 can be electrically common or electrically isolated depending on the design and function of semiconductor die 124 .
- An insulating or passivation layer 226 is formed around conductive layer 226 for electrical isolation using PVD, CVD, printing, spin coating, spray coating, sintering or thermal oxidation.
- the insulating layer 226 contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties. A portion of insulating layer 226 can be removed by an etching process to expose conductive layer 224 for additional electrical interconnect.
- an electrically conductive bump material is deposited over build-up interconnect structure 222 and electrically connected to the exposed portion of conductive layer 224 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process.
- the bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution.
- the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder.
- the bump material is bonded to conductive layer 224 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form spherical balls or bumps 228 .
- bumps 228 are reflowed a second time to improve electrical contact to conductive layer 224 .
- a UBM can be formed under bumps 228 .
- the bumps can also be compression bonded to conductive layer 224 .
- Bumps 228 represent one type of interconnect structure that can be formed over conductive layer 224 .
- the interconnect structure can also use stud bump, micro bump, or other electrical interconnect.
- Semiconductor die 124 are singulated through interposer frame 210 , encapsulant 194 , and build-up interconnect structure 196 with saw blade or laser cutting tool 230 into individual Fo-WLCSP 232 .
- FIG. 11 shows Fo-WLCSP 232 after singulation.
- Semiconductor die 124 is electrically connected through contact pads 132 and build-up interconnect structure 222 to conductive pillars 218 and interposer frame 210 .
- the pre-formed interposer frame 210 simplifies the assembly process by negating the need for RDL patterning over at least one surface of encapsulant 194 , or forming conductive pillars through the encapsulant.
- FIG. 12 shows an embodiment of Fo-WLCSP 240 , similar to FIG. 6 , with semiconductor die 242 mounted to interposer frame 166 with die attach adhesive 244 .
- Semiconductor die 242 has an active surface 248 containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die.
- the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface 248 to implement analog circuits or digital circuits, such as DSP, ASIC, memory, or other signal processing circuit.
- Semiconductor die 242 may also contain IPDs, such as inductors, capacitors, and resistors, for RF signal processing.
- semiconductor die 242 is a wire-bond die. Bond wires 250 are electrically connected between contact pads 252 on active surface 248 and conductive layer 150 of interposer frame 166 .
- An encapsulant or molding compound 254 is deposited over semiconductor die 242 and interposer frame 166 using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator.
- Encapsulant 254 can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler.
- Encapsulant 254 is non-conductive and environmentally protects the semiconductor device from external elements and contaminants.
- FIG. 13 shows an embodiment of Fo-WLCSP 260 , similar to FIG. 6 , with internal stacking module (ISM) 262 mounted to semiconductor die 124 with die attach adhesive 263 prior to mounting interposer frame 166 in FIG. 5c .
- the internal stacking module 262 includes semiconductor die 264 with an active surface 268 containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die.
- the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface 268 to implement analog circuits or digital circuits, such as DSP, ASIC, memory, or other signal processing circuit.
- Semiconductor die 264 may also contain IPDs, such as inductors, capacitors, and resistors, for RF signal processing.
- IPDs such as inductors, capacitors, and resistors
- Semiconductor die 264 is mounted to interposer frame 166 with die attach adhesive 269 .
- Bond wires 270 are electrically connected between contact pads 272 on active surface 268 and conductive layer 160 of interposer frame 166 .
- Encapsulant or molding compound 274 is deposited over semiconductor die 264 and interposer frame 166 using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator.
- Encapsulant 274 can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler.
- Encapsulant 274 is non-conductive and environmentally protects the semiconductor device from external elements and contaminants.
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Abstract
Description
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US12/545,357 US8169058B2 (en) | 2009-08-21 | 2009-08-21 | Semiconductor device and method of stacking die on leadframe electrically connected by conductive pillars |
US12/875,981 US8383457B2 (en) | 2010-09-03 | 2010-09-03 | Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect |
US15/473,447 USRE48111E1 (en) | 2009-08-21 | 2017-03-29 | Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect |
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Citations (134)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5250843A (en) | 1991-03-27 | 1993-10-05 | Integrated System Assemblies Corp. | Multichip integrated circuit modules |
US5353498A (en) | 1993-02-08 | 1994-10-11 | General Electric Company | Method for fabricating an integrated circuit module |
US5543657A (en) | 1994-10-07 | 1996-08-06 | International Business Machines Corporation | Single layer leadframe design with groundplane capability |
US5612513A (en) | 1995-09-19 | 1997-03-18 | Micron Communications, Inc. | Article and method of manufacturing an enclosed electrical circuit using an encapsulant |
US5742100A (en) | 1995-03-27 | 1998-04-21 | Motorola, Inc. | Structure having flip-chip connected substrates |
US5770888A (en) | 1995-12-29 | 1998-06-23 | Lg Semicon Co., Ltd. | Integrated chip package with reduced dimensions and leads exposed from the top and bottom of the package |
US5841193A (en) | 1996-05-20 | 1998-11-24 | Epic Technologies, Inc. | Single chip modules, repairable multichip modules, and methods of fabrication thereof |
US6020629A (en) | 1998-06-05 | 2000-02-01 | Micron Technology, Inc. | Stacked semiconductor package and method of fabrication |
US6291892B1 (en) | 1998-04-02 | 2001-09-18 | Oki Electric Industry Co., Ltd | Semiconductor package that includes a shallow metal basin surrounded by an insulator frame |
US6297547B1 (en) | 1998-02-13 | 2001-10-02 | Micron Technology Inc. | Mounting multiple semiconductor dies in a package |
US20020028327A1 (en) | 2000-05-30 | 2002-03-07 | Perry Charles H. | Conductive polymer interconnection configurations |
US6380624B1 (en) | 2000-10-10 | 2002-04-30 | Walsin Advanced Electronics Ltd. | Stacked integrated circuit structure |
US6417462B1 (en) | 2000-06-19 | 2002-07-09 | Intel Corporation | Low cost and high speed 3-load printed wiring board bus topology |
US20020098676A1 (en) | 2001-01-24 | 2002-07-25 | Ning Xian J. | Metal hard mask for ild rie processing of semiconductor memory devices to prevent oxidation of conductive lines |
US20030020151A1 (en) | 2001-06-04 | 2003-01-30 | Siliconware Precision Industries Co., Ltd | Thermally-enhanced stacked-die ball grid array semiconductor package and method of fabricating the same |
US20030032216A1 (en) | 2001-08-08 | 2003-02-13 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and manufacturing method thereof |
KR20030045950A (en) | 2001-12-03 | 2003-06-12 | 삼성전자주식회사 | Multi chip package comprising heat sinks |
US20030110788A1 (en) | 2001-12-19 | 2003-06-19 | Koeneman Paul B. | Method and apparatus for cooling an integrated circuit package using a cooling fluid |
US6590281B2 (en) | 2001-11-15 | 2003-07-08 | Siliconware Precision Industries Co., Ltd. | Crack-preventive semiconductor package |
US20030178719A1 (en) | 2002-03-22 | 2003-09-25 | Combs Edward G. | Enhanced thermal dissipation integrated circuit package and method of manufacturing enhanced thermal dissipation integrated circuit package |
US20030218250A1 (en) | 2002-05-27 | 2003-11-27 | Moriss Kung | Method for high layout density integrated circuit package substrate |
US6664644B2 (en) | 2001-08-03 | 2003-12-16 | Seiko Epson Corporation | Semiconductor device and method for manufacturing the same |
US20040036164A1 (en) | 2001-07-31 | 2004-02-26 | Toshihiko Koike | Semiconductor device and its manufacturing method |
US20040067605A1 (en) | 2002-10-02 | 2004-04-08 | Shinko Electric Industries, Co., Ltd. | Semiconductor device having additional functional element and method of manufacturing thereof |
US20040070064A1 (en) | 2002-10-15 | 2004-04-15 | Tae Yamane | Semiconductor device and fabrication method of the same |
US20040075164A1 (en) | 2002-10-18 | 2004-04-22 | Siliconware Precision Industries, Ltd. | Module device of stacked semiconductor packages and method for fabricating the same |
US6730544B1 (en) | 1999-12-20 | 2004-05-04 | Amkor Technology, Inc. | Stackable semiconductor package and method for manufacturing same |
US20040089943A1 (en) | 2002-11-07 | 2004-05-13 | Masato Kirigaya | Electronic control device and method for manufacturing the same |
US6765287B1 (en) | 2001-07-27 | 2004-07-20 | Charles W. C. Lin | Three-dimensional stacked semiconductor package |
US20040155359A1 (en) * | 2003-01-30 | 2004-08-12 | Yu-Nung Shen | Semiconductor device and method for making the same |
US20040160752A1 (en) | 2003-02-18 | 2004-08-19 | Matsushita Electric Industrial Co. | Electronic component built-in module and method of manufacturing the same |
US20040178499A1 (en) | 2003-03-10 | 2004-09-16 | Mistry Addi B. | Semiconductor package with multiple sides having package contacts |
US20040219717A1 (en) | 2000-03-09 | 2004-11-04 | Yoshikazu Takahashi | Method of manufacturing chip size package semiconductor device without intermediate substrate |
US20040238857A1 (en) | 2001-08-28 | 2004-12-02 | Tessera, Inc. | High frequency chip packages with connecting elements |
US20040262774A1 (en) | 2003-06-27 | 2004-12-30 | In-Ku Kang | Multi-chip packages having a plurality of flip chips and methods of manufacturing the same |
US20040262811A1 (en) | 2003-06-26 | 2004-12-30 | Semiconductor Components Industries, Llc | Method for making a direct chip attach device and structure |
US20050006730A1 (en) | 2003-07-07 | 2005-01-13 | Motorola, Inc. | Semiconductor component and method of manufacturing same |
US20050077626A1 (en) | 2003-10-13 | 2005-04-14 | Jacky Seiller | Forming of the last metallization level of an integrated circuit |
US6881607B2 (en) | 2000-08-08 | 2005-04-19 | Micron Technology, Inc. | Underfill and encapsulation of carrier substrate-mounted flip-chip components using stereolithography |
US20050133932A1 (en) | 2003-12-19 | 2005-06-23 | Jens Pohl | Semiconductor module with a semiconductor stack, and methods for its production |
US20050156296A1 (en) | 2004-01-02 | 2005-07-21 | Hsueh-Te Wang | Quad flat flip chip package and leadframe thereof |
US20050167812A1 (en) | 2003-01-15 | 2005-08-04 | Fujitsu Limited | Semiconductor device, three-dimensional semiconductor device, and method of manufacturing semiconductor device |
WO2005119776A1 (en) | 2004-06-04 | 2005-12-15 | Zycube Co., Ltd. | Semiconductor device having three-dimensional stack structure and method for manufacturing the same |
US20060006517A1 (en) | 2004-07-08 | 2006-01-12 | Lee Jin-Yang | Multi-chip package having heat dissipating path |
US7023085B2 (en) | 2004-03-29 | 2006-04-04 | Siliconware Precision Industries Co., Ltd | Semiconductor package structure with reduced parasite capacitance and method of fabricating the same |
US20060087020A1 (en) | 2004-10-22 | 2006-04-27 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for producing the same |
US20060102994A1 (en) | 2004-11-16 | 2006-05-18 | Siliconware Precision Industries Co., Ltd. | Multi-chip semiconductor package and fabrication method thereof |
US20060121718A1 (en) | 2004-12-07 | 2006-06-08 | Yoshihiro Machida | Manufacturing method of chip integrated substrate |
US20060128068A1 (en) | 2004-12-13 | 2006-06-15 | 3M Innovative Properties Company | Methods of using sonication to couple a heat sink to a heat-generating component |
US20060125042A1 (en) | 2003-07-28 | 2006-06-15 | Edward Fuergut | Electronic component and panel for producing the same |
US7071568B1 (en) | 2003-11-10 | 2006-07-04 | Amkor Technology, Inc. | Stacked-die extension support structure and method thereof |
US20060267175A1 (en) | 2005-05-31 | 2006-11-30 | Stats Chippac Ltd. | Stacked Semiconductor Package Assembly Having Hollowed Substrate |
US20060270106A1 (en) | 2005-05-31 | 2006-11-30 | Tz-Cheng Chiu | System and method for polymer encapsulated solder lid attach |
US7180165B2 (en) | 2003-09-05 | 2007-02-20 | Sanmina, Sci Corporation | Stackable electronic assembly |
US7186588B1 (en) | 2004-06-18 | 2007-03-06 | National Semiconductor Corporation | Method of fabricating a micro-array integrated circuit package |
US20070122940A1 (en) | 2005-11-30 | 2007-05-31 | Viswanadam Gautham | Method for packaging a semiconductor device |
US7235871B2 (en) | 2000-08-23 | 2007-06-26 | Micron Technology, Inc. | Stacked microelectronic dies |
US20070158832A1 (en) | 2003-11-07 | 2007-07-12 | Eiji Takaike | Electronic device and method of manufacturing the same |
US20070181990A1 (en) | 2006-02-03 | 2007-08-09 | Siliconware Precision Industries Co., Ltd. | Stacked semiconductor structure and fabrication method thereof |
US7261596B2 (en) | 2005-01-05 | 2007-08-28 | Shinko Electric Industries Co., Ltd. | Shielded semiconductor device |
US20070216004A1 (en) | 2006-03-17 | 2007-09-20 | Infineon Technologies Ag | Blank including a composite panel with semiconductor chips and plastic package molding compound and method and mold for producing the same |
US20070254404A1 (en) | 2006-05-01 | 2007-11-01 | Texas Instruments Incorporated | Semiconductor Package-on-Package System Including Integrated Passive Components |
US20070262346A1 (en) | 2006-05-10 | 2007-11-15 | Ralf Otremba | Electronic Component and a Method for its Production |
US20070290376A1 (en) | 2006-06-20 | 2007-12-20 | Broadcom Corporation | Integrated circuit (IC) package stacking and IC packages formed by same |
US20070290338A1 (en) | 2006-06-15 | 2007-12-20 | Joseph Kuczynski | Method and Apparatus for Carbon Dioxide Gettering for a Chip Module Assembly |
US20080017968A1 (en) | 2006-07-18 | 2008-01-24 | Samsung Electronics Co., Ltd. | Stack type semiconductor package and method of fabricating the same |
US20080029869A1 (en) | 2006-08-01 | 2008-02-07 | Samsung Electronics Co., Ltd. | Vertical stack type multi-chip package having improved grounding performance and lower semiconductor chip reliability |
US20080054434A1 (en) | 2006-08-31 | 2008-03-06 | Jae Myun Kim | Semiconductor stack package for optimal packaging of components having interconnections |
US20080054437A1 (en) | 2006-09-06 | 2008-03-06 | Samsung Electronics Co., Ltd. | Pop package and method of fabricating the same |
US20080067645A1 (en) | 2006-09-20 | 2008-03-20 | Chee Seng Foong | Heat spreader for semiconductor package |
US20080088019A1 (en) | 2001-03-05 | 2008-04-17 | Megica Corporation | Structure and manufacturing method of a chip scale package |
US20080090405A1 (en) | 2006-09-29 | 2008-04-17 | Tom Fitzgerald | Composite solder TIM for electronic package |
US7361531B2 (en) | 2005-11-01 | 2008-04-22 | Allegro Microsystems, Inc. | Methods and apparatus for Flip-Chip-On-Lead semiconductor package |
US20080099925A1 (en) | 2006-10-31 | 2008-05-01 | Qimonda Ag | Solder pillar bumping and a method of making the same |
US7368811B2 (en) | 2004-10-04 | 2008-05-06 | Samsung Electronics Co., Ltd | Multi-chip package and method for manufacturing the same |
US20080122059A1 (en) | 2006-11-29 | 2008-05-29 | Advanced Semiconductor Engineering, Inc. | Stacked chip package structure and fabricating method thereof |
US20080230898A1 (en) | 2007-03-19 | 2008-09-25 | Spansion Llc | Semiconductor device and method for manufacturing thereof |
US20080284001A1 (en) | 2007-04-13 | 2008-11-20 | Nec Corporation | Semiconductor device and fabrication method |
US20080315375A1 (en) | 2007-06-25 | 2008-12-25 | Epic Technologies, Inc. | Integrated conductive structures and fabrication methods thereof facilitating implementing a cell phone or other electronic system |
US20080315372A1 (en) | 2007-06-20 | 2008-12-25 | Stats Chippac, Ltd. | Wafer Level Integration Package |
US7476980B2 (en) | 2006-06-27 | 2009-01-13 | Infineon Technologies Ag | Die configurations and methods of manufacture |
US20090072368A1 (en) | 2007-08-03 | 2009-03-19 | Kunzhong Hu | Package for monolithic compound semiconductor (csc) devices for dc to dc converters |
US20090079067A1 (en) | 2007-09-26 | 2009-03-26 | Texas Instruments Incorporated | Method for Stacking Semiconductor Chips |
US20090091022A1 (en) | 2007-10-09 | 2009-04-09 | Infineon Technologies Ag | Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device |
US20090108425A1 (en) * | 2007-10-30 | 2009-04-30 | Samsung Electronics Co. Ltd. | Stacked package and method of manufacturing the same |
US20090127700A1 (en) | 2007-11-20 | 2009-05-21 | Matthew Romig | Thermal conductor lids for area array packaged multi-chip modules and methods to dissipate heat from multi-chip modules |
US7550832B2 (en) | 2006-08-18 | 2009-06-23 | Advanced Semiconductor Engineering, Inc. | Stackable semiconductor package |
US7550857B1 (en) | 2006-11-16 | 2009-06-23 | Amkor Technology, Inc. | Stacked redistribution layer (RDL) die assembly package |
US20090170241A1 (en) | 2007-12-26 | 2009-07-02 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier |
US20090166886A1 (en) | 2007-12-27 | 2009-07-02 | Kim Youngjoon | Mountable integrated circuit package system with intra-stack encapsulation |
US7579691B2 (en) | 2004-08-24 | 2009-08-25 | Sony Corporation | Semiconductor device, substrate, equipment board, method for producing semiconductor device, and semiconductor chip for communication |
US20090212401A1 (en) | 2008-02-26 | 2009-08-27 | Byung Tai Do | Package system for shielding semiconductor dies from electromagnetic interference |
US20090224391A1 (en) | 2008-03-04 | 2009-09-10 | Stats Chippac, Ltd. | Wafer Level Die Integration and Method Therefor |
US20090236720A1 (en) | 2008-03-24 | 2009-09-24 | In Sang Yoon | Integrated circuit package system with step mold recess |
US7608921B2 (en) | 2006-12-07 | 2009-10-27 | Stats Chippac, Inc. | Multi-layer semiconductor package |
US7615854B2 (en) | 2005-11-03 | 2009-11-10 | International Rectifier Corporation | Semiconductor package that includes stacked semiconductor die |
US20090278244A1 (en) | 2008-05-12 | 2009-11-12 | Texas Instruments Inc | Ic device having low resistance tsv comprising ground connection |
US7622324B2 (en) | 2002-09-25 | 2009-11-24 | Ziptronix | Wafer bonding hermetic encapsulation |
US20090302227A1 (en) | 2008-06-09 | 2009-12-10 | Honeywell International Inc. | Neutron Detection Structure |
US20100019362A1 (en) | 2008-07-23 | 2010-01-28 | Manolito Galera | Isolated stacked die semiconductor packages |
US20100025829A1 (en) | 2008-07-31 | 2010-02-04 | Infineon Technologies Ag | Semiconductor device |
US7687899B1 (en) | 2007-08-07 | 2010-03-30 | Amkor Technology, Inc. | Dual laminate package structure with embedded elements |
US20100084749A1 (en) | 2008-10-02 | 2010-04-08 | Advanced Semiconductor Engineering, Inc. | Package and fabricating method thereof |
US7714453B2 (en) | 2006-05-12 | 2010-05-11 | Broadcom Corporation | Interconnect structure and formation for package stacking of molded plastic area array package |
US7728420B2 (en) | 2006-12-07 | 2010-06-01 | International Rectifier Corporation | High current lead electrode for semiconductor device |
US20100133655A1 (en) | 2006-10-26 | 2010-06-03 | Elpida Memory, Inc. | Semiconductor device having a capacitance element and method of manufacturing the same |
US20100136749A1 (en) | 2007-08-17 | 2010-06-03 | National Semiconductor Corporation | Microarray package with plated contact pedestals |
US20100133665A1 (en) * | 2008-11-29 | 2010-06-03 | Jong-Woo Ha | Integrated circuit packaging system with lead frame and method of manufacture thereof |
US7745918B1 (en) | 2004-11-24 | 2010-06-29 | Amkor Technology, Inc. | Package in package (PiP) |
US20100164078A1 (en) | 2008-12-31 | 2010-07-01 | Ruben Madrid | Package assembly for semiconductor devices |
US7790504B2 (en) | 2006-03-10 | 2010-09-07 | Stats Chippac Ltd. | Integrated circuit package system |
US20100230792A1 (en) | 2009-03-12 | 2010-09-16 | Scott Irving | Premolded Substrates with Apertures for Semiconductor Die Packages with Stacked Dice, Said Packages, and Methods of Making the Same |
US20100237495A1 (en) | 2009-03-17 | 2010-09-23 | Stats Chippac, Ltd. | Semiconductor Device and Method of Providing Z-Interconnect Conductive Pillars with Inner Polymer Core |
US20100276792A1 (en) | 2009-05-01 | 2010-11-04 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Shielding Layer After Encapsulation and Grounded Through Interconnect Structure |
US20100289131A1 (en) | 2009-05-18 | 2010-11-18 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Overlapping Semiconductor Die with Coplanar Vertical Interconnect Structure |
US20100289126A1 (en) | 2009-05-18 | 2010-11-18 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming a 3D Inductor from Prefabricated Pillar Frame |
US7838337B2 (en) | 2008-12-01 | 2010-11-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming an interposer package with through silicon vias |
US7843052B1 (en) | 2008-11-13 | 2010-11-30 | Amkor Technology, Inc. | Semiconductor devices and fabrication methods thereof |
US7880280B2 (en) | 2007-02-16 | 2011-02-01 | Infineon Technologies Ag | Electronic component and method for manufacturing an electronic component |
US20110024888A1 (en) | 2009-07-31 | 2011-02-03 | Stats Chippac, Ltd. | Semiconductor Device and Method of Mounting Die with TSV in Cavity of Substrate for Electrical Interconnect of FI-POP |
US20110037155A1 (en) | 2009-08-12 | 2011-02-17 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Dam Material Around Periphery of Die to Reduce Warpage |
US20110037169A1 (en) | 2009-08-12 | 2011-02-17 | Stats Chippac, Ltd. | Semiconductor Device and Method of Dual-Molding Die Formed on Opposite Sides of Build-Up Interconnect Structures |
US20110042798A1 (en) | 2009-08-21 | 2011-02-24 | Stats Chippac, Ltd. | Semiconductor Device and Method of Stacking Die on Leadframe Electrically Connected by Conductive Pillars |
US20110068444A1 (en) | 2009-09-23 | 2011-03-24 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Open Cavity in TSV Interposer to Contain Semiconductor Die in WLCSMP |
US7964450B2 (en) | 2008-05-23 | 2011-06-21 | Stats Chippac, Ltd. | Wirebondless wafer level package with plated bumps and interconnects |
US20110186977A1 (en) * | 2010-01-29 | 2011-08-04 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Thin Profile WLCSP with Vertical Interconnect over Package Footprint |
US8039384B2 (en) | 2010-03-09 | 2011-10-18 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertically offset bond on trace interconnects on different height traces |
US20110278707A1 (en) | 2010-05-17 | 2011-11-17 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Prefabricated Multi-Die Leadframe for Electrical Interconnect of Stacked Semiconductor Die |
US20110278741A1 (en) | 2010-05-14 | 2011-11-17 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Interconnect Structure and Mounting Semiconductor Die in Recessed Encapsulant |
US20110291257A1 (en) | 2010-05-27 | 2011-12-01 | Reza Argenty Pagaila | Integrated circuit packaging system with dual side connection and method of manufacture thereof |
US20120038064A1 (en) | 2010-08-16 | 2012-02-16 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Wafer-Level Multi-Row Etched Leadframe With Base Leads and Embedded Semiconductor Die |
US8184453B1 (en) | 2008-07-31 | 2012-05-22 | Amkor Technology, Inc. | Increased capacity semiconductor package |
US20120193789A1 (en) | 2011-01-27 | 2012-08-02 | Unimicron Technology Corporation | Package stack device and fabrication method thereof |
US9240380B2 (en) | 2009-08-21 | 2016-01-19 | Stats Chippac, Ltd. | Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect |
-
2017
- 2017-03-29 US US15/473,447 patent/USRE48111E1/en active Active
Patent Citations (149)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5250843A (en) | 1991-03-27 | 1993-10-05 | Integrated System Assemblies Corp. | Multichip integrated circuit modules |
US5353498A (en) | 1993-02-08 | 1994-10-11 | General Electric Company | Method for fabricating an integrated circuit module |
US5543657A (en) | 1994-10-07 | 1996-08-06 | International Business Machines Corporation | Single layer leadframe design with groundplane capability |
US5742100A (en) | 1995-03-27 | 1998-04-21 | Motorola, Inc. | Structure having flip-chip connected substrates |
US5612513A (en) | 1995-09-19 | 1997-03-18 | Micron Communications, Inc. | Article and method of manufacturing an enclosed electrical circuit using an encapsulant |
US5770888A (en) | 1995-12-29 | 1998-06-23 | Lg Semicon Co., Ltd. | Integrated chip package with reduced dimensions and leads exposed from the top and bottom of the package |
US5841193A (en) | 1996-05-20 | 1998-11-24 | Epic Technologies, Inc. | Single chip modules, repairable multichip modules, and methods of fabrication thereof |
US6297547B1 (en) | 1998-02-13 | 2001-10-02 | Micron Technology Inc. | Mounting multiple semiconductor dies in a package |
US6291892B1 (en) | 1998-04-02 | 2001-09-18 | Oki Electric Industry Co., Ltd | Semiconductor package that includes a shallow metal basin surrounded by an insulator frame |
US6020629A (en) | 1998-06-05 | 2000-02-01 | Micron Technology, Inc. | Stacked semiconductor package and method of fabrication |
US6730544B1 (en) | 1999-12-20 | 2004-05-04 | Amkor Technology, Inc. | Stackable semiconductor package and method for manufacturing same |
US20040219717A1 (en) | 2000-03-09 | 2004-11-04 | Yoshikazu Takahashi | Method of manufacturing chip size package semiconductor device without intermediate substrate |
US20020028327A1 (en) | 2000-05-30 | 2002-03-07 | Perry Charles H. | Conductive polymer interconnection configurations |
US6417462B1 (en) | 2000-06-19 | 2002-07-09 | Intel Corporation | Low cost and high speed 3-load printed wiring board bus topology |
US6881607B2 (en) | 2000-08-08 | 2005-04-19 | Micron Technology, Inc. | Underfill and encapsulation of carrier substrate-mounted flip-chip components using stereolithography |
US7235871B2 (en) | 2000-08-23 | 2007-06-26 | Micron Technology, Inc. | Stacked microelectronic dies |
US8067827B2 (en) | 2000-08-23 | 2011-11-29 | Micron Technology, Inc. | Stacked microelectronic device assemblies |
US6380624B1 (en) | 2000-10-10 | 2002-04-30 | Walsin Advanced Electronics Ltd. | Stacked integrated circuit structure |
US20020098676A1 (en) | 2001-01-24 | 2002-07-25 | Ning Xian J. | Metal hard mask for ild rie processing of semiconductor memory devices to prevent oxidation of conductive lines |
US20080088019A1 (en) | 2001-03-05 | 2008-04-17 | Megica Corporation | Structure and manufacturing method of a chip scale package |
US20030020151A1 (en) | 2001-06-04 | 2003-01-30 | Siliconware Precision Industries Co., Ltd | Thermally-enhanced stacked-die ball grid array semiconductor package and method of fabricating the same |
US6765287B1 (en) | 2001-07-27 | 2004-07-20 | Charles W. C. Lin | Three-dimensional stacked semiconductor package |
US20040036164A1 (en) | 2001-07-31 | 2004-02-26 | Toshihiko Koike | Semiconductor device and its manufacturing method |
US6664644B2 (en) | 2001-08-03 | 2003-12-16 | Seiko Epson Corporation | Semiconductor device and method for manufacturing the same |
US20030032216A1 (en) | 2001-08-08 | 2003-02-13 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and manufacturing method thereof |
US20040238857A1 (en) | 2001-08-28 | 2004-12-02 | Tessera, Inc. | High frequency chip packages with connecting elements |
US6590281B2 (en) | 2001-11-15 | 2003-07-08 | Siliconware Precision Industries Co., Ltd. | Crack-preventive semiconductor package |
KR20030045950A (en) | 2001-12-03 | 2003-06-12 | 삼성전자주식회사 | Multi chip package comprising heat sinks |
US20030110788A1 (en) | 2001-12-19 | 2003-06-19 | Koeneman Paul B. | Method and apparatus for cooling an integrated circuit package using a cooling fluid |
US20030178719A1 (en) | 2002-03-22 | 2003-09-25 | Combs Edward G. | Enhanced thermal dissipation integrated circuit package and method of manufacturing enhanced thermal dissipation integrated circuit package |
US20030218250A1 (en) | 2002-05-27 | 2003-11-27 | Moriss Kung | Method for high layout density integrated circuit package substrate |
US7622324B2 (en) | 2002-09-25 | 2009-11-24 | Ziptronix | Wafer bonding hermetic encapsulation |
US20040067605A1 (en) | 2002-10-02 | 2004-04-08 | Shinko Electric Industries, Co., Ltd. | Semiconductor device having additional functional element and method of manufacturing thereof |
US20040070064A1 (en) | 2002-10-15 | 2004-04-15 | Tae Yamane | Semiconductor device and fabrication method of the same |
US6828665B2 (en) | 2002-10-18 | 2004-12-07 | Siliconware Precision Industries Co., Ltd. | Module device of stacked semiconductor packages and method for fabricating the same |
US20040075164A1 (en) | 2002-10-18 | 2004-04-22 | Siliconware Precision Industries, Ltd. | Module device of stacked semiconductor packages and method for fabricating the same |
US20040089943A1 (en) | 2002-11-07 | 2004-05-13 | Masato Kirigaya | Electronic control device and method for manufacturing the same |
US20050167812A1 (en) | 2003-01-15 | 2005-08-04 | Fujitsu Limited | Semiconductor device, three-dimensional semiconductor device, and method of manufacturing semiconductor device |
US20040155359A1 (en) * | 2003-01-30 | 2004-08-12 | Yu-Nung Shen | Semiconductor device and method for making the same |
CN1543291A (en) | 2003-02-18 | 2004-11-03 | ���µ�����ҵ��ʽ���� | Electronic component built-in module and method of manufacturing the same |
US20040160752A1 (en) | 2003-02-18 | 2004-08-19 | Matsushita Electric Industrial Co. | Electronic component built-in module and method of manufacturing the same |
US20040178499A1 (en) | 2003-03-10 | 2004-09-16 | Mistry Addi B. | Semiconductor package with multiple sides having package contacts |
US20040262811A1 (en) | 2003-06-26 | 2004-12-30 | Semiconductor Components Industries, Llc | Method for making a direct chip attach device and structure |
US20040262774A1 (en) | 2003-06-27 | 2004-12-30 | In-Ku Kang | Multi-chip packages having a plurality of flip chips and methods of manufacturing the same |
US20050006730A1 (en) | 2003-07-07 | 2005-01-13 | Motorola, Inc. | Semiconductor component and method of manufacturing same |
US20060125042A1 (en) | 2003-07-28 | 2006-06-15 | Edward Fuergut | Electronic component and panel for producing the same |
US7180165B2 (en) | 2003-09-05 | 2007-02-20 | Sanmina, Sci Corporation | Stackable electronic assembly |
US20050077626A1 (en) | 2003-10-13 | 2005-04-14 | Jacky Seiller | Forming of the last metallization level of an integrated circuit |
US20070158832A1 (en) | 2003-11-07 | 2007-07-12 | Eiji Takaike | Electronic device and method of manufacturing the same |
US7071568B1 (en) | 2003-11-10 | 2006-07-04 | Amkor Technology, Inc. | Stacked-die extension support structure and method thereof |
US20050133932A1 (en) | 2003-12-19 | 2005-06-23 | Jens Pohl | Semiconductor module with a semiconductor stack, and methods for its production |
US20050156296A1 (en) | 2004-01-02 | 2005-07-21 | Hsueh-Te Wang | Quad flat flip chip package and leadframe thereof |
US7023085B2 (en) | 2004-03-29 | 2006-04-04 | Siliconware Precision Industries Co., Ltd | Semiconductor package structure with reduced parasite capacitance and method of fabricating the same |
US20090115042A1 (en) | 2004-06-04 | 2009-05-07 | Zycube Co., Ltd. | Semiconductor device having three-dimensional stacked structure and method of fabricating the same |
WO2005119776A1 (en) | 2004-06-04 | 2005-12-15 | Zycube Co., Ltd. | Semiconductor device having three-dimensional stack structure and method for manufacturing the same |
US7186588B1 (en) | 2004-06-18 | 2007-03-06 | National Semiconductor Corporation | Method of fabricating a micro-array integrated circuit package |
US20060006517A1 (en) | 2004-07-08 | 2006-01-12 | Lee Jin-Yang | Multi-chip package having heat dissipating path |
US7579691B2 (en) | 2004-08-24 | 2009-08-25 | Sony Corporation | Semiconductor device, substrate, equipment board, method for producing semiconductor device, and semiconductor chip for communication |
US7368811B2 (en) | 2004-10-04 | 2008-05-06 | Samsung Electronics Co., Ltd | Multi-chip package and method for manufacturing the same |
US20060087020A1 (en) | 2004-10-22 | 2006-04-27 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for producing the same |
CN1779971A (en) | 2004-10-22 | 2006-05-31 | 松下电器产业株式会社 | Semiconductor device and method for producing the same |
US20060102994A1 (en) | 2004-11-16 | 2006-05-18 | Siliconware Precision Industries Co., Ltd. | Multi-chip semiconductor package and fabrication method thereof |
US7745918B1 (en) | 2004-11-24 | 2010-06-29 | Amkor Technology, Inc. | Package in package (PiP) |
US20060121718A1 (en) | 2004-12-07 | 2006-06-08 | Yoshihiro Machida | Manufacturing method of chip integrated substrate |
US20060128068A1 (en) | 2004-12-13 | 2006-06-15 | 3M Innovative Properties Company | Methods of using sonication to couple a heat sink to a heat-generating component |
US7261596B2 (en) | 2005-01-05 | 2007-08-28 | Shinko Electric Industries Co., Ltd. | Shielded semiconductor device |
US20060267175A1 (en) | 2005-05-31 | 2006-11-30 | Stats Chippac Ltd. | Stacked Semiconductor Package Assembly Having Hollowed Substrate |
US20060270106A1 (en) | 2005-05-31 | 2006-11-30 | Tz-Cheng Chiu | System and method for polymer encapsulated solder lid attach |
US20080230879A1 (en) | 2005-11-01 | 2008-09-25 | Nirmal Sharma | Methods and apparatus for flip-chip-on-lead semiconductor package |
US7361531B2 (en) | 2005-11-01 | 2008-04-22 | Allegro Microsystems, Inc. | Methods and apparatus for Flip-Chip-On-Lead semiconductor package |
US7615854B2 (en) | 2005-11-03 | 2009-11-10 | International Rectifier Corporation | Semiconductor package that includes stacked semiconductor die |
US20070122940A1 (en) | 2005-11-30 | 2007-05-31 | Viswanadam Gautham | Method for packaging a semiconductor device |
CN1983533A (en) | 2005-11-30 | 2007-06-20 | 飞思卡尔半导体公司 | Method for packaging a semiconductor device |
US20070181990A1 (en) | 2006-02-03 | 2007-08-09 | Siliconware Precision Industries Co., Ltd. | Stacked semiconductor structure and fabrication method thereof |
US7790504B2 (en) | 2006-03-10 | 2010-09-07 | Stats Chippac Ltd. | Integrated circuit package system |
US20070216004A1 (en) | 2006-03-17 | 2007-09-20 | Infineon Technologies Ag | Blank including a composite panel with semiconductor chips and plastic package molding compound and method and mold for producing the same |
US20070254404A1 (en) | 2006-05-01 | 2007-11-01 | Texas Instruments Incorporated | Semiconductor Package-on-Package System Including Integrated Passive Components |
US20070262346A1 (en) | 2006-05-10 | 2007-11-15 | Ralf Otremba | Electronic Component and a Method for its Production |
US7714453B2 (en) | 2006-05-12 | 2010-05-11 | Broadcom Corporation | Interconnect structure and formation for package stacking of molded plastic area array package |
US20070290338A1 (en) | 2006-06-15 | 2007-12-20 | Joseph Kuczynski | Method and Apparatus for Carbon Dioxide Gettering for a Chip Module Assembly |
US20070290376A1 (en) | 2006-06-20 | 2007-12-20 | Broadcom Corporation | Integrated circuit (IC) package stacking and IC packages formed by same |
US7476980B2 (en) | 2006-06-27 | 2009-01-13 | Infineon Technologies Ag | Die configurations and methods of manufacture |
US20080017968A1 (en) | 2006-07-18 | 2008-01-24 | Samsung Electronics Co., Ltd. | Stack type semiconductor package and method of fabricating the same |
US20080029869A1 (en) | 2006-08-01 | 2008-02-07 | Samsung Electronics Co., Ltd. | Vertical stack type multi-chip package having improved grounding performance and lower semiconductor chip reliability |
US7550832B2 (en) | 2006-08-18 | 2009-06-23 | Advanced Semiconductor Engineering, Inc. | Stackable semiconductor package |
US20080054434A1 (en) | 2006-08-31 | 2008-03-06 | Jae Myun Kim | Semiconductor stack package for optimal packaging of components having interconnections |
US20080054437A1 (en) | 2006-09-06 | 2008-03-06 | Samsung Electronics Co., Ltd. | Pop package and method of fabricating the same |
US20080067645A1 (en) | 2006-09-20 | 2008-03-20 | Chee Seng Foong | Heat spreader for semiconductor package |
US20080090405A1 (en) | 2006-09-29 | 2008-04-17 | Tom Fitzgerald | Composite solder TIM for electronic package |
US20100133655A1 (en) | 2006-10-26 | 2010-06-03 | Elpida Memory, Inc. | Semiconductor device having a capacitance element and method of manufacturing the same |
US20080099925A1 (en) | 2006-10-31 | 2008-05-01 | Qimonda Ag | Solder pillar bumping and a method of making the same |
US7550857B1 (en) | 2006-11-16 | 2009-06-23 | Amkor Technology, Inc. | Stacked redistribution layer (RDL) die assembly package |
US20080122059A1 (en) | 2006-11-29 | 2008-05-29 | Advanced Semiconductor Engineering, Inc. | Stacked chip package structure and fabricating method thereof |
US7608921B2 (en) | 2006-12-07 | 2009-10-27 | Stats Chippac, Inc. | Multi-layer semiconductor package |
US7728420B2 (en) | 2006-12-07 | 2010-06-01 | International Rectifier Corporation | High current lead electrode for semiconductor device |
US7880280B2 (en) | 2007-02-16 | 2011-02-01 | Infineon Technologies Ag | Electronic component and method for manufacturing an electronic component |
US20080230898A1 (en) | 2007-03-19 | 2008-09-25 | Spansion Llc | Semiconductor device and method for manufacturing thereof |
US20080284001A1 (en) | 2007-04-13 | 2008-11-20 | Nec Corporation | Semiconductor device and fabrication method |
TW200901411A (en) | 2007-06-20 | 2009-01-01 | Stats Chippac Ltd | Wafer level integration package |
US20080315372A1 (en) | 2007-06-20 | 2008-12-25 | Stats Chippac, Ltd. | Wafer Level Integration Package |
US20080315375A1 (en) | 2007-06-25 | 2008-12-25 | Epic Technologies, Inc. | Integrated conductive structures and fabrication methods thereof facilitating implementing a cell phone or other electronic system |
US20080316714A1 (en) * | 2007-06-25 | 2008-12-25 | Epic Technologies, Inc. | Integrated structures and fabrication methods thereof implementing a cell phone or other electronic system |
US7619901B2 (en) | 2007-06-25 | 2009-11-17 | Epic Technologies, Inc. | Integrated structures and fabrication methods thereof implementing a cell phone or other electronic system |
US20090072368A1 (en) | 2007-08-03 | 2009-03-19 | Kunzhong Hu | Package for monolithic compound semiconductor (csc) devices for dc to dc converters |
US7687899B1 (en) | 2007-08-07 | 2010-03-30 | Amkor Technology, Inc. | Dual laminate package structure with embedded elements |
US20100136749A1 (en) | 2007-08-17 | 2010-06-03 | National Semiconductor Corporation | Microarray package with plated contact pedestals |
US20090079067A1 (en) | 2007-09-26 | 2009-03-26 | Texas Instruments Incorporated | Method for Stacking Semiconductor Chips |
US20090091022A1 (en) | 2007-10-09 | 2009-04-09 | Infineon Technologies Ag | Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device |
US7834464B2 (en) | 2007-10-09 | 2010-11-16 | Infineon Technologies Ag | Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device |
US20090108425A1 (en) * | 2007-10-30 | 2009-04-30 | Samsung Electronics Co. Ltd. | Stacked package and method of manufacturing the same |
US20090127700A1 (en) | 2007-11-20 | 2009-05-21 | Matthew Romig | Thermal conductor lids for area array packaged multi-chip modules and methods to dissipate heat from multi-chip modules |
US20090170241A1 (en) | 2007-12-26 | 2009-07-02 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier |
US20090166886A1 (en) | 2007-12-27 | 2009-07-02 | Kim Youngjoon | Mountable integrated circuit package system with intra-stack encapsulation |
US20090212401A1 (en) | 2008-02-26 | 2009-08-27 | Byung Tai Do | Package system for shielding semiconductor dies from electromagnetic interference |
US20110254155A1 (en) | 2008-03-04 | 2011-10-20 | Stats Chippac, Ltd. | Wafer Level Die Integration and Method Therefor |
US20090224391A1 (en) | 2008-03-04 | 2009-09-10 | Stats Chippac, Ltd. | Wafer Level Die Integration and Method Therefor |
US20090236720A1 (en) | 2008-03-24 | 2009-09-24 | In Sang Yoon | Integrated circuit package system with step mold recess |
US20090278244A1 (en) | 2008-05-12 | 2009-11-12 | Texas Instruments Inc | Ic device having low resistance tsv comprising ground connection |
US7964450B2 (en) | 2008-05-23 | 2011-06-21 | Stats Chippac, Ltd. | Wirebondless wafer level package with plated bumps and interconnects |
US20090302227A1 (en) | 2008-06-09 | 2009-12-10 | Honeywell International Inc. | Neutron Detection Structure |
US20100019362A1 (en) | 2008-07-23 | 2010-01-28 | Manolito Galera | Isolated stacked die semiconductor packages |
US8184453B1 (en) | 2008-07-31 | 2012-05-22 | Amkor Technology, Inc. | Increased capacity semiconductor package |
US20100025829A1 (en) | 2008-07-31 | 2010-02-04 | Infineon Technologies Ag | Semiconductor device |
US20100084749A1 (en) | 2008-10-02 | 2010-04-08 | Advanced Semiconductor Engineering, Inc. | Package and fabricating method thereof |
US7843052B1 (en) | 2008-11-13 | 2010-11-30 | Amkor Technology, Inc. | Semiconductor devices and fabrication methods thereof |
US20100133665A1 (en) * | 2008-11-29 | 2010-06-03 | Jong-Woo Ha | Integrated circuit packaging system with lead frame and method of manufacture thereof |
US7838337B2 (en) | 2008-12-01 | 2010-11-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming an interposer package with through silicon vias |
US20100164078A1 (en) | 2008-12-31 | 2010-07-01 | Ruben Madrid | Package assembly for semiconductor devices |
US20100230792A1 (en) | 2009-03-12 | 2010-09-16 | Scott Irving | Premolded Substrates with Apertures for Semiconductor Die Packages with Stacked Dice, Said Packages, and Methods of Making the Same |
US20100237495A1 (en) | 2009-03-17 | 2010-09-23 | Stats Chippac, Ltd. | Semiconductor Device and Method of Providing Z-Interconnect Conductive Pillars with Inner Polymer Core |
US20100276792A1 (en) | 2009-05-01 | 2010-11-04 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Shielding Layer After Encapsulation and Grounded Through Interconnect Structure |
US20100289126A1 (en) | 2009-05-18 | 2010-11-18 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming a 3D Inductor from Prefabricated Pillar Frame |
US20100289131A1 (en) | 2009-05-18 | 2010-11-18 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Overlapping Semiconductor Die with Coplanar Vertical Interconnect Structure |
US7955942B2 (en) | 2009-05-18 | 2011-06-07 | Stats Chippac, Ltd. | Semiconductor device and method of forming a 3D inductor from prefabricated pillar frame |
US20110204472A1 (en) | 2009-05-18 | 2011-08-25 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming 3D Inductor from Prefabricated Pillar Frame |
US20110024888A1 (en) | 2009-07-31 | 2011-02-03 | Stats Chippac, Ltd. | Semiconductor Device and Method of Mounting Die with TSV in Cavity of Substrate for Electrical Interconnect of FI-POP |
US20110037169A1 (en) | 2009-08-12 | 2011-02-17 | Stats Chippac, Ltd. | Semiconductor Device and Method of Dual-Molding Die Formed on Opposite Sides of Build-Up Interconnect Structures |
US20110037155A1 (en) | 2009-08-12 | 2011-02-17 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Dam Material Around Periphery of Die to Reduce Warpage |
US20110042798A1 (en) | 2009-08-21 | 2011-02-24 | Stats Chippac, Ltd. | Semiconductor Device and Method of Stacking Die on Leadframe Electrically Connected by Conductive Pillars |
US9240380B2 (en) | 2009-08-21 | 2016-01-19 | Stats Chippac, Ltd. | Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect |
US20110068444A1 (en) | 2009-09-23 | 2011-03-24 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Open Cavity in TSV Interposer to Contain Semiconductor Die in WLCSMP |
US20110186977A1 (en) * | 2010-01-29 | 2011-08-04 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Thin Profile WLCSP with Vertical Interconnect over Package Footprint |
US8039384B2 (en) | 2010-03-09 | 2011-10-18 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertically offset bond on trace interconnects on different height traces |
US20110278741A1 (en) | 2010-05-14 | 2011-11-17 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Interconnect Structure and Mounting Semiconductor Die in Recessed Encapsulant |
US20110278707A1 (en) | 2010-05-17 | 2011-11-17 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Prefabricated Multi-Die Leadframe for Electrical Interconnect of Stacked Semiconductor Die |
US8357564B2 (en) | 2010-05-17 | 2013-01-22 | Stats Chippac, Ltd. | Semiconductor device and method of forming prefabricated multi-die leadframe for electrical interconnect of stacked semiconductor die |
US20110291257A1 (en) | 2010-05-27 | 2011-12-01 | Reza Argenty Pagaila | Integrated circuit packaging system with dual side connection and method of manufacture thereof |
US20120038064A1 (en) | 2010-08-16 | 2012-02-16 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Wafer-Level Multi-Row Etched Leadframe With Base Leads and Embedded Semiconductor Die |
US20120193789A1 (en) | 2011-01-27 | 2012-08-02 | Unimicron Technology Corporation | Package stack device and fabrication method thereof |
Cited By (2)
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US20210384153A1 (en) * | 2020-06-09 | 2021-12-09 | Samsung Electronics Co., Ltd. | Semiconductor package |
US11710715B2 (en) * | 2020-06-09 | 2023-07-25 | Samsung Electronics Co., Ltd. | Semiconductor package |
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