USRE44410E1 - Charge comparator with low input offset - Google Patents
Charge comparator with low input offset Download PDFInfo
- Publication number
- USRE44410E1 USRE44410E1 US12/322,658 US32265809A USRE44410E US RE44410 E1 USRE44410 E1 US RE44410E1 US 32265809 A US32265809 A US 32265809A US RE44410 E USRE44410 E US RE44410E
- Authority
- US
- United States
- Prior art keywords
- charge
- output
- input
- pair
- sample
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
- G11C19/282—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements with charge storage in a depletion layer, i.e. charge coupled devices [CCD]
- G11C19/285—Peripheral circuits, e.g. for writing into the first stage; for reading-out of the last stage
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
- G11C27/02—Sample-and-hold arrangements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
- G11C27/02—Sample-and-hold arrangements
- G11C27/024—Sample-and-hold arrangements using a capacitive memory element
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
- H03F3/45928—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit
- H03F3/45968—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit by offset reduction
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
- H03K5/249—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors using clock signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/78—A comparator being used in a controlling circuit of an amplifier
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45614—Indexing scheme relating to differential amplifiers the IC comprising two cross coupled switches
Definitions
- the present invention relates to charge comparators, especially those which may be used with Charge Coupled Device (CCD) pipeline-based structures.
- CCD Charge Coupled Device
- Circuits for performing signal processing functions are now common in numerous consumer devices such as digital cameras, cellular telephones, wireless data network equipment, audio devices such as MP3 players, video equipment such as Digital Video Disc (DVD) players, High Definition Digital Television (HDTV) equipment and numerous other products. It is well known that Charge Coupled Devices (CCDs) circuits may be used to implement many of the signal processing functions required in such products.
- CCDs Charge Coupled Devices
- QDC Charge to Digital
- One way to implement a QDC is as a successive approximation type converter that includes a number of charge storage stages arranged as a serial pipeline register.
- the input signal voltage is typically represented as a pair of complimentary charges which are processed in positive (plus) and negative (minus) signal paths.
- the complimentary input charges pass from stage to stage down respective pipelines dedicated to processing the plus and minus signals.
- the reference charge comparator compares an input charge amount to a reference charge amount, and then optionally adds a reference charge amount to each charge as it travels through the stage.
- the invention is a Direct Current (DC) charge comparator that provides low input offset. Low offset is achieved through a single final amplification path using an alternate path switch and a track and hold input circuits.
- DC Direct Current
- the two complimentary charge inputs are each first fed to a cross point switch.
- the switch In a first state, the switch sends the input plus signal charge down a first path to first output and the minus signal charge down a second path to a second output. This is called the “non-inverted” condition.
- the state of the switch is swapped, so that the plus charge travels down a path to the second output, and so that the minus charge down a path to the first output. This is called the “inverted” condition of the switch.
- the charges appearing at each switch output are then integrated, and the integrated outputs are then sampled and stored, such as by storage capacitors.
- the storage capacitors can be precharged to a preset voltage before the switch state is swapped and the output sampled and stored again. These outputs are preferably tracked by a sample and hold circuit, to avoid spikes close to the comparator decision times.
- the output of the sample and hold circuit is then typically amplified before further processing.
- the circuit thus provides a pair of outputs, in each of two different states.
- One pair of output represents the amplified and sampled plus and minus inputs in the non-inverted switch state, and another pair of outputs represents the amplified and sampled plus and minus inputs in the inverted switch state.
- the input offset is amplified in the same way for both the inverted and non-inverted switch conditions, the input offset is effectively cancelled by the difference amplifier. As a result, any input charge differences are more accurately determined.
- FIG. 1 is a high level diagram of a Charge to Digital (QDC) converter that may use a DC sensor according the present invention.
- QDC Charge to Digital
- FIG. 2 is a more detailed block diagram of the DC sensor.
- FIG. 3 is a detailed circuit diagram of portions of the DC sensor.
- FIG. 4 is a timing diagram for the DC sensor.
- FIG. 1 is a block diagram of device 10 that may use a Direct Current (DC) sensor 20 according to the present invention.
- the illustrated device 10 is a Charge to Digital converter (QDC), but it should be understood that the DC sensor 20 may be used in other types of circuits adopted for processing charge packets.
- QDC Charge to Digital converter
- QDC 10 is a so-called successive approximation type converter that uses a number of charge storage stages arranged as a serial pipeline register.
- an input source charge passes from stage to stage along the pipeline.
- a reference charge generator and a charge splitter connected to each stage generate a reference charge signal for that stage.
- the reference charge signal is then optionally added to the charge as it travels down the pipeline, depending upon the comparison result.
- the illustrated circuit there are actually two pipelines. That is, charges are carried in the circuit as complimentary pairs, which correspond to a complimentary representation of the input signals.
- the overall operation of QDC 10 is similar to the QDC described in U.S. Pat. No. 5,579,007 issued to Paul.
- an input voltage is presented as a complimentary pair of voltages, VinP and VinM, representing a positive (plus) and a negative (minus) version of the input signal to be converted.
- Switches 22 -P and 22 -M one for each of the plus and minus paths, provide the selected input signal to a corresponding sampler 23 -P and 23 -M.
- the samplers 23 each convert their respective input voltage to a charge.
- the charges output by the samplers 23 are then fed to an input stage of a respective charge pipeline 24 -P, 24 -M.
- the charge pipelines 24 may each use a Charge Coupled Device (CCD) analog shift register.
- CCD Charge Coupled Device
- the plus and minus paths through the converter 10 also have a respective Digital to Analog (DAC) ladder 27 -P, 27 -M.
- DAC Digital to Analog
- the DC sensor 20 is used for comparing the output charge from plus CCD pipeline 24 -M to the output of minus CCD pipeline 24 -P calibrates the circuit 10 in such a way that a low input offset is provided.
- the basic idea is to provide a circuit that determines a difference between the charges provided in the complimentary charge paths, by periodically swapping the connection between the inputs and the comparison circuits.
- FIG. 2 shows one embodiment of DC sensor 20 in more detail.
- DC sensor 20 consists of an input cross point (A/B) switch 210 , integrators 220 -A, 220 -B, prechargers 221 -A, 221 -B, amplifier 215 , sampling switches, 222 -A- 1 , 222 -A- 2 , 222 -B- 1 , 222 -B- 2 , sampling capacitors 223 -A- 1 , 223 -A- 2 , 223 -B- 1 , 223 -B- 2 and output difference amplifier 225 .
- A/B input cross point
- Positive and negative charges, Q M , Q P such as may be provided by the CCD pipelines 24 -P, 24 -M are first received at the switch 210 .
- the charges may be input at a relatively high clock rate of, for example, 100 Megahertz (MHz) or higher.
- the switch 210 allows for either the plus charge Q M or the minus charge Q P to be fed to the respective switch 210 output port A or B.
- the switch 210 feeds Q M to output A and Q P to output B; in the other, or “inverted” state, switch 210 feeds charge Q P to output A and Q M to output B.
- the A/B state or mode of the switch is changed at a rate which is somewhat slower than the input sample rate.
- the A/B toggle rate may be 1/48 th of the input charge sample rate.
- the respective outputs of the switch 210 therefore are a series of charges that for a length of time correspond to the signal charges provided on input Q M , followed by a series of the signal charges provided on input Q P for a subsequent length of time, then followed again by a series of the charges on input Q M , then the Q P charges again, etc.
- the switch outputs A and B can thus be thought of as having two states—a normal or “non-inverted” state when the switch 210 is in one position, and an inverted state when the switch is 210 is in the other position.
- integrator 220 -A, 220 -B associated with each of the A and B outputs.
- the integrators 220 are of the pre-chargeable type such that they are recharged to a preset voltage by the respective pre-charger 221 before each cycle of operation.
- An amplifier 215 provides amplified versions of the integrator outputs for further processing.
- the integrator outputs are amplified and then fed to a set of four sampling switches 222 -A- 1 , 222 -A- 2 , 222 -B- 1 , 222 -B- 2 and four sampling capacitors 223 -A- 1 , 223 -A- 2 , 223 -B- 1 , and 223 -B- 2 .
- sampling switch 222 and corresponding capacitor 223 for storing each possible combination of switch state and input signal path—that is separate a sampling switch is provided for storing the integration result when (1) charge Q P is coupled to switch port A, (2) charge Q M is coupled to switch port B, (3) charge Q P is coupled to switch port B, and (4) charge Q M is coupled to switch port A.
- the resulting pair of differential, sampled charges (carried on the four capacitor ouputs) are then compared using the differential difference amplifier 225 . Since the input offset is amplified the same way for both the inverted and non-inverted input charge conditions (i.e., for both modes of the switch 210 ) any difference is effectively cancelled by the difference amplifier 225 . Therefore, only the input charges themselves end up being compared, and any input offset is cancelled.
- the output of the difference amplifier which may be a digital bit, can then be fed back to control circuits such as a reference charge input, or calibration circuits.
- FIG. 3 A more detailed circuit diagram of certain portion of the DC charge comparator 20 is shown in FIG. 3 .
- the input switch 210 , integrator pre-charge circuits 221 , integrating capacitors 223 , as well as a first stage of amplifier 220 are shown in much greater detail in this drawing.
- the input chargers Q P and Q M are fed to a respective portions of the input switch 210 .
- the input switch 210 consists of four transistors arranged in pairs.
- the first transistor pair 310 - 1 and 310 - 2 are coupled to receive the plus charge Q P
- transistor pair 311 - 1 and 311 - 2 are arranged to receive the minus charge Q M .
- the transistor pairs select their respective input charges to be passed along one of two outputs, either drain P 1 or drain M 1 .
- a precharge circuit 221 is used to precharge the integrating capacitors.
- precharge circuit 221 consists of a pair of transistors 313 - 1 , 313 - 2 that respectively receive the drain P 1 and drain M 1 signals.
- the gates terminals of these transistors 313 are controlled by a clock input K PCH that determines the precharger state.
- Integrating capacitors 314 are arranged to be fed to be coupled to the source terminals of respective transistors 313 - 1 and 313 - 2 . Although four (4) capacitors are shown (with a pair of capacitors being necessary to provide the required capacitance for each path) other configurations for capacitors 314 are possible.
- the integrated signals are then fed to an amplifier 215 in the preferred embodiment they are first fed, however, through a preamplifier 318 .
- the preamplifier 318 consists of a pair of transistors 320 - 1 , 320 - 2 for amplifying each of the respective signal paths.
- a reference voltage may be provided to control these preamplifiers 318 via reference stages 322 - 1 , 322 - 2 .
- V IM1 and V IP1 represent the plus and minus signal paths after they have been sampled and held and after they have been subjected to the operation of the input switch 210 .
- signal V IM1 will for a period of time have a value associated with it that depends on the value of the input charge Q P , and for a period of time then correspond to the value of input charge Q M .
- V IP1 will for a time have a value that depends upon input charge Q M , and then take on a value for a period of time that depends on input charge Q P .
- FIG. 4 is a set of timing diagrams that further explain the operation of the DC charge comparator circuit 20 .
- the top signal trace 40 represents the A/B state of the mode switch 210 .
- integrator A 220 -A
- the output of integrator A is shown in signal trace 41 .
- the switch set in the A mode after being pre-charged at time T 1 , the integrator output will slowly ramp down as each successive charge is fed through the pipeline.
- a time T 2 is reached that corresponds to the rising edge of a clock signal fed to the sampling switch 222 .
- the remaining charge on the integrator 220 -A is approximately 2.2 volts.
- This voltage will then be stored by the sampling capacitor 223 -A- 1 so that its output, Q A-1 , is also set to 2.2 volts, as shown in trace 44 .
- the integrator 220 -B for signal path B will be pre-charged at time T 1 and gradually reach a particular voltage at time T 2 .
- This final voltage will be different for the B path, at 2.1 volts for example, due to the difference on charge Q M .
- This voltage will be stored in the capacitor 223 -B- 1 as output Q B-1 as shown in trace 45 .
- the comparator output signal 48 will stay at a logic 1 or high logic state. The signal can then be fed back to the microprocessor 30 to effect an adjustment to the reference charge generators 25 -P, 25 -M to increase the level of Q M .
- Q M is increased to a level larger than Q P
- the comparator output will switch to logic 0 or low state.
- FIG. 2 it is suggested by FIG. 2 that adjustments will be made such that the charge Q M is gradually increased from 39 fc up to 40 fc, eventually reaching a point where the two input charges are equal.
- a redirecting switch or “chopper” to feed a pair of integrators, to compare the integrator result at a first time with that as of a second time.
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Analogue/Digital Conversion (AREA)
- Measurement Of Current Or Voltage (AREA)
Abstract
Description
Claims (21)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/322,658 USRE44410E1 (en) | 2004-07-06 | 2009-02-05 | Charge comparator with low input offset |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US58561104P | 2004-07-06 | 2004-07-06 | |
US11/175,994 US7173558B2 (en) | 2004-07-06 | 2005-07-06 | Charge comparator with low input offset |
US12/322,658 USRE44410E1 (en) | 2004-07-06 | 2009-02-05 | Charge comparator with low input offset |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/175,994 Reissue US7173558B2 (en) | 2004-07-06 | 2005-07-06 | Charge comparator with low input offset |
Publications (1)
Publication Number | Publication Date |
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USRE44410E1 true USRE44410E1 (en) | 2013-08-06 |
Family
ID=35787626
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
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US11/175,994 Ceased US7173558B2 (en) | 2004-07-06 | 2005-07-06 | Charge comparator with low input offset |
US12/322,658 Expired - Fee Related USRE44410E1 (en) | 2004-07-06 | 2009-02-05 | Charge comparator with low input offset |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
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US11/175,994 Ceased US7173558B2 (en) | 2004-07-06 | 2005-07-06 | Charge comparator with low input offset |
Country Status (2)
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US (2) | US7173558B2 (en) |
WO (1) | WO2006014500A2 (en) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7358876B1 (en) * | 2006-02-02 | 2008-04-15 | Marvell International Ltd. | Mixed-mode analog offset cancellation for data conversion systems |
US8587465B2 (en) | 2011-10-11 | 2013-11-19 | International Business Machines Corporation | Successive approximation analog to digital converter with comparator input toggling |
US8618965B2 (en) | 2011-12-28 | 2013-12-31 | St-Ericsson Sa | Calibration of a charge-to-digital timer |
US9379729B2 (en) | 2011-12-28 | 2016-06-28 | St-Ericsson Sa | Resistive/residue charge-to-digital timer |
US8659360B2 (en) | 2011-12-28 | 2014-02-25 | St-Ericsson Sa | Charge-to-digital timer |
US20190050012A1 (en) * | 2017-08-10 | 2019-02-14 | Macronix International Co., Ltd. | Voltage regulator with improved slew rate |
JP2020198524A (en) * | 2019-05-31 | 2020-12-10 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4121248A (en) | 1977-03-07 | 1978-10-17 | Texas Instruments Incorporated | Streak reduction system for FLIR display |
US5008698A (en) | 1987-09-28 | 1991-04-16 | Kyocera Corporation | Control apparatus for image sensor |
US5661397A (en) | 1995-09-22 | 1997-08-26 | H. R. Textron Inc. | Demodulator circuit for determining position, velocity and acceleration of displacement sensor independent of frequency or amplitude changes in sensor excitation signal |
US5754056A (en) | 1996-04-23 | 1998-05-19 | David Sarnoff Research Center, Inc. | Charge detector with long integration time |
US5929800A (en) | 1996-08-05 | 1999-07-27 | California Institute Of Technology | Charge integration successive approximation analog-to-digital converter for focal plane applications using a single amplifier |
US6355926B1 (en) | 1999-08-13 | 2002-03-12 | Xerox Corporation | Raster output scanner beam steering |
US6788563B2 (en) | 2000-08-24 | 2004-09-07 | Thin Film Electronics Asa | Sensing device for a passive matrix memory and a read method for use therewith |
-
2005
- 2005-07-06 US US11/175,994 patent/US7173558B2/en not_active Ceased
- 2005-07-06 WO PCT/US2005/024007 patent/WO2006014500A2/en active Application Filing
-
2009
- 2009-02-05 US US12/322,658 patent/USRE44410E1/en not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4121248A (en) | 1977-03-07 | 1978-10-17 | Texas Instruments Incorporated | Streak reduction system for FLIR display |
US5008698A (en) | 1987-09-28 | 1991-04-16 | Kyocera Corporation | Control apparatus for image sensor |
US5661397A (en) | 1995-09-22 | 1997-08-26 | H. R. Textron Inc. | Demodulator circuit for determining position, velocity and acceleration of displacement sensor independent of frequency or amplitude changes in sensor excitation signal |
US5754056A (en) | 1996-04-23 | 1998-05-19 | David Sarnoff Research Center, Inc. | Charge detector with long integration time |
US5929800A (en) | 1996-08-05 | 1999-07-27 | California Institute Of Technology | Charge integration successive approximation analog-to-digital converter for focal plane applications using a single amplifier |
US6355926B1 (en) | 1999-08-13 | 2002-03-12 | Xerox Corporation | Raster output scanner beam steering |
US6788563B2 (en) | 2000-08-24 | 2004-09-07 | Thin Film Electronics Asa | Sensing device for a passive matrix memory and a read method for use therewith |
Also Published As
Publication number | Publication date |
---|---|
WO2006014500A3 (en) | 2006-07-20 |
US20060017603A1 (en) | 2006-01-26 |
US7173558B2 (en) | 2007-02-06 |
WO2006014500A2 (en) | 2006-02-09 |
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