USRE42349E1 - Wafer treating method for making adhesive dies - Google Patents

Wafer treating method for making adhesive dies Download PDF

Info

Publication number
USRE42349E1
USRE42349E1 US11/371,307 US37130706A USRE42349E US RE42349 E1 USRE42349 E1 US RE42349E1 US 37130706 A US37130706 A US 37130706A US RE42349 E USRE42349 E US RE42349E
Authority
US
United States
Prior art keywords
wafer
adhesive
dies
die
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US11/371,307
Inventor
Chun-Hung Lin
Jesse Huang
Kuang-Hui Chen
Shih-Wen Chou
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chipmos Technologies Inc
Original Assignee
Chipmos Technologies Bermuda Ltd
Chipmos Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipmos Technologies Bermuda Ltd, Chipmos Technologies Inc filed Critical Chipmos Technologies Bermuda Ltd
Priority to US11/371,307 priority Critical patent/USRE42349E1/en
Application granted granted Critical
Publication of USRE42349E1 publication Critical patent/USRE42349E1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83856—Pre-cured adhesive, i.e. B-stage adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92147—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92162—Sequential connecting processes the first connecting process involving a wire connector
    • H01L2224/92165—Sequential connecting processes the first connecting process involving a wire connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06575—Auxiliary carrier between devices, the carrier having no electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention is generally relating to a wafer treating technique after finishing integrated circuits on a wafer, particularly to a wafer treating method for making adhesive dies.
  • a plurality of dies are singulated from the semiconductor wafer and according to various packaging styles are attached on a proper IC substrate, or one of dies is attached one on top of the other die to form multi-chip stack.
  • Die is attached onto a printed circuit board to form Ball Grid Array (BGA) package.
  • Die is attached to die pad or inner leads of a lead frame to form Thin Small Outline Package (TSOP).
  • Conventional adhesive for die-attaching is thermosetting silver liquid compound or solid polyimide adhesive tape, which is applied on base carrier (e.g., substrate, leadframe or lower die) during die-attaching.
  • a method for assembling multi-chip module disclosed from U.S. Pat. No. 2001/0005935 is to attach a larger die onto a substrate using a die attach machine, then a smaller die is affixed on the larger die without using a die attach machine.
  • the adhesive attaching the larger die and the smaller die conventionally is a liquid thermosetting adhesive or solid polyimide tape.
  • that is failed to disclose the procedure of coating the adhesive firstly coated on the smaller die or on the larger die prior to die-attaching and the procedure of wire-bonding.
  • a solid adhesive tape may also be used for die-attaching, but cost of adhesive tape is high and the adhesive tape is demanded double-sided adhesive for die-to-die, die-to-substrate or die-to-leadframe bonding.
  • the adhesive tape is firstly attached on a substrate (leadframe or larger die) in predetermined pattern, then a die is bonded on the adhesive tape. The dies do not have adhesive after sigulating from a wafer.
  • a first object of the present invention is to provide a wafer treating method for making adhesive dies by utilizing a liquid adhesive with two-stage property printed on a wafer.
  • the printed adhesive with two-stage property is pre-cured to become solid without flowable and adhesive under room temperature (B-stage condition), then after singulating the wafer, a plurality of dies with B-stage adhesive will be obtained for decreasing cost of forming adhesive.
  • a second object of the present invention is to provide a wafer treating method for making adhesive dies by utilizing a liquid adhesive with two-stage property printed on a wafer.
  • the adhesive with two-stage property is precured to become solid film without flowable and adhesive under room temperature (B-stage condition), then after singulating the wafer, the dies with B-stage adhesive will be obtained, so as to possess good processing characteristic for a variety of semiconductor packaging processes.
  • a semiconductor wafer having integrated circuits is provided.
  • the wafer has a plane surface, such as an active surface or an inactive surface.
  • a liquid adhesive with two-stage property is evenly coated on the partial or overall surface of the wafer by means of screen printing, stencil printing or spin coating. It is desirable to coat the liquid adhesive with two-stage property on the partial surface of the wafer without covering the cutting paths or bonding pads of the wafer.
  • the wafer is pre-cured to make the adhesive with two-stage property become a wafer-level thermo-bonding adhesive film with B-stage property, that is, being solid without flowable and adhesive under room temperature.
  • the pre-cured time is about 1 hour around 125° C.
  • the B-stage solid film has thermosetting property and adhesion of thermal bonding, also has a glass transition temperature (Tg) more than 40° C. for operation of positioning the wafer, sucking the dies utilizing a die binder and transportation after singulating the dies from the wafer.
  • Tg glass transition temperature
  • the dies with wafer-level thermo-bonding adhesive film are provided to affix to a substrate, another die, a printed circuit board, a ceramic circuit board or a lead frame without extra adhesive. Therefore, the dies with wafer-level thermo-bonding adhesive film are able to be efficiently, broadly used in die-to-die stack or die-to-substrate attach for various packages at low cost.
  • the present invention is directed to a chip package comprising a carrier, a first chip, a first adhesive layer and a molding compound.
  • the first chip is disposed on the carrier and electrically connected with the carrier.
  • the first adhesive layer is disposed between the carrier and the first chip, wherein an area of the first adhesive layer is not larger than an area of the first chip.
  • the molding compound is disposed on the carrier to cover the first chip.
  • the chip package further comprises a plurality of first bonding wires, which are electrically connected with the carrier and the first chip.
  • the first adhesive layer can be an adhesive film, wherein the adhesive film can be an adhesive film having B-stage property.
  • the carrier is a package substrate or a lead frame.
  • the chip package further comprises a second adhesive layer and a second chip, wherein the second adhesive layer is disposed on the first chip and the second chip is disposed on the second adhesive layer. And wherein an area of the second adhesive layer is not larger than an area of the second chip and the second chip is electrically connected with the carrier.
  • the chip package further comprises a plurality of second bonding wires, which are electrically connected with the carrier and the second chip.
  • the second bonding wires and the second chip are covered with the molding compound.
  • the second adhesive layer is disposed between an inactive surface of the second chip and an active surface of the first chip.
  • the second adhesive layer can be an adhesive film.
  • the second adhesive layer can be an adhesive film having B-stage property.
  • the present invention is directed to a chip package comprising a carrier, a first chip, a second chip, a second adhesive layer and a molding compound.
  • the first chip is disposed on the carrier and electrically connected with the carrier.
  • the second chip is disposed on the first chip and electrically connected with the carrier.
  • the second adhesive layer is disposed between the first chip and the second chip, wherein an area of the second adhesive layer is not larger than an area of the second chip.
  • the molding compound is disposed on the carrier to cover the first chip, the second chip, and the second adhesive layer.
  • the chip package further comprises a plurality of first bonding wires, which are electrically connected with the carrier and the first chip.
  • the chip package further comprises a plurality of second bonding wires, which are electrically connected with the carrier and the second chip.
  • the second adhesive layer can be an adhesive film.
  • the second adhesive layer can be an adhesive film having B-stage property.
  • the chip package further comprises a first adhesive layer, which is disposed between the carrier and the first chip.
  • the first adhesive layer can be an adhesive film.
  • the first adhesive layer can be an adhesive film having B-stage property.
  • the carrier is a package substrate or a lead frame.
  • the second adhesive layer is disposed between an inactive surface of the second chip and an active surface of the first chip.
  • FIG. 1 is a flow chart of a wafer treating method for making adhesive dies in accordance with the present invention.
  • FIG. 2 is a front view of a provided wafer in accordance with a wafer treating method for making adhesive dies of the present invention.
  • FIG. 3A to FIG. 3D are cross-sectional views of a wafer in wafer treating process in accordance with a first embodiment of the present invention.
  • FIG. 3E to FIG. 3F are cross-sectional views of an adhesive die made from the first embodiment in die-to-die stack.
  • FIG. 4A to FIG. 4D are cross-sectional views of a wafer in wafer treating process in accordance with a second embodiment of the present invention.
  • FIG. 4E to FIG. 4F are cross-sectional views of an adhesive die made from the second embodiment in die-to-substrate package.
  • FIG. 5 is a cross-sectional view illustrating the inactive surface of wafer attached to a position tape for singulation to make adhesive dies in accordance with a third embodiment of the present invention.
  • FIG. 6 and FIG. 7 are cross-sectional views illustrating an adhesive die made from the third embodiment in die-to-leadframe package.
  • the wafer treating method for making adhesive dies according to the present invention comprises the main steps of “providing a wafer” 11 , “coating a liquid adhesive with two-stage property” 12 , “pre-curing the wafer” 13 , “positioning the wafer” 14 and “singulating the wafer to form dies with wafer-level thermo-bonding adhesive film” 15 .
  • a wafer 110 is provided.
  • the wafer 110 has an active surface 112 which had formed integrated circuits and bonding pads 115 , an inactive surface 111 corresponding to the active surface 112 in order to integrate a plurality of dies 113 together.
  • the bonding pads 115 are located on each die 113 .
  • a surface of the wafer 110 for required to being adhesive is active surface 112 or inactive surface 111 .
  • the inactive surface 111 of the wafer 110 is predetermined to be adhesive, the inactive surface 111 should face upward.
  • the step of “coating a liquid adhesive with two-stage property” 12 is executed, as shown in FIG. 3B .
  • a liquid adhesive 130 having at least two-stage property (A-stage, B-stage, C-stage) is coated on partially or totally inactive surface 111 of the wafer 110 by screen printing, stencil printing or spin coating.
  • a screen 121 is placed on the inactive surface 111 of the wafer 110 , then the liquid adhesive 130 with proper flowability is printed on the inactive surface 111 by a scraper 122 .
  • the screen 121 covers the cutting paths 114 of the wafer 110 so that the adhesive 130 with two-stage property is partially printed on the inactive surface 111 of the wafer 110 without covering the cutting paths 114 .
  • the printed thickness of the adhesive 130 with two-stage property is about 3 ⁇ 6 mil and depends on the screen 121 .
  • the adhesive 130 with two-stage property includes thermosetting resin or polymer such as polyimide, polyquinolin or benzocyclobutene and solvent that enable dissolution of mentioned-above thermosetting resin such as mix-solvent of butyrolactone and cyclopentanone or 1,3,5-mesitylene, etc. Since the liquid adhesive 130 with two-stage property has A-stage property while coated, the liquid adhesive 130 is fluid enough to be printed.
  • the step of “pre-curing the wafer” 13 is executed as shown in FIG. 3C .
  • the wafer 130 is placed in an oven to be heated at a proper temperature (90 ⁇ 150° C. approximately) for 1 hour for removing solvent.
  • the pre-curing procedure is to remove the solvent of the liquid adhesive 130 with two-stage property, so that the printed liquid adhesive 130 transforms a wafer-level thermo-bonding adhesive film 131 .
  • the pre-curing step 13 is executed by vacuum drying.
  • the wafer-level thermo-bonding adhesive film 131 is solid and has a thickness between 3 ⁇ 8 mil for die-to-die stacking, preferably between 5 ⁇ 6 mil.
  • the wafer-level thermo-bonding adhesive film 131 becomes adhesive when operating temperature is more than its glass transition temperature (Tg), that is to say, the wafer-level thermo-bonding adhesive film 131 possesses B-stage condition and also has thermosetting property.
  • Tg glass transition temperature
  • the glass transition temperature of the wafer-level thermo-bonding adhesive film 131 is not less than 40° C. (Tg ⁇ 40° C.). Therefore, the wafer 110 with the wafer-level thermo-bonding adhesive film 131 is easy to handle, transport under normal room temperature.
  • the step of “positioning the wafer” 14 is executed as shown in FIG. 3D , the wafer 110 is turned over to make the inactive surface 111 facing downward and attached to a positioning tape 140 .
  • the positioned tape 140 is a wafer positioning tape such as polyvinyl chloride, which has adhesive and is attached to a metal frame with circular opening for wafer-dicing procedure.
  • the wafer-level thermo-bonding adhesive film 131 attaches on the positioning tape 140 by the adhesive of the positioning tape 140 .
  • the step of “singulating the wafer to form dies with wafer-level thermo-bonding adhesive film” 15 is executed that is along the cutting paths 114 to dice the wafer 110 by using the dicer 150 (laser or diamond cutting tool) of wafer-dicing machine to form a plurality of dies 113 with wafer-level thermo-bonding adhesive film 131 .
  • the adhesive dies 113 not only can be rapidly provided at low cost but also can be used in die-to-die stacks or other various packages. For example, as shown in FIG.
  • the thermal compression temperature and time do not make the wafer-level thermo-bonding adhesive film 131 finish the thermosetting reaction after die-to-die attaching.
  • the bonding wires 180 are wire-bonded to electrically connect the bonding pads 115 of the die 113 with the substrate 170 .
  • the wafer treating method for making adhesive dies of the present invention is applicable not only for die-to-die stacking but also for the-to-substrate and die-to-leadframe attaching for various packages.
  • a layer of liquid adhesive 130 with two-stage property is completely coated on all of the inactive surface 111 of a wafer 110 by spin coating or printing method, then passing through pre-curing step 13 , positioning step 14 and singulating step 15 , a plurality of dies 113 with wafer-level thermo-bonding adhesive film 131 on the inactive surface thereof are formed for die-to-substrate attaching.
  • the wafer-level thermo-bonding adhesive film 131 has higher viscous and handling-easier than conventional silver liquid paste so that the contact pads of substrate can be closer to the adhesive die 113 for making chip scale package (CSP).
  • a wafer 210 is provided.
  • the wafer 210 has an active surface 211 having a plurality of bonding pads 215 (or bumps) and an inactive surface 212 corresponding to the active surface 211 to integrate a plurality of dies 213 .
  • the bonding pads 215 are located at the center of each die 213 and the active surface 211 faces upward.
  • a liquid adhesive 230 with two-stage property is formed on the active surface 211 by screen printing or stencil printing method.
  • a screen 221 is put on the active surface 211 of the wafer 210 , then the liquid adhesive 230 with two-stage property is printed on the active surface 212 by a scraper 222 .
  • the screen 221 covers the bonding pads 215 of the wafer 210 , the liquid adhesive 230 with two-stage property is partially printed on the active surface 212 of the wafer 210 with predetermined pattern, the thickness thereof is about 1 ⁇ 3 mil.
  • the wafer 210 is pre-cured to remove solvent in the liquid adhesive 230 with two-stage property on the active surface 211 of the wafer 210 so as to transform a wafer-level thermo-bonding adhesive film 231 .
  • the wafer-level thermo-bonding adhesive film 231 has B-stage property and has a glass transition temperature (Tg) not less than 40° C., so that the wafer-level thermo-bonding adhesive film 231 doesn't possess adhesive under the normal room temperature for being portable, movable and storable and also possesses thermo-bonding adhesive.
  • Tg glass transition temperature
  • the wafer 210 After the wafer 210 is positioned, it is diced along the cutting paths 214 by a dicer 250 to form a plurality of dies 213 with wafer-level thermo-bonding adhesive film 231 on the active surface 211 .
  • the adhesive dies 213 not only can be rapidly provided at low cost but also can be utilized in various packages.
  • the die 213 with wafer-level thermo-bonding adhesive film 231 is sucked by a die attach machine and is affixed to a substrate 260 such as a printed circuit board or ceramic circuit substrate.
  • the die 213 can be quickly attached to a substrate at the thermal bonding temperature around 120° C.-175° C. even in few seconds.
  • the adhesive strength between substrate 260 and die 213 is provided by means of the wafer-level thermo-bonding adhesive film 231 at the thermal bonding temperature. Also, a BGA package can be fabricated after executing the steps of forming bonding-wire 262 , the molding package body 263 and the solder balls 261 (as shown in FIG. 4F ).
  • the process steps are the same as those illustrated in the second embodiment shown in FIG. 4A to FIG. 4C .
  • the inactive surface 212 of the wafer 210 is directly positioned to a position tape 240 .
  • the active surface 211 of the wafer 210 faces upward and is singulated to form a plurality of die 213 by dicer 250 .
  • FIG. 5 shows that the inactive surface 212 of the wafer 210 is directly positioned to a position tape 240 .
  • the active surface 211 of the wafer 210 faces upward and is singulated to form a plurality of die 213 by dicer 250 .
  • the dies 213 with wafer-level thermo-bonding adhesive film 231 are sucked on a carrier 272 , then the inner leads 271 of a LOC (Lead-On-Chip) lead frame are attached downward to the active surface 211 of the die 213 .
  • the wafer-level thermo-bonding adhesive film 231 becomes adhesive to adhere the die 213 and the inner leads 271 of leadframe.
  • bonding wires 274 , molding compound 273 are formed to manufacture a package of TSOP (Thin Small Outline Package) or QFP (Quad Flat Package). Therefore, according to the wafer treating method for making adhesive dies of the present invention, the dies 213 with wafer-level thermo-bonding adhesive film 231 can be massively manufactured at low cost for die-to-leadframe package.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)

Abstract

A wafer treating method for making adhesive dies is provided. A liquid adhesive with two-stage property is coated on a surface of a wafer. Then, the wafer is pre-cured to make the liquid adhesive transform a thermo-bonding adhesive film having B-stage property which has a glass transition temperature not less than 40° C. for handling without adhesive under room temperature. After positioning the wafer, the wafer is singulated to form a plurality of dies with adhesive for die-to-die stacking, die-to-substrate or die-to-leadframe attaching.

Description

FIELD OF THE INVENTION
The present invention is generally relating to a wafer treating technique after finishing integrated circuits on a wafer, particularly to a wafer treating method for making adhesive dies.
BACKGROUND OF THE INVENTION
After manufacturing the integrated circuits on a semiconductor wafer, a plurality of dies are singulated from the semiconductor wafer and according to various packaging styles are attached on a proper IC substrate, or one of dies is attached one on top of the other die to form multi-chip stack. Die is attached onto a printed circuit board to form Ball Grid Array (BGA) package. Die is attached to die pad or inner leads of a lead frame to form Thin Small Outline Package (TSOP). Conventional adhesive for die-attaching is thermosetting silver liquid compound or solid polyimide adhesive tape, which is applied on base carrier (e.g., substrate, leadframe or lower die) during die-attaching.
A method for assembling multi-chip module disclosed from U.S. Pat. No. 2001/0005935 is to attach a larger die onto a substrate using a die attach machine, then a smaller die is affixed on the larger die without using a die attach machine. The adhesive attaching the larger die and the smaller die conventionally is a liquid thermosetting adhesive or solid polyimide tape. However, that is failed to disclose the procedure of coating the adhesive (firstly coated on the smaller die or on the larger die prior to die-attaching and the procedure of wire-bonding. On one hand, when a liquid thermosetting adhesive is used for die-attaching prior wire-bonding, it is difficult to pre-coat on the smaller die (upper die) and also easy to contaminate the bonding pads of the larger die (lower die) due to flowage of liquid thermosetting adhesive. On the other hand, when the liquid adhesive is printed after wire-bonding, the printing screen is unable to be placed on the larger die(or substrate) with bonding wires, so that adhesive must be applied on the larger die before wire-bonding. Thus, the limits for multi-chip packaging process are quite a lots, lead to package uneasily. Alternatively, a solid adhesive tape may also be used for die-attaching, but cost of adhesive tape is high and the adhesive tape is demanded double-sided adhesive for die-to-die, die-to-substrate or die-to-leadframe bonding. Conventionally the adhesive tape is firstly attached on a substrate (leadframe or larger die) in predetermined pattern, then a die is bonded on the adhesive tape. The dies do not have adhesive after sigulating from a wafer.
SUMMARY
A first object of the present invention is to provide a wafer treating method for making adhesive dies by utilizing a liquid adhesive with two-stage property printed on a wafer. The printed adhesive with two-stage property is pre-cured to become solid without flowable and adhesive under room temperature (B-stage condition), then after singulating the wafer, a plurality of dies with B-stage adhesive will be obtained for decreasing cost of forming adhesive.
A second object of the present invention is to provide a wafer treating method for making adhesive dies by utilizing a liquid adhesive with two-stage property printed on a wafer. The adhesive with two-stage property is precured to become solid film without flowable and adhesive under room temperature (B-stage condition), then after singulating the wafer, the dies with B-stage adhesive will be obtained, so as to possess good processing characteristic for a variety of semiconductor packaging processes.
In accordance with the wafer treating method for making adhesive dies of the present invention, a semiconductor wafer having integrated circuits is provided. The wafer has a plane surface, such as an active surface or an inactive surface. A liquid adhesive with two-stage property is evenly coated on the partial or overall surface of the wafer by means of screen printing, stencil printing or spin coating. It is desirable to coat the liquid adhesive with two-stage property on the partial surface of the wafer without covering the cutting paths or bonding pads of the wafer. Next, the wafer is pre-cured to make the adhesive with two-stage property become a wafer-level thermo-bonding adhesive film with B-stage property, that is, being solid without flowable and adhesive under room temperature. Usually the pre-cured time is about 1 hour around 125° C. Meanwhile, the B-stage solid film has thermosetting property and adhesion of thermal bonding, also has a glass transition temperature (Tg) more than 40° C. for operation of positioning the wafer, sucking the dies utilizing a die binder and transportation after singulating the dies from the wafer. Thus the dies with wafer-level thermo-bonding adhesive film are provided to affix to a substrate, another die, a printed circuit board, a ceramic circuit board or a lead frame without extra adhesive. Therefore, the dies with wafer-level thermo-bonding adhesive film are able to be efficiently, broadly used in die-to-die stack or die-to-substrate attach for various packages at low cost.
Additionally, the present invention is directed to a chip package comprising a carrier, a first chip, a first adhesive layer and a molding compound. The first chip is disposed on the carrier and electrically connected with the carrier. The first adhesive layer is disposed between the carrier and the first chip, wherein an area of the first adhesive layer is not larger than an area of the first chip. The molding compound is disposed on the carrier to cover the first chip.
In accordance with the chip package of the present invention, the chip package further comprises a plurality of first bonding wires, which are electrically connected with the carrier and the first chip. The first adhesive layer can be an adhesive film, wherein the adhesive film can be an adhesive film having B-stage property.
In accordance with the chip package of the present invention, wherein the carrier is a package substrate or a lead frame.
In accordance with the chip package of the present invention, the chip package further comprises a second adhesive layer and a second chip, wherein the second adhesive layer is disposed on the first chip and the second chip is disposed on the second adhesive layer. And wherein an area of the second adhesive layer is not larger than an area of the second chip and the second chip is electrically connected with the carrier.
In accordance with the chip package of the present invention, the chip package further comprises a plurality of second bonding wires, which are electrically connected with the carrier and the second chip.
In accordance with the chip package of the present invention, wherein the second bonding wires and the second chip are covered with the molding compound. In accordance with the chip package of the present invention, wherein the second adhesive layer is disposed between an inactive surface of the second chip and an active surface of the first chip.
In accordance with the chip package of the present invention, wherein the second adhesive layer can be an adhesive film.
In accordance with the chip package of the present invention, wherein the second adhesive layer can be an adhesive film having B-stage property.
In addition, the present invention is directed to a chip package comprising a carrier, a first chip, a second chip, a second adhesive layer and a molding compound. The first chip is disposed on the carrier and electrically connected with the carrier. The second chip is disposed on the first chip and electrically connected with the carrier. The second adhesive layer is disposed between the first chip and the second chip, wherein an area of the second adhesive layer is not larger than an area of the second chip. The molding compound is disposed on the carrier to cover the first chip, the second chip, and the second adhesive layer.
In accordance with the chip package of the present invention, the chip package further comprises a plurality of first bonding wires, which are electrically connected with the carrier and the first chip.
In accordance with the chip package of the present invention, the chip package further comprises a plurality of second bonding wires, which are electrically connected with the carrier and the second chip.
In accordance with the chip package of the present invention, wherein the second adhesive layer can be an adhesive film.
In accordance with the chip package of the present invention, wherein the second adhesive layer can be an adhesive film having B-stage property.
In accordance with the chip package of the present invention, the chip package further comprises a first adhesive layer, which is disposed between the carrier and the first chip. In addition, the first adhesive layer can be an adhesive film.
In accordance with the chip package of the present invention, wherein the first adhesive layer can be an adhesive film having B-stage property.
In accordance with the chip package of the present invention, wherein the carrier is a package substrate or a lead frame.
In accordance with the chip package of the present invention, wherein the second adhesive layer is disposed between an inactive surface of the second chip and an active surface of the first chip.
DESCRIPTION OF THE DRAWINGS
FIG. 1 is a flow chart of a wafer treating method for making adhesive dies in accordance with the present invention.
FIG. 2 is a front view of a provided wafer in accordance with a wafer treating method for making adhesive dies of the present invention.
FIG. 3A to FIG. 3D are cross-sectional views of a wafer in wafer treating process in accordance with a first embodiment of the present invention.
FIG. 3E to FIG. 3F are cross-sectional views of an adhesive die made from the first embodiment in die-to-die stack.
FIG. 4A to FIG. 4D are cross-sectional views of a wafer in wafer treating process in accordance with a second embodiment of the present invention.
FIG. 4E to FIG. 4F are cross-sectional views of an adhesive die made from the second embodiment in die-to-substrate package.
FIG. 5 is a cross-sectional view illustrating the inactive surface of wafer attached to a position tape for singulation to make adhesive dies in accordance with a third embodiment of the present invention.
FIG. 6 and FIG. 7 are cross-sectional views illustrating an adhesive die made from the third embodiment in die-to-leadframe package.
 DETAILED DESCRIPTION OF THE PRESENT INVENTION
Referring to the drawings attached, the present invention will be described by means of the embodiments below.
As shown in FIG. 1, the wafer treating method for making adhesive dies according to the present invention comprises the main steps of “providing a wafer” 11, “coating a liquid adhesive with two-stage property” 12, “pre-curing the wafer” 13, “positioning the wafer” 14 and “singulating the wafer to form dies with wafer-level thermo-bonding adhesive film” 15.
As illustrated in FIG. 2 and FIG. 3A, initially in the step of “providing a wafer” 11, a wafer 110 is provided. The wafer 110 has an active surface 112 which had formed integrated circuits and bonding pads 115, an inactive surface 111 corresponding to the active surface 112 in order to integrate a plurality of dies 113 together. The bonding pads 115 are located on each die 113. There are straight cutting paths 114 located at the perimeters of the dies 113 to define the dies 113. According to predetermined packag or stack process, a surface of the wafer 110 for required to being adhesive is active surface 112 or inactive surface 111. In the first embodiment, the inactive surface 111 of the wafer 110 is predetermined to be adhesive, the inactive surface 111 should face upward. Next, the step of “coating a liquid adhesive with two-stage property” 12 is executed, as shown in FIG. 3B. A liquid adhesive 130 having at least two-stage property (A-stage, B-stage, C-stage) is coated on partially or totally inactive surface 111 of the wafer 110 by screen printing, stencil printing or spin coating. Preferably, a screen 121 is placed on the inactive surface 111 of the wafer 110, then the liquid adhesive 130 with proper flowability is printed on the inactive surface 111 by a scraper 122. In this embodiment, the screen 121 covers the cutting paths 114 of the wafer 110 so that the adhesive 130 with two-stage property is partially printed on the inactive surface 111 of the wafer 110 without covering the cutting paths 114. Since the dies 113 formed in this embodiment are used for die-to-die stack, the printed thickness of the adhesive 130 with two-stage property is about 3˜6 mil and depends on the screen 121. The adhesive 130 with two-stage property includes thermosetting resin or polymer such as polyimide, polyquinolin or benzocyclobutene and solvent that enable dissolution of mentioned-above thermosetting resin such as mix-solvent of butyrolactone and cyclopentanone or 1,3,5-mesitylene, etc. Since the liquid adhesive 130 with two-stage property has A-stage property while coated, the liquid adhesive 130 is fluid enough to be printed.
Next, the step of “pre-curing the wafer” 13 is executed as shown in FIG. 3C. The wafer 130 is placed in an oven to be heated at a proper temperature (90˜150° C. approximately) for 1 hour for removing solvent. The pre-curing procedure is to remove the solvent of the liquid adhesive 130 with two-stage property, so that the printed liquid adhesive 130 transforms a wafer-level thermo-bonding adhesive film 131. Otherwise, the pre-curing step 13 is executed by vacuum drying. The wafer-level thermo-bonding adhesive film 131 is solid and has a thickness between 3˜8 mil for die-to-die stacking, preferably between 5˜6 mil. And the wafer-level thermo-bonding adhesive film 131 becomes adhesive when operating temperature is more than its glass transition temperature (Tg), that is to say, the wafer-level thermo-bonding adhesive film 131 possesses B-stage condition and also has thermosetting property. Preferably, the glass transition temperature of the wafer-level thermo-bonding adhesive film 131 is not less than 40° C. (Tg≧40° C.). Therefore, the wafer 110 with the wafer-level thermo-bonding adhesive film 131 is easy to handle, transport under normal room temperature.
Next, the step of “positioning the wafer” 14 is executed as shown in FIG. 3D, the wafer 110 is turned over to make the inactive surface 111 facing downward and attached to a positioning tape 140. The positioned tape 140 is a wafer positioning tape such as polyvinyl chloride, which has adhesive and is attached to a metal frame with circular opening for wafer-dicing procedure. In the first embodiment, the wafer-level thermo-bonding adhesive film 131 attaches on the positioning tape 140 by the adhesive of the positioning tape 140. After completing the step of “positioning the wafer” 14, the step of “singulating the wafer to form dies with wafer-level thermo-bonding adhesive film” 15 is executed that is along the cutting paths 114 to dice the wafer 110 by using the dicer 150 (laser or diamond cutting tool) of wafer-dicing machine to form a plurality of dies 113 with wafer-level thermo-bonding adhesive film 131. Thus, the adhesive dies 113 not only can be rapidly provided at low cost but also can be used in die-to-die stacks or other various packages. For example, as shown in FIG. 3E, initially another die 160 is affixed to a substrate 170 and the bonding pads 161 of the die 160 is electrically connected with the substrate 170 by bonding wires 162, then the die 113 with the wafer-level thermo-bonding adhesive film 131 is sucked by a die attach machine and is affixed onto the die 160. A die-to-die stack structure will be completed in few seconds, even in less than a second when a thermal compression temperature 120° C.-175° C. approximately is supplied at the die 113 to allow the wafer-level thermo-bonding adhesive film 131 become adhesive (as shown in FIG. 3F). However, it is desirable that the thermal compression temperature and time do not make the wafer-level thermo-bonding adhesive film 131 finish the thermosetting reaction after die-to-die attaching. Thereafter, the bonding wires 180 are wire-bonded to electrically connect the bonding pads 115 of the die 113 with the substrate 170. However, the wafer treating method for making adhesive dies of the present invention is applicable not only for die-to-die stacking but also for the-to-substrate and die-to-leadframe attaching for various packages. Alternatively, in the step of “coating the liquid adhesive with two-stage property” 12, a layer of liquid adhesive 130 with two-stage property is completely coated on all of the inactive surface 111 of a wafer 110 by spin coating or printing method, then passing through pre-curing step 13, positioning step 14 and singulating step 15, a plurality of dies 113 with wafer-level thermo-bonding adhesive film 131 on the inactive surface thereof are formed for die-to-substrate attaching. The wafer-level thermo-bonding adhesive film 131 has higher viscous and handling-easier than conventional silver liquid paste so that the contact pads of substrate can be closer to the adhesive die 113 for making chip scale package (CSP).
In order to understand the present invention is not limited to the printing surface of wafer, the second embodiment is presented. As shown in FIG. 4A, initially a wafer 210 is provided. The wafer 210 has an active surface 211 having a plurality of bonding pads 215 (or bumps) and an inactive surface 212 corresponding to the active surface 211 to integrate a plurality of dies 213. The bonding pads 215 are located at the center of each die 213 and the active surface 211 faces upward. Thereafter, as shown in FIG. 4B, a liquid adhesive 230 with two-stage property is formed on the active surface 211 by screen printing or stencil printing method. A screen 221 is put on the active surface 211 of the wafer 210, then the liquid adhesive 230 with two-stage property is printed on the active surface 212 by a scraper 222. In the second embodiment, since the screen 221 covers the bonding pads 215 of the wafer 210, the liquid adhesive 230 with two-stage property is partially printed on the active surface 212 of the wafer 210 with predetermined pattern, the thickness thereof is about 1˜3 mil.
Then, as shown in FIG. 4C, the wafer 210 is pre-cured to remove solvent in the liquid adhesive 230 with two-stage property on the active surface 211 of the wafer 210 so as to transform a wafer-level thermo-bonding adhesive film 231. The wafer-level thermo-bonding adhesive film 231 has B-stage property and has a glass transition temperature (Tg) not less than 40° C., so that the wafer-level thermo-bonding adhesive film 231 doesn't possess adhesive under the normal room temperature for being portable, movable and storable and also possesses thermo-bonding adhesive. Next, as shown in FIG. 4D, the wafer 210 is turned over so that the active surface 211 faces downward and is positioned onto a positioning tape 240. After the wafer 210 is positioned, it is diced along the cutting paths 214 by a dicer 250 to form a plurality of dies 213 with wafer-level thermo-bonding adhesive film 231 on the active surface 211. Thus, the adhesive dies 213 not only can be rapidly provided at low cost but also can be utilized in various packages. For example, as shown in FIG. 4E, the die 213 with wafer-level thermo-bonding adhesive film 231 is sucked by a die attach machine and is affixed to a substrate 260 such as a printed circuit board or ceramic circuit substrate. The die 213 can be quickly attached to a substrate at the thermal bonding temperature around 120° C.-175° C. even in few seconds. The adhesive strength between substrate 260 and die 213 is provided by means of the wafer-level thermo-bonding adhesive film 231 at the thermal bonding temperature. Also, a BGA package can be fabricated after executing the steps of forming bonding-wire 262, the molding package body 263 and the solder balls 261 (as shown in FIG. 4F).
Moreover, in the third embodiment of the present invention, the process steps are the same as those illustrated in the second embodiment shown in FIG. 4A to FIG. 4C. As shown in FIG. 5, the inactive surface 212 of the wafer 210 is directly positioned to a position tape 240. After pre-curing the wafer 210, the active surface 211 of the wafer 210 faces upward and is singulated to form a plurality of die 213 by dicer 250. As shown in FIG. 6, the dies 213 with wafer-level thermo-bonding adhesive film 231 are sucked on a carrier 272, then the inner leads 271 of a LOC (Lead-On-Chip) lead frame are attached downward to the active surface 211 of the die 213. By thermal bonding the wafer-level thermo-bonding adhesive film 231 becomes adhesive to adhere the die 213 and the inner leads 271 of leadframe. As shown in FIG. 7, bonding wires 274, molding compound 273 are formed to manufacture a package of TSOP (Thin Small Outline Package) or QFP (Quad Flat Package). Therefore, according to the wafer treating method for making adhesive dies of the present invention, the dies 213 with wafer-level thermo-bonding adhesive film 231 can be massively manufactured at low cost for die-to-leadframe package.
The above description of embodiments of this invention is intended to be illustrative and not limiting. Other embodiments of this invention will be obvious to those skilled in the art in view of the above disclosure.

Claims (16)

1. A wafer treating method for making adhesive dies comprising the steps of:
providing a wafer having a surface;
coating a liquid adhesive with two-stage property on the surface of the wafer, wherein the surface of the wafer is partially coated with the liquid adhesive;
pre-curing the liquid adhesive so that the liquid adhesive transforms into a wafer-level thermo-bonding adhesive film having B-stage property;
providing a positioning tape in contact with the wafer-level thermo-bonding adhesive film for positioning the wafer; and
singulating the wafer on the positioning tape so as to form a plurality of dies with the wafer-level thermo-bonding adhesive film.
2. The wafer treating method for making adhesive dies in accordance with claim 1, wherein the liquid adhesive is formed by screen printing, stencil printing or spin coating.
3. The wafer treating methods for making adhesive dies in accordance with claim 1, wherein the surface of the wafer is an active surface of the wafer.
4. The wafer treating method for making adhesive dies in accordance with claim 1, wherein the surface of the wafer is an inactive surface of the wafer.
5. The wafer treating method for making adhesive dies in accordance with claim 1, wherein the surface of the wafer is partially coated with the liquid adhesive.
6. The wafer treating method for making adhesive dies in accordance with claim 5 1, wherein the wafer has cutting paths and bonding pads and wherein the surface is coated with the liquid adhesive without covering the cutting path and the bonding pads of the wafer.
7. The wafer treating method for making adhesive dies in accordance with claim 1, wherein the entire surface of the wafer is coated with liquid adhesive.
8. The wafer treating method for making adhesive dies in accordance with claim 1, wherein the wafer-level thermo-bonding adhesive film has a glass transition temperature (Tg) not less than 40° C.
9. The wafer treating method for making adhesive dies in accordance with claim 1, wherein the wafer-level thermo-bonding adhesive film has a thickness between 3˜8 mil for die-to-die stacking.
10. The wafer treating method for making adhesive dies in accordance with claim 1, wherein the wafer-level thermo-bonding adhesive film has a thickness between 5˜6 mil for die-to-die stacking.
11. The wafer treating method for making adhesive dies in accordance with claim 1, wherein the wafer-level thermo-bonding adhesive film has a thickness between 1˜3 mil for die-to-substrate or die-to-leadframe attaching.
12. A wafer treating method for making adhesive dies comprising the steps of:
providing a wafer having an active surface upwardly, wherein a plurality of bonding pads are formed on the active surface, there are a plurality of cutting paths at the wafer to define dies;
coating a liquid adhesive on the partially active surface of the wafer, wherein the liquid adhesive exposes the bonding pads;
pre-curing the liquid adhesive so that the liquid adhesive transforms into a wafer-level thermo-bonding adhesive film having B-stage property; and
singulating the wafer along the cutting path so as to form a plurality of dies with the wafer-level thermo-bonding adhesive film.
13. The wafer treating method for making adhesive dies in accordance with claim 12, wherein the liquid adhesive is formed by screen printing or stencil printing method.
14. The wafer treating method for making adhesive dies accordance with claim 12, wherein the wafer-level thermo-bonding adhesive film has a glass transition temperature (Tg) not less than 40° C.
15. The wafer treating method for making adhesive dies in accordance with claim 12, wherein the wafer-level thermo-bonding adhesive film has a thickness between 1˜3 mil for die-to-leadframe attaching.
16. The wafer treating method for making adhesive dies in accordance with claim 12, wherein the coating step of a liquid adhesive, the liquid adhesive exposes the cutting paths.
US11/371,307 2002-12-24 2006-03-07 Wafer treating method for making adhesive dies Expired - Lifetime USRE42349E1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/371,307 USRE42349E1 (en) 2002-12-24 2006-03-07 Wafer treating method for making adhesive dies

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/327,064 US6703075B1 (en) 2002-12-24 2002-12-24 Wafer treating method for making adhesive dies
US11/371,307 USRE42349E1 (en) 2002-12-24 2006-03-07 Wafer treating method for making adhesive dies

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/327,064 Reissue US6703075B1 (en) 2002-12-24 2002-12-24 Wafer treating method for making adhesive dies

Publications (1)

Publication Number Publication Date
USRE42349E1 true USRE42349E1 (en) 2011-05-10

Family

ID=31888012

Family Applications (2)

Application Number Title Priority Date Filing Date
US10/327,064 Expired - Lifetime US6703075B1 (en) 2002-12-24 2002-12-24 Wafer treating method for making adhesive dies
US11/371,307 Expired - Lifetime USRE42349E1 (en) 2002-12-24 2006-03-07 Wafer treating method for making adhesive dies

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US10/327,064 Expired - Lifetime US6703075B1 (en) 2002-12-24 2002-12-24 Wafer treating method for making adhesive dies

Country Status (1)

Country Link
US (2) US6703075B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8697542B2 (en) * 2012-04-12 2014-04-15 The Research Foundation Of State University Of New York Method for thin die-to-wafer bonding
US20180204818A1 (en) * 2017-01-18 2018-07-19 Disco Corporation Manufacturing method for package device

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004322168A (en) * 2003-04-25 2004-11-18 Disco Abrasive Syst Ltd Laser machining apparatus
US6943061B1 (en) * 2004-04-12 2005-09-13 Ns Electronics Bangkok (1993) Ltd. Method of fabricating semiconductor chip package using screen printing of epoxy on wafer
US7102159B2 (en) * 2004-06-12 2006-09-05 Macronix International Co., Ltd. Ultra thin image sensor package structure and method for fabrication
US7186588B1 (en) * 2004-06-18 2007-03-06 National Semiconductor Corporation Method of fabricating a micro-array integrated circuit package
US7235196B2 (en) * 2004-07-07 2007-06-26 Xerox Corporation Display capsules and a method of manufacturing thereof
US20070063344A1 (en) * 2005-09-22 2007-03-22 Chun-Hung Lin Chip package structure and bumping process
US20080308915A1 (en) * 2006-03-17 2008-12-18 Chipmos Technologies Inc. Chip package
US20080308914A1 (en) * 2006-03-17 2008-12-18 Chipmos Technologies Inc. Chip package
US7638880B2 (en) * 2006-03-17 2009-12-29 Chipmos Technologies Inc. Chip package
TWI288959B (en) * 2006-03-17 2007-10-21 Chipmos Technologies Inc Chip package and wafer treating method for making adhesive chips
SG143098A1 (en) 2006-12-04 2008-06-27 Micron Technology Inc Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
TWI357104B (en) * 2007-11-07 2012-01-21 Advanced Semiconductor Eng Wafer grinding method
CN101567301B (en) * 2008-04-21 2010-09-29 力成科技股份有限公司 Method for forming viscous grain by wafer separation
US8334170B2 (en) * 2008-06-27 2012-12-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method for stacking devices
TWI387089B (en) * 2008-11-14 2013-02-21 Chipmos Technologies Inc Multi-chips package and manufacturing method thereof
US7851266B2 (en) * 2008-11-26 2010-12-14 Micron Technologies, Inc. Microelectronic device wafers including an in-situ molded adhesive, molds for in-situ molding adhesives on microelectronic device wafers, and methods of molding adhesives on microelectronic device wafers
US8222088B2 (en) * 2009-09-21 2012-07-17 Alpha And Omega Semiconductor Incorporated Semiconductor package with adhesive material pre-printed on the lead frame and chip, and its manufacturing method
JP5558900B2 (en) * 2010-04-23 2014-07-23 株式会社東芝 Semiconductor device manufacturing method and semiconductor manufacturing apparatus
JP2012033842A (en) * 2010-08-03 2012-02-16 Disco Abrasive Syst Ltd Manufacturing method for device chip
CN102842511A (en) * 2012-08-20 2012-12-26 上海凯虹科技电子有限公司 Chip packaging method and wafer manufactured through chip packaging method
KR20160052798A (en) * 2012-12-14 2016-05-12 아사히 가세이 일렉트로닉스 가부시끼가이샤 Magnetic sensor and magnetic sensor device, and magnetic sensor manufacturing method
JP6735653B2 (en) * 2016-10-24 2020-08-05 株式会社ディスコ Wafer division method
DE102017215303A1 (en) 2017-09-01 2018-07-19 Robert Bosch Gmbh Method for producing a semiconductor component

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58196031A (en) 1982-05-11 1983-11-15 Nec Home Electronics Ltd Manufacture of semiconductor device
JPH06302629A (en) 1993-04-19 1994-10-28 Toshiba Chem Corp Mounting method of semiconductor device
US5635010A (en) * 1995-04-14 1997-06-03 Pepe; Angel A. Dry adhesive joining of layers of electronic devices
US20010005935A1 (en) * 1999-08-31 2001-07-05 Tandy Patrick W. Assembling a stacked die package
TW457654B (en) 2000-03-23 2001-10-01 Siliconware Precision Industries Co Ltd Method for die attach
US6689638B2 (en) * 2001-08-27 2004-02-10 Chipmos Technologies (Bermuda) Ltd. Substrate-on-chip packaging process
US6943061B1 (en) * 2004-04-12 2005-09-13 Ns Electronics Bangkok (1993) Ltd. Method of fabricating semiconductor chip package using screen printing of epoxy on wafer

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58196031A (en) 1982-05-11 1983-11-15 Nec Home Electronics Ltd Manufacture of semiconductor device
JPH06302629A (en) 1993-04-19 1994-10-28 Toshiba Chem Corp Mounting method of semiconductor device
US5635010A (en) * 1995-04-14 1997-06-03 Pepe; Angel A. Dry adhesive joining of layers of electronic devices
US20010005935A1 (en) * 1999-08-31 2001-07-05 Tandy Patrick W. Assembling a stacked die package
TW457654B (en) 2000-03-23 2001-10-01 Siliconware Precision Industries Co Ltd Method for die attach
US6689638B2 (en) * 2001-08-27 2004-02-10 Chipmos Technologies (Bermuda) Ltd. Substrate-on-chip packaging process
US6943061B1 (en) * 2004-04-12 2005-09-13 Ns Electronics Bangkok (1993) Ltd. Method of fabricating semiconductor chip package using screen printing of epoxy on wafer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8697542B2 (en) * 2012-04-12 2014-04-15 The Research Foundation Of State University Of New York Method for thin die-to-wafer bonding
US20180204818A1 (en) * 2017-01-18 2018-07-19 Disco Corporation Manufacturing method for package device

Also Published As

Publication number Publication date
US6703075B1 (en) 2004-03-09

Similar Documents

Publication Publication Date Title
USRE42349E1 (en) Wafer treating method for making adhesive dies
US20070215992A1 (en) Chip package and wafer treating method for making adhesive chips
US7358117B2 (en) Stacked die in die BGA package
JP5227501B2 (en) Stack die package and method of manufacturing the same
US9691688B2 (en) Thin plastic leadless package with exposed metal die paddle
US7745918B1 (en) Package in package (PiP)
US8815645B2 (en) Multi-chip stacking method to reduce voids between stacked chips
US20070122943A1 (en) Method of making semiconductor package having exposed heat spreader
US8093104B1 (en) Multi-chip stacking method to reduce voids between stacked chips
US8531017B2 (en) Semiconductor packages having increased input/output capacity and related methods
US20070080435A1 (en) Semiconductor packaging process and carrier for semiconductor package
US6207478B1 (en) Method for manufacturing semiconductor package of center pad type device
US20080265393A1 (en) Stack package with releasing layer and method for forming the same
US7226813B2 (en) Semiconductor package
US6339253B1 (en) Semiconductor package
US7579680B2 (en) Packaging system for semiconductor devices
US20080283981A1 (en) Chip-On-Lead and Lead-On-Chip Stacked Structure
US7229849B2 (en) Method for packaging a semiconductor device
KR100456815B1 (en) Semiconductor package and method for attaching chip

Legal Events

Date Code Title Description
FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12