USRE37769E1 - Methods for fabricating memory cells and load elements - Google Patents
Methods for fabricating memory cells and load elements Download PDFInfo
- Publication number
- USRE37769E1 USRE37769E1 US08/316,035 US31603594A USRE37769E US RE37769 E1 USRE37769 E1 US RE37769E1 US 31603594 A US31603594 A US 31603594A US RE37769 E USRE37769 E US RE37769E
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- polycrystalline silicon
- silicon interconnect
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- 238000000034 method Methods 0.000 title claims description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 53
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 16
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 4
- 230000005669 field effect Effects 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims 7
- 239000002019 doping agent Substances 0.000 claims 5
- 101150049547 Lyar gene Proteins 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000007943 implant Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007850 degeneration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/019—Contacts of silicides
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
- Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
- Y10T428/24926—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including ceramic, glass, porcelain or quartz layer
Definitions
- the present invention is related generally to integrated circuits, and more specifically to a contact between different layers of polycrystalline silicon interconnect.
- An ohmic contact is one in which no P-N junction is formed.
- a contact structure provides electrical contact between two polycrystalline silicon interconnect layers.
- the lower layer has a silicide layer on its upper surface.
- the upper polycrystalline silicon layer can be doped with a different conductivity type, and makes the ohmic contact with the silicided region of the lower polycrystalline silicon layer.
- FIGS. 1-3 illustrate a preferred method for forming a contact according to the present invention.
- FIG. 4 is a schematic diagram of the SRAM cell utilizing an ohmic contact formed according to the present invention.
- a semiconductor substrate 10 is partially covered with an oxide layer 12 .
- the oxide layer 12 is not complete over the entire surface of the substrate 10 , but that portion of interest to the present description has no openings to the substrate 10 .
- a polycrystalline silicon layer 14 lies on the oxide layer 12 .
- layer 14 is doped N-type.
- the polycrystalline silicon layer 14 has been silicided to form a silicide layer 16 thereon.
- the polycrystalline silicon 14 and silicide layer 16 have been patterned in a previous processing step as known in the art to form a signal line.
- the polycrystalline silicon layer 14 may be a first polycrystalline silicon layer, such as commonly used to form gate electrodes of field effect devices.
- polycrystalline silicon layer 14 may be a second or later level used for interconnect between different portions of an integrated circuit device. At the processing stage shown in FIG. 1, the transistors of the device have already been formed.
- Oxide layer 18 is typically a thin oxide layer, having a thickness of between 500 and 1000 angstroms.
- the thickness of oxide layer 18 may be any thickness which is compatible with the fabrication process with which the invention described herein is being used.
- oxide layer 18 is patterned and etched to define a contact opening 20 to the upper surface of the silicide layer 16 .
- a layer of polycrystalline silicon 22 is then deposited over the surface of the device.
- a light dosage of boron is implanted into the polycrystalline silicon layer 22 in order to convert it to a P-type conductor.
- a typical dosage would be approximately 10 13 atoms/cm 2 .
- the polycrystalline silicon layer 22 is then masked, and a heavy arsenic implant made to define an N + region 24 .
- a typical dosage for such implant is 5 ⁇ 10 15 atoms/cm 2 .
- Such doping level is used to allow the N + region 24 to be used as a power supply line.
- a P-N junction 26 is formed at the interface between the N + region 24 and the lightly P-doped polycrystalline silicon layer 22 .
- the doping of polycrystalline silicon layer 22 is low enough to define a resistor, but is sufficiently high to cause degeneration in the contact opening 20 , providing an ohmic contact between the polycrystalline silicon layer 22 and the silicide layer 16 .
- the polycrystalline silicon layer 14 is N-type, no P-N junction is formed at the contact between the two layers 14 , 22 .
- the polycrystalline silicon layer 22 is etched to define interconnect, leaving the structure shown in FIG. 3 .
- the device is then ready for formation of further oxide and interconnect levels as desired.
- FIG. 4 a 4-transistor SRAM cell is shown.
- the contact structure formed in FIG. 1-3 is suitable for use as a load element in the cell of FIG. 4 .
- Cross-coupled field effect devices 30 , 32 form the basis of the SRAM cell.
- Access transistors 34 , 36 connect the bit line BL and complemented bit line BL′ to common nodes 38 , 40 , respectively.
- Access transistors 34 , 36 are driven by the word line 42 as known in the art.
- Node 38 is connected to the power supply line V cc through resistor 44 and diode 46 .
- Node 40 is connected to V cc through resistor 48 and diode 50 .
- Node 38 corresponds to contact opening 20 in FIG. 3 .
- Resistor 44 corresponds to polycrystalline silicon region 22 of FIG. 3, with diode 46 being formed at the junction 26 .
- Node 40 , resistor 48 , and diode 50 correspond to FIG. 3 in a similar manner.
- the load for the SRAM cell is formed by a resistor and a diode rather than back-to-back polycrystalline silicon diodes. In some SRAM cell designs, this can provide improved performance over the use of a resistor alone, or back-to-back polycrystalline silicon diodes.
- a similar ohmic contact can be formed between a lower polycrystalline silicon layer which is doped P-type and an upper N-type layer.
- the silicide layer prevents formation of a P-N junction in the contact opening.
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
A contact structure provides electrical contact between two polycrystalline silicon interconnect layers. The lower layer has a silicide layer on its upper surface. The upper polycrystalline silicon layer can be doped with a different conductivity type, and makes an ohmic contact with the silicided region of the lower polycrystalline silicon layer.
Description
1. Field of the Invention
The present invention is related generally to integrated circuits, and more specifically to a contact between different layers of polycrystalline silicon interconnect.
2. Description of the Prior Art
In semiconductor circuits, it is known that ohmic contacts are desirable between interconnect layers. An ohmic contact is one in which no P-N junction is formed.
When polycrystalline silicon interconnect lines having different conductivity types make contact, a P-N junction is formed. A similar junction can be formed when polycrystalline silicon having the same conductivity type, but very different doping levels (such as N−− to N +) make contact. For various reasons, it is often desirable to have interconnect having different conductivity types make contact, and it would be desirable to provide an ohmic contact for such structures.
It is therefore an object of the present invention to provide an ohmic contact between polycrystalline silicon interconnect layers having different conductivity types.
It is another object of the present invention to provide such a contact which is easily formed with a process compatible with existing process technologies.
It is a further object of the present invention to provide such a contact which is suitable for use in an SRAM structure to provide a load.
Therefore, according to the present invention, a contact structure provides electrical contact between two polycrystalline silicon interconnect layers. The lower layer has a silicide layer on its upper surface. The upper polycrystalline silicon layer can be doped with a different conductivity type, and makes the ohmic contact with the silicided region of the lower polycrystalline silicon layer.
The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself however, as well as a preferred mode of use, and further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
FIGS. 1-3 illustrate a preferred method for forming a contact according to the present invention; and
FIG. 4 is a schematic diagram of the SRAM cell utilizing an ohmic contact formed according to the present invention.
The process steps and structures described below do not form a complete process flow for manufacturing integrated circuits. The present invention can be practiced in conjunction with integrated circuit fabrication techniques currently used in the art, and only so much of the commonly practiced process steps are included as are necessary for an understanding of the present invention. The figures representing cross-sections of portions of an integrated circuit during fabrication are not drawn to scale, but instead are drawn so as to illustrate the important features of the invention.
Referring to FIG. 1, a semiconductor substrate 10 is partially covered with an oxide layer 12. The oxide layer 12 is not complete over the entire surface of the substrate 10, but that portion of interest to the present description has no openings to the substrate 10.
A polycrystalline silicon layer 14 lies on the oxide layer 12. In the illustrative embodiment, layer 14 is doped N-type. The polycrystalline silicon layer 14 has been silicided to form a silicide layer 16 thereon. The polycrystalline silicon 14 and silicide layer 16 have been patterned in a previous processing step as known in the art to form a signal line. The polycrystalline silicon layer 14 may be a first polycrystalline silicon layer, such as commonly used to form gate electrodes of field effect devices. Alternatively, polycrystalline silicon layer 14 may be a second or later level used for interconnect between different portions of an integrated circuit device. At the processing stage shown in FIG. 1, the transistors of the device have already been formed.
Once the polycrystalline silicon and silicide layers 14, 16 have been formed and patterned, an oxide layer 18 is formed over the surface of the device. Oxide layer 18 is typically a thin oxide layer, having a thickness of between 500 and 1000 angstroms. The thickness of oxide layer 18 may be any thickness which is compatible with the fabrication process with which the invention described herein is being used.
Referring to FIG. 2, oxide layer 18 is patterned and etched to define a contact opening 20 to the upper surface of the silicide layer 16. A layer of polycrystalline silicon 22 is then deposited over the surface of the device.
A light dosage of boron is implanted into the polycrystalline silicon layer 22 in order to convert it to a P-type conductor. A typical dosage would be approximately 1013 atoms/cm2.
Referring to FIG. 3, the polycrystalline silicon layer 22 is then masked, and a heavy arsenic implant made to define an N+region 24. A typical dosage for such implant is 5×1015 atoms/cm2. Such doping level is used to allow the N+region 24 to be used as a power supply line.
A P-N junction 26 is formed at the interface between the N+region 24 and the lightly P-doped polycrystalline silicon layer 22. The doping of polycrystalline silicon layer 22 is low enough to define a resistor, but is sufficiently high to cause degeneration in the contact opening 20, providing an ohmic contact between the polycrystalline silicon layer 22 and the silicide layer 16. Thus, although the polycrystalline silicon layer 14 is N-type, no P-N junction is formed at the contact between the two layers 14, 22.
After formation of the highly doped N+regions 24, the polycrystalline silicon layer 22 is etched to define interconnect, leaving the structure shown in FIG. 3. The device is then ready for formation of further oxide and interconnect levels as desired.
Referring to FIG. 4, a 4-transistor SRAM cell is shown. The contact structure formed in FIG. 1-3 is suitable for use as a load element in the cell of FIG. 4.
Cross-coupled field effect devices 30, 32 form the basis of the SRAM cell. Access transistors 34, 36 connect the bit line BL and complemented bit line BL′ to common nodes 38, 40, respectively. Access transistors 34, 36 are driven by the word line 42 as known in the art. Node 38 is connected to the power supply line Vcc through resistor 44 and diode 46. Node 40 is connected to Vcc through resistor 48 and diode 50.
Since the contact at contact opening 20, corresponding to nodes 38 and 40, is an ohmic contact, the load for the SRAM cell is formed by a resistor and a diode rather than back-to-back polycrystalline silicon diodes. In some SRAM cell designs, this can provide improved performance over the use of a resistor alone, or back-to-back polycrystalline silicon diodes.
A similar ohmic contact can be formed between a lower polycrystalline silicon layer which is doped P-type and an upper N-type layer. The silicide layer prevents formation of a P-N junction in the contact opening.
While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
Claims (20)
1. A method for forming a contact in a semiconductor integrated circuit device, comprising the steps of:
forming a first polycrystalline silicon interconnect layer having a first conductivity type;
forming a silicide layer on the first polycrystalline silicon interconnect layer;
forming an insulating layer over the entire device;
forming a contact opening in the insulating layer, wherein a contact region on an upper surface of the silicide layer is exposed;
forming a second polycrystalline silicon interconnect layer having a second conductivity type over the insulating layer, wherein the second polycrystalline silicon interconnect layer makes ohmic contact with the silicide layer through the contact opening.
2. The method of claim 1 , wherein the first and second conductivity types are the same type, and wherein the second polycrystalline silicon interconnect layer is lightly doped relative to the first polycrystalline silicon interconnect layer.
3. The method of claim 1 , wherein the first and second conductivity types are of opposite types.
4. The method of claim 1 , wherein the first and second conductivity types are the same type, and wherein the first polycrystalline silicon interconnect layer is lightly doped relative to the second polycrystalline silicon interconnect layer.
5. The method of claim 3 , wherein the first conductivity type is N-type, and the second conductivity type is P-type.
6. The method of claim 3 , wherein the first conductivity type is P-type, and the second conductivity type is N-type.
7. A method for forming a contact in a semiconductor integrated circuit device, comprising the steps of:
forming a first polycrystalline silicon interconnect lyar having a first conductivity type;
forming a silicide layer on the first polycrystalline silicon interconnect layer;
forming an insulating layer over the entire device;
forming a contact opening in the insulating layer, wherein a contact region on an upper surface of the silicide layer is exposed;
forming a second polycrystalline silicon interconnect layer having a second conductivity type opposite to the first conductivity type over the insulating layer, wherein the second polycrystalline silicon interconnect layer makes ohmic contact with the silicide layer through the contact opening; and
forming a region having the first conductivity type within the second polycrystalline silicon interconnect layer at a location spaced from the contact opening, wherein a P-N junction is formed within the second polycrystalline silicon interconnect layer.
8. A method of fabricating an SRAM cell, comprising the steps of:
fabricating first and second driver transistors and first and second pass transistors, said driver transistors each being N-channel field-effect transistors and having respect gates, sources, and drains;
connecting said gate of said driver transistor to said drain of second driver transistor, and connecting said gate of said second driver transistor to said drain of said first driver transistor, using a polycide layer comprising a lower polysilicon portion which is doped n-type polysilicon and an upper silicide portion;
providing an additional patterned polysilicon layer which includes both heavily doped n-type regions and lightly doped p-type regions,
said heavily doped n-regions of said additional polysilicon layer being connected directly to a positive power supply voltage, and
said lightly doped p-type regions of said additional polysilicon layer making ohmic contact directly to said silicide portion of said polycide layer to provide pull-up connections to said drains of said driver transistors.
9. A product made by the method of claim 1 .
10. A product made by the method of claim 7 .
11. A product made by the method of claim 8 .
12. The method of claim 1 , wherein said insulating layer has a thickness in the range of 500-1000 Å.
13. The method of claim 1 , wherein said second polycrystalline silicon interconnect layer includes 10 13 cm −2 implanted atoms of dopant.
14. The method of claim 1 , wherein said first polycrystalline silicon interconnect layer includes about 5×10 15 cm −2 implanted atoms of dopant.
15. The method of claim 7 , wherein the first and second conductivity types are of opposite types.
16. The method of claim 7 , wherein said insulating layer has a thickness in the range of 500-1000 Å.
17. The method of claim 7 , wherein said second polycrystalline silicon interconnect layer, other than said region having the first conductivity type, includes 10 13 cm −2 implanted atoms of dopant.
18. The method of claim 8 , wherein said additional patterned polysilicon layer includes 10 13 cm −2 implanted atoms of dopant.
19. The method of claim 8 , wherein said polycide layer includes about 5×10 15 cm −2 implanted atoms of dopant.
20. The method of claim 8 , wherein said additional patterned polysilicon layer overlies an oxide layer which has a thickness in the range of 500-1000 Å.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/316,035 USRE37769E1 (en) | 1990-04-30 | 1994-09-29 | Methods for fabricating memory cells and load elements |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/516,272 US5151387A (en) | 1990-04-30 | 1990-04-30 | Polycrystalline silicon contact structure |
US08/316,035 USRE37769E1 (en) | 1990-04-30 | 1994-09-29 | Methods for fabricating memory cells and load elements |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US07/516,272 Reissue US5151387A (en) | 1990-04-30 | 1990-04-30 | Polycrystalline silicon contact structure |
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USRE37769E1 true USRE37769E1 (en) | 2002-06-25 |
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Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
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US07/516,272 Ceased US5151387A (en) | 1990-04-30 | 1990-04-30 | Polycrystalline silicon contact structure |
US07/843,818 Expired - Lifetime US5279887A (en) | 1990-04-30 | 1992-02-28 | Polycrystalline silicon contact structure |
US08/316,035 Expired - Lifetime USRE37769E1 (en) | 1990-04-30 | 1994-09-29 | Methods for fabricating memory cells and load elements |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
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US07/516,272 Ceased US5151387A (en) | 1990-04-30 | 1990-04-30 | Polycrystalline silicon contact structure |
US07/843,818 Expired - Lifetime US5279887A (en) | 1990-04-30 | 1992-02-28 | Polycrystalline silicon contact structure |
Country Status (5)
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US (3) | US5151387A (en) |
EP (1) | EP0455339B1 (en) |
JP (1) | JP3064472B2 (en) |
KR (1) | KR910019137A (en) |
DE (1) | DE69130622T2 (en) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5204279A (en) * | 1991-06-03 | 1993-04-20 | Sgs-Thomson Microelectronics, Inc. | Method of making SRAM cell and structure with polycrystalline p-channel load devices |
JPH06275724A (en) * | 1993-01-22 | 1994-09-30 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
TW230266B (en) * | 1993-01-26 | 1994-09-11 | American Telephone & Telegraph | |
US5432129A (en) * | 1993-04-29 | 1995-07-11 | Sgs-Thomson Microelectronics, Inc. | Method of forming low resistance contacts at the junction between regions having different conductivity types |
WO1996024138A1 (en) * | 1995-01-31 | 1996-08-08 | Hitachi, Ltd. | Nonvolatile memory device and refreshing method |
US5627103A (en) * | 1995-03-02 | 1997-05-06 | Sony Corporation | Method of thin film transistor formation with split polysilicon deposition |
US6406984B1 (en) | 1997-10-06 | 2002-06-18 | The United States Of America As Represented By The Secretary Of The Navy | Method of making improved electrical contact to porous silicon using intercalated conductive materials |
KR100379136B1 (en) * | 1998-10-02 | 2003-04-08 | 인터내셔널 비지네스 머신즈 코포레이션 | Beta control using a rapid thermal oxidation |
US6214694B1 (en) * | 1998-11-17 | 2001-04-10 | International Business Machines Corporation | Process of making densely patterned silicon-on-insulator (SOI) region on a wafer |
US6429101B1 (en) | 1999-01-29 | 2002-08-06 | International Business Machines Corporation | Method of forming thermally stable polycrystal to single crystal electrical contact structure |
Citations (46)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4178674A (en) | 1978-03-27 | 1979-12-18 | Intel Corporation | Process for forming a contact region between layers of polysilicon with an integral polysilicon resistor |
US4180826A (en) | 1978-05-19 | 1979-12-25 | Intel Corporation | MOS double polysilicon read-only memory and cell |
US4214917A (en) | 1978-02-10 | 1980-07-29 | Emm Semi | Process of forming a semiconductor memory cell with continuous polysilicon run circuit elements |
US4290185A (en) | 1978-11-03 | 1981-09-22 | Mostek Corporation | Method of making an extremely low current load device for integrated circuit |
US4322821A (en) * | 1978-12-22 | 1982-03-30 | U.S. Philips Corporation | Memory cell for a static memory and static memory comprising such a cell |
US4367580A (en) | 1980-03-21 | 1983-01-11 | Texas Instruments Incorporated | Process for making polysilicon resistors |
US4370798A (en) | 1979-06-15 | 1983-02-01 | Texas Instruments Incorporated | Interlevel insulator for integrated circuit with implanted resistor element in second-level polycrystalline silicon |
JPS58135653A (en) | 1982-02-08 | 1983-08-12 | Toshiba Corp | Manufacture of semiconductor device |
US4398335A (en) * | 1980-12-09 | 1983-08-16 | Fairchild Camera & Instrument Corporation | Multilayer metal silicide interconnections for integrated circuits |
US4505026A (en) | 1983-07-14 | 1985-03-19 | Intel Corporation | CMOS Process for fabricating integrated circuits, particularly dynamic memory cells |
JPS6068634A (en) | 1983-09-26 | 1985-04-19 | Nec Corp | Semiconductor device |
US4535427A (en) | 1982-12-06 | 1985-08-13 | Mostek Corporation | Control of serial memory |
US4554729A (en) | 1981-02-06 | 1985-11-26 | Hitachi, Ltd. | Method of making semiconductor memory device |
US4560419A (en) | 1984-05-30 | 1985-12-24 | Inmos Corporation | Method of making polysilicon resistors with a low thermal activation energy |
US4561907A (en) | 1984-07-12 | 1985-12-31 | Bruha Raicu | Process for forming low sheet resistance polysilicon having anisotropic etch characteristics |
US4562640A (en) * | 1983-04-25 | 1986-01-07 | Siemens Aktiengesellschaft | Method of manufacturing stable, low resistance contacts in integrated semiconductor circuits |
US4581623A (en) * | 1984-05-24 | 1986-04-08 | Motorola, Inc. | Interlayer contact for use in a static RAM cell |
EP0182610A2 (en) | 1984-11-16 | 1986-05-28 | Fujitsu Limited | Semiconductor photodetector device |
US4617071A (en) * | 1981-10-27 | 1986-10-14 | Fairchild Semiconductor Corporation | Method of fabricating electrically connected regions of opposite conductivity type in a semiconductor structure |
US4619037A (en) | 1981-05-31 | 1986-10-28 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device |
US4654824A (en) * | 1984-12-18 | 1987-03-31 | Advanced Micro Devices, Inc. | Emitter coupled logic bipolar memory cell |
US4658378A (en) | 1982-12-15 | 1987-04-14 | Inmos Corporation | Polysilicon resistor with low thermal activation energy |
JPS6298660A (en) | 1985-10-25 | 1987-05-08 | Hitachi Ltd | Semiconductor device |
US4675715A (en) * | 1982-12-09 | 1987-06-23 | American Telephone And Telegraph Company, At&T Bell Laboratories | Semiconductor integrated circuit vertical geometry impedance element |
US4677735A (en) * | 1984-05-24 | 1987-07-07 | Texas Instruments Incorporated | Method of providing buried contacts for N and P channel devices in an SOI-CMOS process using a single N+polycrystalline silicon layer |
US4714685A (en) * | 1986-12-08 | 1987-12-22 | General Motors Corporation | Method of fabricating self-aligned silicon-on-insulator like devices |
US4792923A (en) * | 1985-08-30 | 1988-12-20 | Mitsubishi Denki Kabushiki Kaisha | Bipolar semiconductor memory device with double word lines structure |
US4804636A (en) * | 1985-05-01 | 1989-02-14 | Texas Instruments Incorporated | Process for making integrated circuits having titanium nitride triple interconnect |
US4831424A (en) * | 1981-08-07 | 1989-05-16 | Hitachi, Ltd. | Insulated gate semiconductor device with back-to-back diodes |
US4849344A (en) * | 1986-12-11 | 1989-07-18 | Fairchild Semiconductor Corporation | Enhanced density modified isoplanar process |
US4870033A (en) * | 1985-03-19 | 1989-09-26 | Yamaha Corporation | Method of manufacturing a multilayer electrode containing silicide for a semiconductor device |
US4874719A (en) * | 1986-05-06 | 1989-10-17 | Kabushiki Kaisha Toshiba | Method for manufacturing an electrical connection between conductor levels |
US4877483A (en) | 1987-07-03 | 1989-10-31 | S.G.S. Thomson Microelectronics, S.A. | Method for contact between two conductive or semi-conductive layers deposited on a substrate |
US4903096A (en) | 1984-08-23 | 1990-02-20 | Kabushiki Kaisha Toshiba | Semiconductor memory device with barrier layer |
US4907052A (en) | 1984-10-11 | 1990-03-06 | Kanegafuchi Kagaku Kogyo Kabushiki Kaisha | Semiconductor tandem solar cells with metal silicide barrier |
US4922455A (en) | 1987-09-08 | 1990-05-01 | International Business Machines Corporation | Memory cell with active device for saturation capacitance discharge prior to writing |
US4933735A (en) * | 1981-02-23 | 1990-06-12 | Unisys Corporation | Digital computer having control and arithmetic sections stacked above semiconductor substrate |
US4948747A (en) * | 1989-12-18 | 1990-08-14 | Motorola, Inc. | Method of making an integrated circuit resistor |
US4950620A (en) | 1988-09-30 | 1990-08-21 | Dallas Semiconductor Corp. | Process for making integrated circuit with doped silicon dioxide load elements |
US4966864A (en) | 1989-03-27 | 1990-10-30 | Motorola, Inc. | Contact structure and method |
US4968645A (en) | 1985-12-20 | 1990-11-06 | Sgs-Thomson Microelectronics S.R.L. | Method for manufacturing MOS/CMOS monolithic integrated circuits including silicide and polysilicon patterning |
US5021849A (en) | 1989-10-30 | 1991-06-04 | Motorola, Inc. | Compact SRAM cell with polycrystalline silicon diode load |
US5107322A (en) | 1988-11-10 | 1992-04-21 | Seiko Epson Corporation | Wiring or conductor interconnect for a semiconductor device or the like |
US5151376A (en) | 1990-05-31 | 1992-09-29 | Sgs-Thomson Microelectronics, Inc. | Method of making polycrystalline silicon resistors for integrated circuits |
US5187114A (en) | 1991-06-03 | 1993-02-16 | Sgs-Thomson Microelectronics, Inc. | Method of making SRAM cell and structure with polycrystalline P-channel load devices |
US5196233A (en) | 1989-01-18 | 1993-03-23 | Sgs-Thomson Microelectronics, Inc. | Method for fabricating semiconductor circuits |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5696850A (en) * | 1979-12-30 | 1981-08-05 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
US4609568A (en) * | 1984-07-27 | 1986-09-02 | Fairchild Camera & Instrument Corporation | Self-aligned metal silicide process for integrated circuits having self-aligned polycrystalline silicon electrodes |
JP2667392B2 (en) * | 1986-09-26 | 1997-10-27 | 株式会社デンソー | Method for manufacturing polycrystalline semiconductor diode |
EP0344292B1 (en) * | 1987-12-02 | 1997-04-23 | Advanced Micro Devices, Inc. | A process of fabricating self-aligned semiconductor devices |
JPH0288249U (en) * | 1988-12-24 | 1990-07-12 |
-
1990
- 1990-04-30 US US07/516,272 patent/US5151387A/en not_active Ceased
-
1991
- 1991-03-25 EP EP91302575A patent/EP0455339B1/en not_active Expired - Lifetime
- 1991-03-25 DE DE69130622T patent/DE69130622T2/en not_active Expired - Fee Related
- 1991-04-25 JP JP3095055A patent/JP3064472B2/en not_active Expired - Fee Related
- 1991-04-30 KR KR1019910006936A patent/KR910019137A/en not_active Application Discontinuation
-
1992
- 1992-02-28 US US07/843,818 patent/US5279887A/en not_active Expired - Lifetime
-
1994
- 1994-09-29 US US08/316,035 patent/USRE37769E1/en not_active Expired - Lifetime
Patent Citations (46)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4214917A (en) | 1978-02-10 | 1980-07-29 | Emm Semi | Process of forming a semiconductor memory cell with continuous polysilicon run circuit elements |
US4178674A (en) | 1978-03-27 | 1979-12-18 | Intel Corporation | Process for forming a contact region between layers of polysilicon with an integral polysilicon resistor |
US4180826A (en) | 1978-05-19 | 1979-12-25 | Intel Corporation | MOS double polysilicon read-only memory and cell |
US4290185A (en) | 1978-11-03 | 1981-09-22 | Mostek Corporation | Method of making an extremely low current load device for integrated circuit |
US4322821A (en) * | 1978-12-22 | 1982-03-30 | U.S. Philips Corporation | Memory cell for a static memory and static memory comprising such a cell |
US4370798A (en) | 1979-06-15 | 1983-02-01 | Texas Instruments Incorporated | Interlevel insulator for integrated circuit with implanted resistor element in second-level polycrystalline silicon |
US4367580A (en) | 1980-03-21 | 1983-01-11 | Texas Instruments Incorporated | Process for making polysilicon resistors |
US4398335A (en) * | 1980-12-09 | 1983-08-16 | Fairchild Camera & Instrument Corporation | Multilayer metal silicide interconnections for integrated circuits |
US4554729A (en) | 1981-02-06 | 1985-11-26 | Hitachi, Ltd. | Method of making semiconductor memory device |
US4933735A (en) * | 1981-02-23 | 1990-06-12 | Unisys Corporation | Digital computer having control and arithmetic sections stacked above semiconductor substrate |
US4619037A (en) | 1981-05-31 | 1986-10-28 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device |
US4831424A (en) * | 1981-08-07 | 1989-05-16 | Hitachi, Ltd. | Insulated gate semiconductor device with back-to-back diodes |
US4617071A (en) * | 1981-10-27 | 1986-10-14 | Fairchild Semiconductor Corporation | Method of fabricating electrically connected regions of opposite conductivity type in a semiconductor structure |
JPS58135653A (en) | 1982-02-08 | 1983-08-12 | Toshiba Corp | Manufacture of semiconductor device |
US4535427A (en) | 1982-12-06 | 1985-08-13 | Mostek Corporation | Control of serial memory |
US4675715A (en) * | 1982-12-09 | 1987-06-23 | American Telephone And Telegraph Company, At&T Bell Laboratories | Semiconductor integrated circuit vertical geometry impedance element |
US4658378A (en) | 1982-12-15 | 1987-04-14 | Inmos Corporation | Polysilicon resistor with low thermal activation energy |
US4562640A (en) * | 1983-04-25 | 1986-01-07 | Siemens Aktiengesellschaft | Method of manufacturing stable, low resistance contacts in integrated semiconductor circuits |
US4505026A (en) | 1983-07-14 | 1985-03-19 | Intel Corporation | CMOS Process for fabricating integrated circuits, particularly dynamic memory cells |
JPS6068634A (en) | 1983-09-26 | 1985-04-19 | Nec Corp | Semiconductor device |
US4581623A (en) * | 1984-05-24 | 1986-04-08 | Motorola, Inc. | Interlayer contact for use in a static RAM cell |
US4677735A (en) * | 1984-05-24 | 1987-07-07 | Texas Instruments Incorporated | Method of providing buried contacts for N and P channel devices in an SOI-CMOS process using a single N+polycrystalline silicon layer |
US4560419A (en) | 1984-05-30 | 1985-12-24 | Inmos Corporation | Method of making polysilicon resistors with a low thermal activation energy |
US4561907A (en) | 1984-07-12 | 1985-12-31 | Bruha Raicu | Process for forming low sheet resistance polysilicon having anisotropic etch characteristics |
US4903096A (en) | 1984-08-23 | 1990-02-20 | Kabushiki Kaisha Toshiba | Semiconductor memory device with barrier layer |
US4907052A (en) | 1984-10-11 | 1990-03-06 | Kanegafuchi Kagaku Kogyo Kabushiki Kaisha | Semiconductor tandem solar cells with metal silicide barrier |
EP0182610A2 (en) | 1984-11-16 | 1986-05-28 | Fujitsu Limited | Semiconductor photodetector device |
US4654824A (en) * | 1984-12-18 | 1987-03-31 | Advanced Micro Devices, Inc. | Emitter coupled logic bipolar memory cell |
US4870033A (en) * | 1985-03-19 | 1989-09-26 | Yamaha Corporation | Method of manufacturing a multilayer electrode containing silicide for a semiconductor device |
US4804636A (en) * | 1985-05-01 | 1989-02-14 | Texas Instruments Incorporated | Process for making integrated circuits having titanium nitride triple interconnect |
US4792923A (en) * | 1985-08-30 | 1988-12-20 | Mitsubishi Denki Kabushiki Kaisha | Bipolar semiconductor memory device with double word lines structure |
JPS6298660A (en) | 1985-10-25 | 1987-05-08 | Hitachi Ltd | Semiconductor device |
US4968645A (en) | 1985-12-20 | 1990-11-06 | Sgs-Thomson Microelectronics S.R.L. | Method for manufacturing MOS/CMOS monolithic integrated circuits including silicide and polysilicon patterning |
US4874719A (en) * | 1986-05-06 | 1989-10-17 | Kabushiki Kaisha Toshiba | Method for manufacturing an electrical connection between conductor levels |
US4714685A (en) * | 1986-12-08 | 1987-12-22 | General Motors Corporation | Method of fabricating self-aligned silicon-on-insulator like devices |
US4849344A (en) * | 1986-12-11 | 1989-07-18 | Fairchild Semiconductor Corporation | Enhanced density modified isoplanar process |
US4877483A (en) | 1987-07-03 | 1989-10-31 | S.G.S. Thomson Microelectronics, S.A. | Method for contact between two conductive or semi-conductive layers deposited on a substrate |
US4922455A (en) | 1987-09-08 | 1990-05-01 | International Business Machines Corporation | Memory cell with active device for saturation capacitance discharge prior to writing |
US4950620A (en) | 1988-09-30 | 1990-08-21 | Dallas Semiconductor Corp. | Process for making integrated circuit with doped silicon dioxide load elements |
US5107322A (en) | 1988-11-10 | 1992-04-21 | Seiko Epson Corporation | Wiring or conductor interconnect for a semiconductor device or the like |
US5196233A (en) | 1989-01-18 | 1993-03-23 | Sgs-Thomson Microelectronics, Inc. | Method for fabricating semiconductor circuits |
US4966864A (en) | 1989-03-27 | 1990-10-30 | Motorola, Inc. | Contact structure and method |
US5021849A (en) | 1989-10-30 | 1991-06-04 | Motorola, Inc. | Compact SRAM cell with polycrystalline silicon diode load |
US4948747A (en) * | 1989-12-18 | 1990-08-14 | Motorola, Inc. | Method of making an integrated circuit resistor |
US5151376A (en) | 1990-05-31 | 1992-09-29 | Sgs-Thomson Microelectronics, Inc. | Method of making polycrystalline silicon resistors for integrated circuits |
US5187114A (en) | 1991-06-03 | 1993-02-16 | Sgs-Thomson Microelectronics, Inc. | Method of making SRAM cell and structure with polycrystalline P-channel load devices |
Non-Patent Citations (15)
Title |
---|
1989 Symposium on VLSI Technology, Digest of Technical Papers, pp. 61-62, May 22-25, "A New Process Technology for a 4Mbit SRAM with Polysilicon Load Resistor Cell", Yuzuriha et al. |
IEEE GaAs IC Symposium, 1984, Hayashi et al., "ECL-Compatible GaAs SRAM Circuit Technology for High Performance Computer Application", pp. 111-114. |
IEEE J of Solid State Cir., vol. 18. No. 5, Oct. 1983, "A 4.5 ns Access Time 1Kx4 Bit ECL RAM", Nakubo et al., pp. 515-520. |
IEEE J of Solid State Cir., vol. 18. No. 5, Oct. 1983, "A 4.5 ns Access Time 1K×4 Bit ECL RAM", Nakubo et al., pp. 515-520. |
IEEE J. of Solid State Cir, vol. 21, No. 5, Oct. 1986, "A 1.0-ns 5-Kbit ECL RAM", Chuang et al., pp. 670-674. |
IEEE J. of Solid State Cir, vol. 24, No. 2, Apr. 1989, "A Bipolar ECL Static RAM Using Polysilicon Diode Loaded Memory Cell", Hwang et al., pp. 504-511. |
IEEE Trans Electron Dev., vol. 40. No. 2, Feb. 1993, "Experimental Characterization of the Diode-Type Polysilicon Loads for CMOS SRAM", Kalnitsky et al., pp. 358-363. |
IEEE Trans. Electron Dev. vol. 32, No. 9, Sept. 1985, "Ion-Implanted Thin Polycrystalline High-Value Resistors for High-Density Poly-Load Static RAM Applications", Ohzone et al. |
IEEE Trans. Electron Dev., vol. 30, No. 1, Jan. 1993, "Gigaohm-Range Polycrystalline Silicon Resistors for Microelectronic Appn", Mohan et al., pp. 45-51. |
Physics of Semiconductors, S.M. Sze, 1981, pp. 304-305. |
Silicon Processing for the VLSI Era, vol. 2-Process Integration, pp. 84-85, 176-177, x-xv, 1986, Wolf. |
Solid State Elect, vol. 30, No. 3, pp. 339-343, 1987, "Characterization of Aluminum/LPCVD Polysilicon Schottky Barrier Diodes", Chen et al. |
Solid State Elect., vol. 28 No. 12, pgs. 1255-1261 1985 "Field Enhanged Emission and Capture in Polysilicon pn Junctions", Greve et al. |
Solid State Electronics, vol. 15, pp. 1103-1106, 1972, "P-N junctions in Polycrystalline Silicon Films," Manoliu et al. |
Wolf, Stanley, Silicon Processing for the VLSI Era, vol. 2, Lattice Press, Sunset Beach, Calif. (1990), Chapters 3&4.* * |
Also Published As
Publication number | Publication date |
---|---|
EP0455339A2 (en) | 1991-11-06 |
DE69130622D1 (en) | 1999-01-28 |
JP3064472B2 (en) | 2000-07-12 |
EP0455339B1 (en) | 1998-12-16 |
JPH0737885A (en) | 1995-02-07 |
DE69130622T2 (en) | 1999-05-06 |
EP0455339A3 (en) | 1992-06-03 |
US5279887A (en) | 1994-01-18 |
US5151387A (en) | 1992-09-29 |
KR910019137A (en) | 1991-11-30 |
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