USRE34821E - High speed junction field effect transistor for use in bipolar integrated circuits - Google Patents

High speed junction field effect transistor for use in bipolar integrated circuits Download PDF

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USRE34821E
USRE34821E US08/036,935 US3693593A USRE34821E US RE34821 E USRE34821 E US RE34821E US 3693593 A US3693593 A US 3693593A US RE34821 E USRE34821 E US RE34821E
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layer
region
conductivity type
field effect
effect transistor
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US08/036,935
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Wadie N. Khadder
James P. Vokac
Robert C. Dobkin
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Analog Devices International ULC
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Linear Technology LLC
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Priority claimed from US07/553,181 external-priority patent/US5012305A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
    • H01L29/66901—Unipolar field-effect transistors with a PN junction gate, i.e. JFET with a PN homojunction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate

Definitions

  • This invention relates generally to semiconductor transistor devices, and more particularly to a high speed junction field effect transistor.
  • JFETs junction field effect transistors
  • BIFETs bipolar integrated circuits
  • One such transistor is disclosed in U.S. Pat. No. 4,176,368.
  • Operating speed is an important characteristic of such a transistor.
  • BIFET structures have included top and bottom gates with the top gate comprising a lightly doped region above the transistor channel region and with the top and bottom gates electrically connected through the semiconductor structure.
  • U.S. Pat. No. 4,176,368 proposes a higher speed BIFET by forming a more heavily doped region in the lightly doped top gate between and separated from the source and drain regions of the transistor. The heavily doped region reduces the gate conductance from 5-15 kilo-ohms per square to a range of 500-1500 ohms per square.
  • JFETS having independent upper and lower gate contacts are known.
  • the prior art teaches the use of barrier metals on the surface of the upper gate to prevent penetration of aluminum contacts into the underlying silicon material.
  • Use of the barrier metal creates a thermal mismatch with the silicon leading to hysteresis effects during thermal cycling which degrade the device.
  • This invention is directed to an improved higher speed BIFET.
  • a highly doped polycrystalline silicon gate contact is formed on the surface of the thin, lightly doped top gate region extending between the source and drain regions.
  • the ion implanted silicon gate contact is electrically separated from the bottom contact, thereby permitting a four-terminal device operation, if desired.
  • a metal contact such as aluminum, for example, can be placed on the surface of the polysilicon layer to further reduce resistance.
  • the polycrystalline layer inhibits punch through (diffusion) of the aluminum contact metal into the gate and channel regions by the aluminum contact.
  • the lightly doped top gate layer beneath the polysilicon gate contact can be more heavily doped by diffusion from the highly doped polycrystalline layer to increase its conductivity.
  • the gate resistance in accordance with this invention can be reduced to on the order of 1-40 ohms per square, as opposed to the 500-1500 ohms per square for the device disclosed in the '368 patent.
  • the polycrystalline layer permits high temperature processing and the formation of thermal oxide on the surface of the layer.
  • an object of the invention is to provide an improved silicon BIFET.
  • Another object of the invention is to provide a BIFET having increased operating speed.
  • a further object of this invention is to provide a BIFET which can be thermally cycled without degradation of device performance.
  • FIG. 1 is a sectional view of a BIFET device in accordance with the prior art.
  • FIG. 2 is a sectional view of another BIFET device in accordance with the prior art.
  • FIG. 3 is a sectional view of a BIFET device in accordance with one embodiment of the invention.
  • FIG. 4 is a sectional view in accordance with another embodiment of the invention.
  • FIGS. 1 and 2 are sectional views of prior art BIFET devices as disclosed in U.S. Pat. No. 4,176,368.
  • an N-type epitaxial layer 10 is formed on a surface of P-type silicon substrate 12 with a device region defined by P+ isolation diffusion ring 14.
  • An N+ buried layer 16 is formed by doping a surface region of substrate 12 prior to the epitaxial growth of layer 10.
  • a BIFET device is then formed in the epitaxial layer 10 with a source region 18 and a spaced drain region 20 formed by diffusion with P+ dopants.
  • a gate contact 22 is formed by diffusion with N+ dopant.
  • a P-type channel region 24 is formed by ion implantation between the source and drain region 18, 20, and a lightly doped top gate layer 26 is formed by ion implantation on the surface between the source and drain regions.
  • the N-type top gate layer 26 is interconnected with the bottom gate contact defined by epitaxial layer 10 through the epitaxial structure.
  • Metal contacts 28 are made to the source, drain and gate region.
  • a high doped region 30 in the lightly doped top gate contact region 26 is formed by the selective introduction of N-type dopants by ion implantation, for example.
  • the N+ region 30 is electrically interconnected with the bottom gate contact comprising epitaxial layer 10 through the epitaxial structure. Due to the increased conductance of N+ layer 30, the gate resistance is reduced from approximately 5-15 kilo-ohms per square with the device of FIG. 1 to 500-1500 ohms per square with the device of FIG. 2. The reduction in gate resistance results in a significant increase in operating speed.
  • FIG. 3 is a sectional view of a silicon BIFET device in accordance with this invention. Again, like elements have the same reference numbers as in FIGS. 1 and 2.
  • a highly doped polysilicon contact 32 is made to an intermediate portion of the lightly doped top layer 26, spaced from the source and drain region 18, 20.
  • a highly doped region 30 is provided in the lightly doped gate layer 26 beneath the contact 32 as in the embodiment of FIG. 2.
  • the increased speed of operation of the device of FIG. 3 depends primarily on the provision of the high conductance contact as described below, and only secondarily on the provision of the highly doped region 30. Thus, the provision of region 30 is not essential to the invention.
  • the contact comprises a thin layer of highly doped polycrystalline silicon 32 and a metal layer 34 of aluminum, for example, provided on the top surface of contact 32, thereby further increasing the conductance of the contact and further increasing the speed of operation.
  • the highly doped polysilicon layer 32 not only increases the conductance of the contact to the gate region 30, but also inhibits punch through of the aluminum contact during subsequent high temperature processing steps, and provides impurities which diffuse into the region 30 to increase its conductance.
  • the polysilicon layer is thermally matched to the substrate, thereby minimizing degradation of the device during thermal cycling.
  • the top gate contact is isolated from the bottom gate contact, thereby providing a four-terminal device.
  • the smaller area of the top gate metal contact 34 reduces the parasitic capacitance and leakage current.
  • FIG. 4 shows an embodiment of the invention without a high conductance region 30.
  • the impurities from the polysilicon layer are not only allowed to diffuse into the underlying gate region 26, but also into the channel region as shown by the dotted line 36. This effectively reduces the thickness of the channel and increases the frequency of operation.

Abstract

A high speed BIFET junction field effect transistor is formed in an epitaxial layer of one conductivity type and includes source and drain regions of opposite conductivity type interconnected by a thin channel region of the opposite conductivity type. A thin surface layer of the one conductivity type is formed over the channel region, and a highly conductive contact is formed on the surface layer intermediate the source and drain regions. The surface contact can comprise highly doped polycrystalline silicon material with a metal layer on the surface thereof. The surface contact and the epitaxial layer underlying the channel region comprise gates for the field effect transistor. Increased speed of operation comes from the increased conductivity of the surface contact.

Description

This is a continuation-in-part of co-pending application Ser. No. 931,263 filed Nov. 17, 1986 and now abandoned.
BACKGROUND OF THE INVENTION
This invention relates generally to semiconductor transistor devices, and more particularly to a high speed junction field effect transistor.
The use of junction field effect transistors (JFETs) in bipolar integrated circuits is known (BIFETs). One such transistor is disclosed in U.S. Pat. No. 4,176,368. Operating speed is an important characteristic of such a transistor. BIFET structures have included top and bottom gates with the top gate comprising a lightly doped region above the transistor channel region and with the top and bottom gates electrically connected through the semiconductor structure. U.S. Pat. No. 4,176,368 proposes a higher speed BIFET by forming a more heavily doped region in the lightly doped top gate between and separated from the source and drain regions of the transistor. The heavily doped region reduces the gate conductance from 5-15 kilo-ohms per square to a range of 500-1500 ohms per square.
JFETS having independent upper and lower gate contacts are known. The prior art teaches the use of barrier metals on the surface of the upper gate to prevent penetration of aluminum contacts into the underlying silicon material. Use of the barrier metal creates a thermal mismatch with the silicon leading to hysteresis effects during thermal cycling which degrade the device.
SUMMARY OF THE INVENTION
This invention is directed to an improved higher speed BIFET. Briefly, a highly doped polycrystalline silicon gate contact is formed on the surface of the thin, lightly doped top gate region extending between the source and drain regions. The ion implanted silicon gate contact is electrically separated from the bottom contact, thereby permitting a four-terminal device operation, if desired. A metal contact such as aluminum, for example, can be placed on the surface of the polysilicon layer to further reduce resistance. The polycrystalline layer inhibits punch through (diffusion) of the aluminum contact metal into the gate and channel regions by the aluminum contact. The lightly doped top gate layer beneath the polysilicon gate contact can be more heavily doped by diffusion from the highly doped polycrystalline layer to increase its conductivity. Advantageously, the gate resistance in accordance with this invention can be reduced to on the order of 1-40 ohms per square, as opposed to the 500-1500 ohms per square for the device disclosed in the '368 patent. The polycrystalline layer permits high temperature processing and the formation of thermal oxide on the surface of the layer.
OBJECTS OF THE INVENTION
Accordingly, an object of the invention is to provide an improved silicon BIFET.
Another object of the invention is to provide a BIFET having increased operating speed.
A further object of this invention is to provide a BIFET which can be thermally cycled without degradation of device performance.
The objects and features of this invention will be more readily apparent from the following detailed description and dependent claims when taken with the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a sectional view of a BIFET device in accordance with the prior art.
FIG. 2 is a sectional view of another BIFET device in accordance with the prior art.
FIG. 3 is a sectional view of a BIFET device in accordance with one embodiment of the invention.
FIG. 4 is a sectional view in accordance with another embodiment of the invention.
DETAILED DESCRIPTION OF THE DRAWINGS
Turning to the drawings, FIGS. 1 and 2 are sectional views of prior art BIFET devices as disclosed in U.S. Pat. No. 4,176,368. In accordance with the device of FIG. 1, an N-type epitaxial layer 10 is formed on a surface of P-type silicon substrate 12 with a device region defined by P+ isolation diffusion ring 14. An N+ buried layer 16 is formed by doping a surface region of substrate 12 prior to the epitaxial growth of layer 10. A BIFET device is then formed in the epitaxial layer 10 with a source region 18 and a spaced drain region 20 formed by diffusion with P+ dopants. A gate contact 22 is formed by diffusion with N+ dopant. A P-type channel region 24 is formed by ion implantation between the source and drain region 18, 20, and a lightly doped top gate layer 26 is formed by ion implantation on the surface between the source and drain regions. The N-type top gate layer 26 is interconnected with the bottom gate contact defined by epitaxial layer 10 through the epitaxial structure. Metal contacts 28 are made to the source, drain and gate region.
In order to increase the speed of the device shown in FIG. 1, the '368 patent proposes the structure disclosed in FIG. 2. The same reference numbers are used for like elements. In this embodiment, a high doped region 30 in the lightly doped top gate contact region 26 is formed by the selective introduction of N-type dopants by ion implantation, for example. Again, the N+ region 30 is electrically interconnected with the bottom gate contact comprising epitaxial layer 10 through the epitaxial structure. Due to the increased conductance of N+ layer 30, the gate resistance is reduced from approximately 5-15 kilo-ohms per square with the device of FIG. 1 to 500-1500 ohms per square with the device of FIG. 2. The reduction in gate resistance results in a significant increase in operating speed.
FIG. 3 is a sectional view of a silicon BIFET device in accordance with this invention. Again, like elements have the same reference numbers as in FIGS. 1 and 2. In accordance with the invention, a highly doped polysilicon contact 32 is made to an intermediate portion of the lightly doped top layer 26, spaced from the source and drain region 18, 20. As illustrated in FIG. 3, a highly doped region 30 is provided in the lightly doped gate layer 26 beneath the contact 32 as in the embodiment of FIG. 2. However, the increased speed of operation of the device of FIG. 3 depends primarily on the provision of the high conductance contact as described below, and only secondarily on the provision of the highly doped region 30. Thus, the provision of region 30 is not essential to the invention.
In a preferred embodiment, the contact comprises a thin layer of highly doped polycrystalline silicon 32 and a metal layer 34 of aluminum, for example, provided on the top surface of contact 32, thereby further increasing the conductance of the contact and further increasing the speed of operation. The highly doped polysilicon layer 32 not only increases the conductance of the contact to the gate region 30, but also inhibits punch through of the aluminum contact during subsequent high temperature processing steps, and provides impurities which diffuse into the region 30 to increase its conductance. The polysilicon layer is thermally matched to the substrate, thereby minimizing degradation of the device during thermal cycling.
The top gate contact is isolated from the bottom gate contact, thereby providing a four-terminal device. The smaller area of the top gate metal contact 34 reduces the parasitic capacitance and leakage current.
FIG. 4 shows an embodiment of the invention without a high conductance region 30. In this embodiment, the impurities from the polysilicon layer are not only allowed to diffuse into the underlying gate region 26, but also into the channel region as shown by the dotted line 36. This effectively reduces the thickness of the channel and increases the frequency of operation.
The provision of a highly doped polysilicon gate contact on the lightly doped top gate layer and diffusion of impurities thereinto can reduce the top gate resistance to the order of 1-40 ohms per square. This low resistance, coupled with the four-terminal operation of the BIFET, enhances the operating speed significantly over the prior art BIFET structures.
While the invention has been described with reference to specific embodiments, the description is illustrative of the invention, and not to be construed as limiting the invention. Various modifications and applications may be apparent by those skilled in the art without departing from the true spirit and scope of the invention as defined by the appended claims.

Claims (4)

    What is claimed is: .[.1. A high speed junction field effect transistor comprising
  1. polysilicon layer..]. 3. A high speed junction field effect transistor comprising
    a silicon semiconductor body region of one conductivity type,
    first and second regions of opposite conductivity type formed in a surface of said body region and spaced from each other, said first and second regions forming a source and a drain of said transistor,
    a thin channel region of said opposite conductivity type in said body region and interconnecting said first and second regions,
    a thin surface gate layer of said one conductivity type overlying said channel region and extending from said first region to said second region, and
    a surface contact on said surface gate .[.region.]. .Iadd.layer .Iaddend.between said first and second regions and electrically isolated from said body region, said surface contact comprising polycrystalline silicon layer of said one conductivity type and having a conductivity greater than the conductivity of said surface gate layer, said body region beneath said channel region and said surface contact comprising electrically separate gates for said transistor, said thin surface gate layer and an upper region of said channel region include impurities diffused thereinto from said polysilicon layer and
  2. an aluminum metal contact on said polycrystalline silicon layer. 4. The field effect transistor as in claim 3 wherein said semiconductor body region comprises an epitaxial layer, and further including a substrate of said opposite conductivity type on which said epitaxial layer is formed.
  3. The field effect transistor as in claim 4 and further including a buried layer of said .[.first.]. .Iadd.one .Iaddend.conductivity type formed in said substrate at the interface of said epitaxial layer and
  4. positioned beneath said first and second regions. 6. The field effect transistor as in claim 5 and further including an isolation region of said opposite conductivity type extending from the surface of said epitaxial layer to said substrate and surrounding said first and second regions.
US08/036,935 1986-11-17 1993-03-25 High speed junction field effect transistor for use in bipolar integrated circuits Expired - Lifetime USRE34821E (en)

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US08/036,935 USRE34821E (en) 1986-11-17 1993-03-25 High speed junction field effect transistor for use in bipolar integrated circuits

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US93126386A 1986-11-17 1986-11-17
US07/553,181 US5012305A (en) 1986-11-17 1990-07-13 High speed junction field effect transistor for use in bipolar integrated circuits
US08/036,935 USRE34821E (en) 1986-11-17 1993-03-25 High speed junction field effect transistor for use in bipolar integrated circuits

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US93126386A Continuation-In-Part 1986-11-17 1986-11-17
US07/553,181 Reissue US5012305A (en) 1986-11-17 1990-07-13 High speed junction field effect transistor for use in bipolar integrated circuits

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6346446B1 (en) * 1998-06-01 2002-02-12 Massachusetts Institute Of Technology Methods of forming features of integrated circuits using modified buried layers

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GB997996A (en) * 1962-02-19 1965-07-14 Motorola Inc Field effect device and method of manufacturing the same
US3333115A (en) * 1963-11-20 1967-07-25 Toko Inc Field-effect transistor having plural insulated-gate electrodes that vary space-charge voltage as a function of drain voltage
US3335342A (en) * 1962-06-11 1967-08-08 Fairchild Camera Instr Co Field-effect transistors
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US4267012A (en) * 1979-04-30 1981-05-12 Fairchild Camera & Instrument Corp. Process for patterning metal connections on a semiconductor structure by using a tungsten-titanium etch resistant layer
US4482907A (en) * 1981-03-10 1984-11-13 Thomson-Csf Planar-type field-effect transistor having metallized-well electrodes and a method of fabrication of said transistor
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US4185291A (en) * 1977-06-30 1980-01-22 Matsushita Electric Industrial Co., Ltd. Junction-type field effect transistor and method of making the same
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US4267012A (en) * 1979-04-30 1981-05-12 Fairchild Camera & Instrument Corp. Process for patterning metal connections on a semiconductor structure by using a tungsten-titanium etch resistant layer
US4482907A (en) * 1981-03-10 1984-11-13 Thomson-Csf Planar-type field-effect transistor having metallized-well electrodes and a method of fabrication of said transistor
WO1986002203A1 (en) * 1984-10-05 1986-04-10 Analog Devices, Incorporated Low-leakage jfet
US4985739A (en) * 1984-10-05 1991-01-15 Analog Devices, Incorporated Low-leakage JFET

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6346446B1 (en) * 1998-06-01 2002-02-12 Massachusetts Institute Of Technology Methods of forming features of integrated circuits using modified buried layers

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