USRE33209E - Monolithic semiconductor switching device - Google Patents

Monolithic semiconductor switching device Download PDF

Info

Publication number
USRE33209E
USRE33209E US06/539,111 US53911183A USRE33209E US RE33209 E USRE33209 E US RE33209E US 53911183 A US53911183 A US 53911183A US RE33209 E USRE33209 E US RE33209E
Authority
US
United States
Prior art keywords
regions
region
iaddend
iadd
monolithic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US06/539,111
Inventor
James D. Plummer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Leland Stanford Junior University
Original Assignee
Leland Stanford Junior University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US05/943,200 priority Critical patent/US4199774A/en
Application filed by Leland Stanford Junior University filed Critical Leland Stanford Junior University
Priority to US06539111 priority patent/USRE33209F1/en
Application granted granted Critical
Publication of USRE33209E publication Critical patent/USRE33209E/en
Publication of USRE33209F1 publication Critical patent/USRE33209F1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/64Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65Lateral DMOS [LDMOS] FETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411Insulated-gate bipolar transistors [IGBT]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411Insulated-gate bipolar transistors [IGBT]
    • H10D12/441Vertical IGBTs
    • H10D12/461Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D18/00Thyristors
    • H10D18/40Thyristors with turn-on by field effect 
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D18/00Thyristors
    • H10D18/60Gate-turn-off devices 
    • H10D18/65Gate-turn-off devices  with turn-off by field effect 
    • H10D18/655Gate-turn-off devices  with turn-off by field effect  produced by insulated gate structures
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D18/00Thyristors
    • H10D18/80Bidirectional devices, e.g. triacs 
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/611Insulated-gate field-effect transistors [IGFET] having multiple independently-addressable gate electrodes influencing the same channel
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/64Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/645Bidirectional devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/101Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
    • H10D84/151LDMOS having built-in components
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149Source or drain regions of field-effect devices
    • H10D62/151Source or drain regions of field-effect devices of IGFETs 

Definitions

  • This invention relates generally to semiconductor circuits and devices, and more particularly the invention relates to an integrated circuit device having current dependent properties.
  • MOS field effect transistor and the multijunction silicon controlled rectifier and Triac are known semiconductor devices which have current switching applications.
  • the MOS transistor generally operates at lower voltages and current levels and can be used in linear applications.
  • One form of MOS transistor is the double diffused device in which a very short channel region is defined by diffusing a region of one conductivity type in a substrate of opposite conductivity type and then diffusing a region of opposite conductivity type in the first region.
  • SCR silicon controlled rectifier
  • Triac is normally employed for higher voltage and current switching applications.
  • the MOS transistor employs a field effect channel created by the application of a gate voltage, while the SCR typically is turned on by forward biasing a PN junction which renders the device conductive.
  • the Triac is similar to the SCR but provides full wave switching.
  • An object of this invention is a new and improved current switching device.
  • Another object of the invention is an electrical circuit device which has the characteristics of an MOS transistor and of a full wave silicon switch.
  • Still another object of the invention is a monolithic semiconductor device having operational characteristics which are current dependent.
  • a feature of the invention is a monolithic semiconductor device including two merged double diffused MOS transistors.
  • a device in accordance with the invention comprises a semiconductor body having at least one major surface and a region adjacent to the surface of one conductivity.
  • First and second spaced regions of opposite conductivity type are formed in the body region and abutting the major surface.
  • Third and fourth regions of the one conductivity type are formed in the first and second regions, respectively, abutting the major surface and defining first and second channel regions in the first and second regions, respectively.
  • a layer of insulation is formed on the major surface and an ohmic contact is formed on the layer of insulation and adjacent to the first and second gate regions. An ohmic contact is made to the first and third regions, and an ohmic contact is made to the second and fourth regions.
  • An ohmic contact between the first and third regions and between the second and fourth regions may be facilitated by a separate diffusion of the same conductivity type as regions one and two adjacent to regions one and two. This diffusion is normally performed prior to diffusion of regions one and two, with a separate masking operation.
  • the first and third regions cooperatively function with the body region as a first double diffused MOS transistor, and the second and fourth regions cooperatively function with the body region as a second double diffused MOS transistor.
  • the body region functions as a merged drain of the two transistors.
  • a fifth diffused region of the same conductivity type as the body region can be formed in the body region between the first and second diffused regions.
  • the device functions as serially connected MOS transistors having merged drain regions, while at higher voltages and operating currents the device functions as a full wave silicon switch.
  • FIG. 1 is a cross section view of a conventional double diffused MOS transistor.
  • FIG. 2 is a cross section view of one embodiment of a switching device in accordance with the present invention.
  • FIG. 3A and FIG. 3B are an electrical schematic and voltage-current characteristics, respectively, of the device of FIG. 2 at lower operating voltages.
  • FIGS. 4A and 4B are an electrical schematic and voltage-current characteristics, respectively, of the device of FIG. 2 operated at higher voltage level.
  • FIG. 5A .[.and.]..Iadd., .Iaddend.FIG. 5B, .Iadd.and FIG. 5C .Iaddend. are an electrical schematic and voltage-current characteristics, respectively, of the device of FIG. 2 operated at still higher voltages.
  • FIG. 6 is the doping profile along the silicon surface of one embodiment of the device of FIG. 2.
  • FIG. 7 is a cross section view of another embodiment of a switch device in accordance with the present invention.
  • FIGS. 8A, 8B, 8C illustrate schematically several applications of the device of FIG. 7.
  • FIGS. 9-13 are cross section views of other embodiments of devices in accordance with the invention.
  • FIG. 14 is an electrical schematic of the device shown in FIGS. 12 and 13.
  • FIG. 1 is a cross section view of a conventional double diffused MOS transistor (DMOS) formed in a lightly doped (N-) semiconductor body 10.
  • the device includes a first P+ diffused region 12a, a second P diffused region 12 overlapping a portion of region 12a, a third N+ diffused region 14 formed in the P region 12 with all three regions being adjacent to a major surface of the semiconductor body 10.
  • the N+ region 14 comprises the source of the transistor, and the portion 16 of P region 12 adjacent to the major surface and between the N+ region 14 and the N- body 10 comprises the transistor channel.
  • An N+ diffused region 18 spaced from the first two regions along with the adjacent N- body region comprises the transistor drain.
  • a silicon oxide layer 20 is formed on the major surface of the semiconductor body 10 with a metallic ohmic contact 22 made to regions 12, 12a and 14, a metallic ohmic contact 24 made to the drain region 18, and a metallic layer for the gate electrode 26 formed on the layer of insulation 20 above the channel region 16.
  • the device functions as a typical MOS transistor with a short channel region provided by the double diffused structure.
  • the DMOS device is inherently asymmetrical; that is, the source and drain terminals are not interchangeable. This asymmetry can be a problem in many circuit applications, and a device in accordance with the present invention overcomes this limitation.
  • the device is effectively two DMOS devices shown generally at 30 and 32 integrated in a monolithic semiconductor body 36 with merged drain regions.
  • the DMOS transistor 30 comprises a source N+ region 33, a channel region 34 formed in P region 35 and a drain comprising the N- semiconductor body 36 and the N+ diffused region 37.
  • DMOS transistor 32 comprises an N+ source 38, a P channel region 39 formed in P region 40, and a drain comprising the N- body 36 and the N+ diffused region 37.
  • Regions 35a and 40a again are P+ diffused regions designed to facilitate ohmic contact to the P channel regions 35 and 40.
  • I/O contact 42 is made to regions 33, 35 and 35a
  • a second I/O contact 44 is made to regions 38, 40 and 40a
  • a gate electrode 46 is formed on the silicon oxide layer 48 above the channel regions 34, 39.
  • the device Due to the symmetrical construction of the device as shown in FIG. 2, the device has symmetry of operation, i.e. the two I/O contacts are interchangeable. Importantly, the operational characteristics of this device change with the operating voltage and current levels.
  • FIG. 3A is an electrical schematic of the device in FIG. 2 operated at low voltage and current levels (e.g. less than one volt across the device, gate voltage of a few volts above the threshold voltage), and FIG. 3B is the current-voltage operating characteristics of the device of FIG. 3A.
  • the two DMOS transistors 30 and 32 are shown serially connected with the I/O terminals 42, 44 connected to the source regions of transistors 30 and 32, respectively, and gate terminal 46 controlling the gates of both transistors.
  • Diode 52 formed by P region 35 and the N- body 36 is connected in parallel with transistor 30, and diode 50 formed by P region 40 and the N- body 36 is connected in parallel with transistor 32.
  • FIG. 3B is a plot of current vs. voltage for low-level operation wherein the device function in accordance with the circuit illustrated in FIG. 3A.
  • the device By increasing current flow through the device by increasing gate voltage, for example, an applied voltage of +2 volts on one I/O terminal and a +10 volt gate potential, the device assumes an electrical and equivalent electrical schematic as demonstrated in FIGS. 5A and 5B, with the other I/O terminal grounded. In this mode of operation the device assumes the characteristics of a Triac with switching action to a low resistance device, similar to that observed in PNPN four layer structures.
  • the structure shown in FIG. 2 can be viewed as a lateral NPNPN structure, or a symmetrical PNPN arrangement, between the two I/O terminals.
  • an NPN transistor 62 formed by regions 33, 35 and 36 of the structure in FIG. 2 is added to the circuit of FIG.
  • transistor 62 shunting DMOS transistor 30. Both electrons and holes continue to contribute to the overall device current, however, the holes collected by the P region 35 (FIG. 2) flow through a relatively high resistance before reaching the I/O contact 42.
  • This resistance is denoted 64 in the schematic of FIG. 5A, and is physically analogous to the base resistance in a bipolar transistor and is an inherent part of the DMOS structure. The resistance is a distributed resistor and holes are collected all along its length. The voltage drop along the resistor will tend to forward bias the PN+ junction (region 35, 33) which is the base-emitter junction of the NPN transistor whose collector is the N- body 36.
  • FIG. .[.5B.]. .Iadd.5C. .Iaddend.Transistors 60 and 62 are equivalent to the arrangement of PNP and NPN devices used in conventional Triacs and SCRs.
  • the Triac or SCR is switched by applying a trigger voltage from an external source. While the device as illustrated in FIG. 2 is triggered to a low resistance state when the current through the device is increased by increasing the gate voltage, the device can be made to operate as a conventional SCR by forward biasing a junction. If separate ohmic contacts are formed to regions 35a and 33, externally forward biasing the P+N+ junction between regions 35a and 33 will switch the device to its low resistance state. However, the device illustrated in FIG. 2 is switched to a low resistance mode by an MOS device in parallel with the Triac and not by forward biasing the junction externally, as is found with the conventional Triacs and SCRs. At low current levels before the Triac fires, the MOS characteristics of the structure dominate. After firing the Triac, the device becomes a low resistance device.
  • FIG. 6 illustrates the surface doping profile for one switch device in accordance with the present invention. Absolute surface doping concentration is illustrated along the ordinate and distance across the device is illustrated along the abscissa. Relating the doping concentration to the device illustrated in cross section in FIG. 2, the N+ regions 33, 37 and 38 have a dopant concentration on the order of 10 20 impurities per cubic centimeter. The P regions which comprise the channel regions of the two DMOS transistors 34, 39 have a peak dopant concentration on the order of 5 ⁇ 10 16 impurities per cubic centimeter. The dopant concentration of the N- semiconductor body is on the order of 10 15 impurities per cubic centimeter.
  • P+ diffusions are first formed to facilitate ohmic contact to the DMOS transistor channel regions. Then sequential diffusions of boron (P type) and phosphorus or arsenic (N type) are made employing conventional diffusion techniques to form the P and N+ regions. Ion implantation may also be advantageously used to introduce the boron (P type) impurity for the channel region of the devices.
  • the gate oxidation is then formed over the channel regions, contact holes are made for the I/O contacts, metal is formed over the surface of the device and the metal pattern is defined by conventional photoresist masking and etching techniques.
  • the maximum doping in the P region at the surface under the gate along with the gate oxide thickness and the oxide charge density determine the DMOS threshold voltage.
  • the channel width largely determines the DMOS transconductance and on resistance.
  • the channel width also affects the Triac trigger current because the Triac is triggered by a specific current density flowing through the device.
  • the DMOS properties are largely independent of the channel length.
  • the channel doping profile determines directly the DMOS threshold voltage. In addition, the current density at which switching to the low resistance mode of operation occurs is affected by this profile.
  • the doping level in the N- semiconductor body affects the device breakdown voltage, the DMOS on resistance and the lateral PNP transport efficiency.
  • the N+ drain region in the middle of the device is important in order to increase the breakdown voltage. If this diffused region is not included a parasitic P channel MOS transistor across the surface will reduce the breakdown voltage to the field oxide threshold voltage which is typically 20 to 40 volts. In addition, this N+ region increases the lateral PNP transport efficiency. The lateral dimension of the N+ region should be minimized as it degrades the PNP transport efficiency.
  • the semiconductor body region 36 in this embodiment comprises an epitaxial layer formed on a P- substrate 70.
  • the structure may comprise a plurality of switching devices with each device isolated by means of diffused P+ regions 72 and 74 which extend through the epitaxial layer 36 to the underlying substrate 70 and surround the device.
  • a P+ substrate collects injected holes thus delaying the turn-on of the Triac lateral structure.
  • Experimental results indicate that depending upon device geometry 10% to 50% of the injected holes are collected by the substrate before the Triac fires.
  • the efficiency of the device is not affected at low voltage and current levels when all of the device current is carried by the MOS transistors.
  • an N+ buried layer between the N- epitaxial layer and the P- substrate, a reduction in injected holes captured by the substrate would be effected.
  • Such buried layers are commonly employed in commercial integrated circuits and are readily acapted in standard production techniques.
  • dielectric isolation techniques can be employed instead of diffused isolation as shown in FIG. 7. By employing dielectric isolation the P- substrate of FIG. 7 can be replaced with an insulator, and consequently injected holes are not collected by the substrate.
  • the P+ diffused regions, 72, 74 can be replaced by a dielectric such as silicon oxide.
  • the N+ region 37 spaced from the two double diffused regions is not necessary for low voltage. Triac operation and it can be eliminated if the device is not operated at high voltages. By eliminating this N+ region, the base width of the lateral PNP transistor can be reduced, resulting in lower triggering currents for the Triac and lower on resistance for the DMOS device. However, as indicated above the elimination of the N+ regoin creates a parasitic PMOS transistor between the two P diffused regions thus limiting the device breakdown voltage.
  • the separate ohmic contact made to the N+ region 37 as illustrated in FIG. 7 allows more versatility in operation of the device.
  • the device can still be operated as a switching device as above described and as illustrated schematically in FIG. 8A.
  • the N+ connection 78 can be left floating or can be connected to the +V potential applied to terminal .[.42.]. .Iadd.44.Iaddend.. By connecting the terminal to the +V potential, the DMOS characteristics will dominate up to a higher voltage and current level before the device becomes a low resistance switch.
  • the device can be used as a standard DMOS transistor over its full operating range by connecting terminals 42 and 44 together as the source, and the N+ contact 78 becomes the drain.
  • the device is used as a high level analog switch wherein a transducer 80 is driven at a high voltage with the transducer also used as part of a receiver.
  • the Triac capability is used with the transmitter, and the single DMOS capability is used with a receiver.
  • Such a circuit would have application in an ultrasonic imaging system, or other applications involving transmit-receive switching.
  • FIG. 9 is a cross section view of another embodiment of a device in accordance with the present invention.
  • the gate metallization is split into two separate gate contacts 46-1 and 46-2. This structure allows separate control of the firing of the device in the first and third quadrants of the device I-V characteristics.
  • gate 46-1 is used to trigger the device.
  • gate 46-2 is used to trigger the device. This configuration is useful in minimizing high oxide electric fields between the anode and the gate.
  • FIG. 10 is a cross section view of another embodiment of the device in accordance with the present invention.
  • a single double diffused region comprising the N+ region 33 and P region 35 is provided along with a P+ diffused region 37.
  • Contact 42 is made to regions 33 and 35, usually with the addition of P+ region 35a, a gate contact 46-1 is made over oxide 48, and an ohmic contact 78 is made to the P+ region 37.
  • This structure forms an MOS controlled silicon controlled rectifier and operates in the same mode as the device of FIG. 2 except that it is not symmetrical.
  • Contact 78 must always be the anode and contact 42 must always be the cathode.
  • the device has high input impedance on the control electrode 46-1, and good isolation is provided between the control and signal paths.
  • FIG. 11 is a cross section view of another device in accordance with the present invention which also functions as an MOS controlled silicon controlled rectifier.
  • Double diffused region 100 and 102 are formed in N- epitaxial layer 104, and anisotropic silicon etching is employed to form a V groove through the regions 100 and 102 into the epitaxial layer 104.
  • An oxide layer 106 is thermally grown or deposited in the V groove and a gate contact 108 is formed thereover.
  • An anode contact 110 is made to the P+ substrate 105, the contacts 111 and 112 to the double diffused regions are connected in parallel as the cathode, and contact 108 is the gate. In this device current flows vertically.
  • FIG. 12 and FIG. 13 are cross section views of a device similar to the device of FIG. 2 and in which an additional MOS transistor is added to achieve a turnoff capability.
  • the added MOS transistor is provided by a diffused P+ region 122 which is spaced from the P+ region 35a with the N- substrate region therebetween functioning as a channel region of an MOS transistor.
  • the gate electrode to transistor 120 is the off gate, and the gate electrode to the merged transistor 30 and 32 is the on gate.
  • FIG. 13 is a similar structure in which the device is formed in an N- epitaxial layer 124 on a P- substrate 126 with P+ isolation regions 128 diffused through the epitaxial layer 124.
  • the added transistor 120 is isolated from the merged transistor structure and comprises a double diffused MOS transistor (DMOS).
  • DMOS double diffused MOS transistor
  • FIG. 14 is the equivalent electrical schematic of the devices illustrated in FIG. 12 and FIG. 13 and is similar to the electrical schematic of FIG. 5A with the addition of the transistor 120 and off gate.
  • the MOS transistor 120 When the off gate is turned on, the MOS transistor 120 effectively shorts out the base-emitter junction of the NPN transistor 62 thus bringing the transistor out of saturation. This causes the overall device to transfer from its low impedance regenerative condition and, provided the on gate is not turned on, will shut the device completely off thereby stopping anode current.
  • This is a unique capability for a Triac type structure and is especially attractive because a high impedance MOS input is used to turn the device off.
  • an off switch may be included on the anode (A) side of the device to enable it to be switched off when the anode and the cathode are reversed.
  • the transistor 120 may be used as a variable resistor to electronically vary the current at which the device switches to a low impedance regenerative condition. It will be appreciated that in a junction isolated or dielectrically isolated structure, the device in accordance with the present invention may be fabricated along side other components as technology in fabricating the device is compatible with the fabrication of other semiconductor devices.
  • the switching device in accordance with the present invention has a number of applications including analog multiplexers with high current "boost" capability, high voltage display driving, telephone cross point switches, and in power control applications.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

An electrical circuit device made in integrated monolithic form has low level operating characteristics of a MOS device and high level operating characteristics of a Triac. The structure includes two double diffused MOS transistors which have merged drain regions. At higher voltage and current levels a lateral Triac structure is triggered by the MOS devices. Alternatively, separate terminal contacts can be made to the P and N regions comprising the MOS transistor source and channel regions with the Triac triggered conventionally by an externally applied control voltage.

Description

BACKGROUND OF THE INVENTION
This invention relates generally to semiconductor circuits and devices, and more particularly the invention relates to an integrated circuit device having current dependent properties.
The metal oxide silicon (MOS) field effect transistor and the multijunction silicon controlled rectifier and Triac are known semiconductor devices which have current switching applications. The MOS transistor generally operates at lower voltages and current levels and can be used in linear applications. One form of MOS transistor is the double diffused device in which a very short channel region is defined by diffusing a region of one conductivity type in a substrate of opposite conductivity type and then diffusing a region of opposite conductivity type in the first region. The silicon controlled rectifier (SCR) or Triac is normally employed for higher voltage and current switching applications. The MOS transistor employs a field effect channel created by the application of a gate voltage, while the SCR typically is turned on by forward biasing a PN junction which renders the device conductive. The Triac is similar to the SCR but provides full wave switching.
SUMMARY OF THE INVENTION
An object of this invention is a new and improved current switching device.
Another object of the invention is an electrical circuit device which has the characteristics of an MOS transistor and of a full wave silicon switch.
Still another object of the invention is a monolithic semiconductor device having operational characteristics which are current dependent.
A feature of the invention is a monolithic semiconductor device including two merged double diffused MOS transistors.
Briefly, a device in accordance with the invention comprises a semiconductor body having at least one major surface and a region adjacent to the surface of one conductivity. First and second spaced regions of opposite conductivity type are formed in the body region and abutting the major surface. Third and fourth regions of the one conductivity type are formed in the first and second regions, respectively, abutting the major surface and defining first and second channel regions in the first and second regions, respectively. A layer of insulation is formed on the major surface and an ohmic contact is formed on the layer of insulation and adjacent to the first and second gate regions. An ohmic contact is made to the first and third regions, and an ohmic contact is made to the second and fourth regions. An ohmic contact between the first and third regions and between the second and fourth regions may be facilitated by a separate diffusion of the same conductivity type as regions one and two adjacent to regions one and two. This diffusion is normally performed prior to diffusion of regions one and two, with a separate masking operation.
The first and third regions cooperatively function with the body region as a first double diffused MOS transistor, and the second and fourth regions cooperatively function with the body region as a second double diffused MOS transistor. The body region functions as a merged drain of the two transistors. A fifth diffused region of the same conductivity type as the body region can be formed in the body region between the first and second diffused regions.
At lower operating voltages and currents, the device functions as serially connected MOS transistors having merged drain regions, while at higher voltages and operating currents the device functions as a full wave silicon switch.
The invention and objects and features thereof will be more readily apparent from the following detailed description and appended claims when taken with the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross section view of a conventional double diffused MOS transistor.
FIG. 2 is a cross section view of one embodiment of a switching device in accordance with the present invention.
FIG. 3A and FIG. 3B are an electrical schematic and voltage-current characteristics, respectively, of the device of FIG. 2 at lower operating voltages.
FIGS. 4A and 4B are an electrical schematic and voltage-current characteristics, respectively, of the device of FIG. 2 operated at higher voltage level.
FIG. 5A .[.and.]..Iadd., .Iaddend.FIG. 5B, .Iadd.and FIG. 5C .Iaddend.are an electrical schematic and voltage-current characteristics, respectively, of the device of FIG. 2 operated at still higher voltages.
FIG. 6 is the doping profile along the silicon surface of one embodiment of the device of FIG. 2.
FIG. 7 is a cross section view of another embodiment of a switch device in accordance with the present invention.
FIGS. 8A, 8B, 8C illustrate schematically several applications of the device of FIG. 7.
FIGS. 9-13 are cross section views of other embodiments of devices in accordance with the invention.
FIG. 14 is an electrical schematic of the device shown in FIGS. 12 and 13.
DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENT
Referring now to the drawings, FIG. 1 is a cross section view of a conventional double diffused MOS transistor (DMOS) formed in a lightly doped (N-) semiconductor body 10. The device includes a first P+ diffused region 12a, a second P diffused region 12 overlapping a portion of region 12a, a third N+ diffused region 14 formed in the P region 12 with all three regions being adjacent to a major surface of the semiconductor body 10. The N+ region 14 comprises the source of the transistor, and the portion 16 of P region 12 adjacent to the major surface and between the N+ region 14 and the N- body 10 comprises the transistor channel. An N+ diffused region 18 spaced from the first two regions along with the adjacent N- body region comprises the transistor drain. A silicon oxide layer 20 is formed on the major surface of the semiconductor body 10 with a metallic ohmic contact 22 made to regions 12, 12a and 14, a metallic ohmic contact 24 made to the drain region 18, and a metallic layer for the gate electrode 26 formed on the layer of insulation 20 above the channel region 16.
The device functions as a typical MOS transistor with a short channel region provided by the double diffused structure. However, due to the PN junction between region 12 and the body 10, the DMOS device is inherently asymmetrical; that is, the source and drain terminals are not interchangeable. This asymmetry can be a problem in many circuit applications, and a device in accordance with the present invention overcomes this limitation.
Referring now to FIG. 2, one embodiment of a device in accordance with the present invention is illustrated in cross section. The device is effectively two DMOS devices shown generally at 30 and 32 integrated in a monolithic semiconductor body 36 with merged drain regions. The DMOS transistor 30 comprises a source N+ region 33, a channel region 34 formed in P region 35 and a drain comprising the N- semiconductor body 36 and the N+ diffused region 37. DMOS transistor 32 comprises an N+ source 38, a P channel region 39 formed in P region 40, and a drain comprising the N- body 36 and the N+ diffused region 37. Regions 35a and 40a again are P+ diffused regions designed to facilitate ohmic contact to the P channel regions 35 and 40. One input-output (I/O) contact 42 is made to regions 33, 35 and 35a, a second I/O contact 44 is made to regions 38, 40 and 40a, and a gate electrode 46 is formed on the silicon oxide layer 48 above the channel regions 34, 39.
Due to the symmetrical construction of the device as shown in FIG. 2, the device has symmetry of operation, i.e. the two I/O contacts are interchangeable. Importantly, the operational characteristics of this device change with the operating voltage and current levels.
FIG. 3A is an electrical schematic of the device in FIG. 2 operated at low voltage and current levels (e.g. less than one volt across the device, gate voltage of a few volts above the threshold voltage), and FIG. 3B is the current-voltage operating characteristics of the device of FIG. 3A. In FIG. 3A the two DMOS transistors 30 and 32 are shown serially connected with the I/ O terminals 42, 44 connected to the source regions of transistors 30 and 32, respectively, and gate terminal 46 controlling the gates of both transistors. Diode 52 formed by P region 35 and the N- body 36 is connected in parallel with transistor 30, and diode 50 formed by P region 40 and the N- body 36 is connected in parallel with transistor 32. Thus, since the two diodes are provided in series opposition, the device in accordance with the present invention is symmetrical at lower voltage and current operation. FIG. 3B is a plot of current vs. voltage for low-level operation wherein the device function in accordance with the circuit illustrated in FIG. 3A.
For applied voltages greater than approximately 1.5 volts (gate voltage of a few volts above the threshold voltage), holes are injected into semiconductor body 36 by the plus voltage on P regions 40 and 40a, with P regions 40 and 40a and 35 and 35a functioning with the N- semiconductor body 36 as a PNP transistor 60 connected as shown in FIG. 4A. Referring to the plot of voltage vs. current in FIG. 4B, the transconductance or gain of the device shows a sharp increase. However, the device remains symmetrical. The increase in transconductance or device gain can be attributed to the injected holes from regions 40 and 40a which pass through body 36 and are collected at regions 35 and 35a. These collected holes contribute to the total device current (which is measured externally) and thus increase the transconductance or device gain. Some of the injected holes recombine with majority carriers in the N- region while the remaining injected holes are collected at regions 35 and 35a. Thus, applied voltages greater than approximately 1.5 volts cause the lateral PNP transistor to turn on. The current contributed by this device explains the increase in overall device gain as demonstrated by the plot in FIG. 4B. In this mode of operation two parallel conduction paths are provided in the device, electron flow through the surface DMOS devices and hole current through the lateral PNP transistor. The overall device current is the sum of the DMOS electron current and the injected hole current.
By increasing current flow through the device by increasing gate voltage, for example, an applied voltage of +2 volts on one I/O terminal and a +10 volt gate potential, the device assumes an electrical and equivalent electrical schematic as demonstrated in FIGS. 5A and 5B, with the other I/O terminal grounded. In this mode of operation the device assumes the characteristics of a Triac with switching action to a low resistance device, similar to that observed in PNPN four layer structures. The structure shown in FIG. 2 can be viewed as a lateral NPNPN structure, or a symmetrical PNPN arrangement, between the two I/O terminals. As illustrated in FIG. 5A, an NPN transistor 62 formed by regions 33, 35 and 36 of the structure in FIG. 2, is added to the circuit of FIG. .[.4B.]. .Iadd.4A .Iaddend.with transistor 62 shunting DMOS transistor 30. Both electrons and holes continue to contribute to the overall device current, however, the holes collected by the P region 35 (FIG. 2) flow through a relatively high resistance before reaching the I/O contact 42. This resistance is denoted 64 in the schematic of FIG. 5A, and is physically analogous to the base resistance in a bipolar transistor and is an inherent part of the DMOS structure. The resistance is a distributed resistor and holes are collected all along its length. The voltage drop along the resistor will tend to forward bias the PN+ junction (region 35, 33) which is the base-emitter junction of the NPN transistor whose collector is the N- body 36. Once the voltage differential turns the NPN transistor on (at approximately 0.7 volts) a regenerative switching causes the four layer structure comprising the two bipolar transistors to switch to a low resistance state, which is illustrated in FIG. .[.5B.]. .Iadd.5C. . Iaddend.Transistors 60 and 62 are equivalent to the arrangement of PNP and NPN devices used in conventional Triacs and SCRs.
It should be noted that the Triac or SCR is switched by applying a trigger voltage from an external source. While the device as illustrated in FIG. 2 is triggered to a low resistance state when the current through the device is increased by increasing the gate voltage, the device can be made to operate as a conventional SCR by forward biasing a junction. If separate ohmic contacts are formed to regions 35a and 33, externally forward biasing the P+N+ junction between regions 35a and 33 will switch the device to its low resistance state. However, the device illustrated in FIG. 2 is switched to a low resistance mode by an MOS device in parallel with the Triac and not by forward biasing the junction externally, as is found with the conventional Triacs and SCRs. At low current levels before the Triac fires, the MOS characteristics of the structure dominate. After firing the Triac, the device becomes a low resistance device.
FIG. 6 illustrates the surface doping profile for one switch device in accordance with the present invention. Absolute surface doping concentration is illustrated along the ordinate and distance across the device is illustrated along the abscissa. Relating the doping concentration to the device illustrated in cross section in FIG. 2, the N+ regions 33, 37 and 38 have a dopant concentration on the order of 1020 impurities per cubic centimeter. The P regions which comprise the channel regions of the two DMOS transistors 34, 39 have a peak dopant concentration on the order of 5×1016 impurities per cubic centimeter. The dopant concentration of the N- semiconductor body is on the order of 1015 impurities per cubic centimeter.
In fabricating the device, P+ diffusions are first formed to facilitate ohmic contact to the DMOS transistor channel regions. Then sequential diffusions of boron (P type) and phosphorus or arsenic (N type) are made employing conventional diffusion techniques to form the P and N+ regions. Ion implantation may also be advantageously used to introduce the boron (P type) impurity for the channel region of the devices. The gate oxidation is then formed over the channel regions, contact holes are made for the I/O contacts, metal is formed over the surface of the device and the metal pattern is defined by conventional photoresist masking and etching techniques.
The maximum doping in the P region at the surface under the gate along with the gate oxide thickness and the oxide charge density determine the DMOS threshold voltage. The channel width largely determines the DMOS transconductance and on resistance. The channel width also affects the Triac trigger current because the Triac is triggered by a specific current density flowing through the device. The DMOS properties are largely independent of the channel length.
The channel doping profile determines directly the DMOS threshold voltage. In addition, the current density at which switching to the low resistance mode of operation occurs is affected by this profile.
The doping level in the N- semiconductor body affects the device breakdown voltage, the DMOS on resistance and the lateral PNP transport efficiency.
The N+ drain region in the middle of the device is important in order to increase the breakdown voltage. If this diffused region is not included a parasitic P channel MOS transistor across the surface will reduce the breakdown voltage to the field oxide threshold voltage which is typically 20 to 40 volts. In addition, this N+ region increases the lateral PNP transport efficiency. The lateral dimension of the N+ region should be minimized as it degrades the PNP transport efficiency.
Referring now to FIG. 7, several modifications to the device shown in cross section in FIG. 2 are made. The same numerals are given to like elements. The semiconductor body region 36 in this embodiment comprises an epitaxial layer formed on a P- substrate 70. The structure may comprise a plurality of switching devices with each device isolated by means of diffused P+ regions 72 and 74 which extend through the epitaxial layer 36 to the underlying substrate 70 and surround the device. However, it is noted that a P+ substrate collects injected holes thus delaying the turn-on of the Triac lateral structure. Experimental results indicate that depending upon device geometry 10% to 50% of the injected holes are collected by the substrate before the Triac fires. While this does affect the efficiency of the device at higher voltage and current levels, the efficiency of the device is not affected at low voltage and current levels when all of the device current is carried by the MOS transistors. By adding an N+ buried layer between the N- epitaxial layer and the P- substrate, a reduction in injected holes captured by the substrate would be effected. Such buried layers are commonly employed in commercial integrated circuits and are readily acapted in standard production techniques. Additionally, dielectric isolation techniques can be employed instead of diffused isolation as shown in FIG. 7. By employing dielectric isolation the P- substrate of FIG. 7 can be replaced with an insulator, and consequently injected holes are not collected by the substrate. Alternatively, the P+ diffused regions, 72, 74 can be replaced by a dielectric such as silicon oxide.
The N+ region 37 spaced from the two double diffused regions is not necessary for low voltage. Triac operation and it can be eliminated if the device is not operated at high voltages. By eliminating this N+ region, the base width of the lateral PNP transistor can be reduced, resulting in lower triggering currents for the Triac and lower on resistance for the DMOS device. However, as indicated above the elimination of the N+ regoin creates a parasitic PMOS transistor between the two P diffused regions thus limiting the device breakdown voltage.
The separate ohmic contact made to the N+ region 37 as illustrated in FIG. 7 allows more versatility in operation of the device. The device can still be operated as a switching device as above described and as illustrated schematically in FIG. 8A. The N+ connection 78 can be left floating or can be connected to the +V potential applied to terminal .[.42.]. .Iadd.44.Iaddend.. By connecting the terminal to the +V potential, the DMOS characteristics will dominate up to a higher voltage and current level before the device becomes a low resistance switch.
Alternatively, as shown schematically in FIG. 8B the device can be used as a standard DMOS transistor over its full operating range by connecting terminals 42 and 44 together as the source, and the N+ contact 78 becomes the drain.
In FIG. 8C, the device is used as a high level analog switch wherein a transducer 80 is driven at a high voltage with the transducer also used as part of a receiver. In this application the Triac capability is used with the transmitter, and the single DMOS capability is used with a receiver. Such a circuit would have application in an ultrasonic imaging system, or other applications involving transmit-receive switching.
FIG. 9 is a cross section view of another embodiment of a device in accordance with the present invention. In this embodiment the gate metallization is split into two separate gate contacts 46-1 and 46-2. This structure allows separate control of the firing of the device in the first and third quadrants of the device I-V characteristics. When the terminal 44 is positive (the anode) gate 46-1 is used to trigger the device. When the terminal 42 is positive (the anode), gate 46-2 is used to trigger the device. This configuration is useful in minimizing high oxide electric fields between the anode and the gate.
FIG. 10 is a cross section view of another embodiment of the device in accordance with the present invention. In this embodiment a single double diffused region comprising the N+ region 33 and P region 35 is provided along with a P+ diffused region 37. Contact 42 is made to regions 33 and 35, usually with the addition of P+ region 35a, a gate contact 46-1 is made over oxide 48, and an ohmic contact 78 is made to the P+ region 37. This structure forms an MOS controlled silicon controlled rectifier and operates in the same mode as the device of FIG. 2 except that it is not symmetrical. Contact 78 must always be the anode and contact 42 must always be the cathode. The device has high input impedance on the control electrode 46-1, and good isolation is provided between the control and signal paths.
FIG. 11 is a cross section view of another device in accordance with the present invention which also functions as an MOS controlled silicon controlled rectifier. Double diffused region 100 and 102 are formed in N- epitaxial layer 104, and anisotropic silicon etching is employed to form a V groove through the regions 100 and 102 into the epitaxial layer 104. An oxide layer 106 is thermally grown or deposited in the V groove and a gate contact 108 is formed thereover. An anode contact 110 is made to the P+ substrate 105, the contacts 111 and 112 to the double diffused regions are connected in parallel as the cathode, and contact 108 is the gate. In this device current flows vertically.
FIG. 12 and FIG. 13 are cross section views of a device similar to the device of FIG. 2 and in which an additional MOS transistor is added to achieve a turnoff capability. In FIG. 12 the added MOS transistor is provided by a diffused P+ region 122 which is spaced from the P+ region 35a with the N- substrate region therebetween functioning as a channel region of an MOS transistor. The gate electrode to transistor 120 is the off gate, and the gate electrode to the merged transistor 30 and 32 is the on gate.
FIG. 13 is a similar structure in which the device is formed in an N- epitaxial layer 124 on a P- substrate 126 with P+ isolation regions 128 diffused through the epitaxial layer 124. In this embodiment the added transistor 120 is isolated from the merged transistor structure and comprises a double diffused MOS transistor (DMOS).
FIG. 14 is the equivalent electrical schematic of the devices illustrated in FIG. 12 and FIG. 13 and is similar to the electrical schematic of FIG. 5A with the addition of the transistor 120 and off gate. When the off gate is turned on, the MOS transistor 120 effectively shorts out the base-emitter junction of the NPN transistor 62 thus bringing the transistor out of saturation. This causes the overall device to transfer from its low impedance regenerative condition and, provided the on gate is not turned on, will shut the device completely off thereby stopping anode current. This is a unique capability for a Triac type structure and is especially attractive because a high impedance MOS input is used to turn the device off. In addition, an off switch may be included on the anode (A) side of the device to enable it to be switched off when the anode and the cathode are reversed. This makes the overall device symmetric. Additionally, the transistor 120 may be used as a variable resistor to electronically vary the current at which the device switches to a low impedance regenerative condition. It will be appreciated that in a junction isolated or dielectrically isolated structure, the device in accordance with the present invention may be fabricated along side other components as technology in fabricating the device is compatible with the fabrication of other semiconductor devices.
The switching device in accordance with the present invention has a number of applications including analog multiplexers with high current "boost" capability, high voltage display driving, telephone cross point switches, and in power control applications.
Thus, while the invention has been described with reference to specific embodiments and applications, the description is illustrative of the invention and is not to be construed as limiting the invention. It will be appreciated that various manufacturing techniques are known for fabricating the devices and equivalent structures can be fabricated. For example, while the ohmic contacts are described as metallic, other contacts such as doped polysilicon can be employed. Thus, various applications, changes, and modifications may occur to those skilled in the art without departing from the true spirit and scope of the invention as defined by the appended claims.

Claims (20)

What is claimed is:
1. A monolithic semiconductor .Iadd.SCR .Iaddend.device comprising:
a semiconductor .[.body.]. .Iadd.substrate of one conductivity type and an epitaxial layer of opposite conductivity type, said epitaxial layer .Iaddend.having at least one major surface, and
.[.a body region adjacent to said surface of one conductivity type,.]. first and second spaced regions of .[.opposite.]. .Iadd.said one .Iaddend.conductivity type formed in said .[.body region.]. .Iadd.epitaxial layer .Iaddend.and abutting said major surface, third and fourth regions of said .[.one conductivity.]. .Iadd.opposite conductivity .Iaddend.type formed in said first and second regions, respectively, abutting said major surface and defining first and second channel regions in said first and second regions, respectively,
a layer of insulation on said major surface,
a gate electrode formed on said layer of insulation and above said first and second channel regions, an ohmic contact to said first and third regions, and an ohmic contact to said second and fourth regions.Iadd., and .Iaddend.
.Iadd.an ohmic contact to said semiconductor substrate.Iaddend.. .[.2. A monolithic semiconductor device as defined by claim 1 and further including a fifth region of said one conductivity type formed in said semiconductor body between and spaced from said first and second
regions..]. 3. A monolithic semiconductor device as defined by claim .[.2.]. .Iadd.1 .Iaddend.wherein said one conductivity type is .[.N.]. .Iadd.P .Iaddend.type and said opposite conductivity type is .[.P.]. .Iadd.N .Iaddend.type. .[.4. A monolithic semiconductor device as defined by claim 2 and including an ohmic contact to said fifth region..]. .[.5. A monolithic semiconductor device as defined by claim 1 wherein said body
region of said semiconductor body comprises an epitaxial layer..]. 6. A monolithic semiconductor device as defined by claim .[.5.]. .Iadd.1 .Iaddend.wherein said semiconductor device is electrically isolated by an isolation region through said epitaxial layer and surrounding said device.
. A monolithic semiconductor device as defined by claim 6 wherein said
isolation region comprises a diffused region. 8. A monolithic semiconductor device as defined by claim 6 wherein said isolation region
comprises a dielectric material. 9. A monolithic semiconductor device as defined by claim 6 .[.wherein said semiconductor body includes.]. .Iadd.and including a .Iaddend.plurality of like semiconductor devices which are spaced and isolated from said one device by said isolation
region. 10. A monolithic semiconductor device as defined by claim 1 wherein .[.said semiconductor body comprises a semiconductor substrate of said opposite conductivity type, said body region comprises an epitaxial layer of said one conductivity type formed on said substrate,.]. said first and second regions are spaced apart by a V-groove formed in said major surface and further including a layer of insulation over the surface of said V-groove and .[.a.]. .Iadd.said .Iaddend.gate electrode .Iadd.is .Iaddend.formed over said layer of insulation and spaced from said surface of said V-groove. .[.11. A monolithic semiconductor device as defined by claim 1 and further including a fifth region of said opposite conductivity type abutting said major surface and spaced from said first region, an insulating layer overlying said major surface between said first and fifth
regions, and a gate electrode formed on said insulative layer..]. 12. An electrical .Iadd.triac .Iaddend.circuit device comprising:
a first double diffused field effect transistor having source, gate, and drain regions,
a second double diffused field effect transistor having source, gate, and drain regions,
means ohmically connecting said drain regions, contact means for said gate regions,
.[.an.]. .Iadd.a first anode .Iaddend.ohmic contact to said source region of said first field effect transistor, and
.[.an.]. .Iadd.a second anode .Iaddend.ohmic contact to said source region of said second field effect transistor.Iadd., .Iaddend.
.Iadd.said first and second field effect transistors being formed in a semiconductor body and said means ohmically connecting said drain regions comprises a region of said semiconductor body. .Iaddend. .[.13. An electrical circuit device as defined by claim 12 wherein said first and second field effect transistors are formed in a semiconductor body and said means ohmically connecting said drain regions comprises a region of
said semiconductor body..]. 14. An electrical circuit device as defined by claim 12 wherein said source and drain regions are N type, and said
channel regions are P type. 15. An electrical circuit device as defined by claim 12 wherein said semiconductor body includes an epitaxial layer and said first and second field effect transistors are formed in said
epitaxial layer. 16. An electrical circuit device as defined by claim 15 and including an isolation region extending through said epitaxial layer
and surrounding said first and second field effect transistors. 17. A monolithic semiconductor device as defined by claim 16 wherein said
isolation region comprises a diffused region. 18. A monolithic semiconductor device as defined by claim 16 wherein said isolation region
comprises a dielectric material. 19. A monolithic body having a plurality of isolated semiconductor regions of one conductivity type abutting a major surface of said body, each region including an electrical .Iadd.triac .Iaddend.device comprising
first and second spaced regions of opposite conductivity type,
third and fourth regions of said one conductivity type formed in said first and second regions, respectively, and defining first and second channel regions in said first and second regions, respectively,
a layer of insulation on the surface of said semiconductor region,
a gate electrode formed on said layer of insulation and adjacent to said first and second channel regions,
.[.an.]. .Iadd.a first anode .Iaddend.ohmic contact to said first and third regions, and
.[.an.]. .Iadd.a second anode .Iaddend.ohmic contact to said second and
fourth regions. 20. A monolithic body as defined by claim 19 wherein said insulation layer comprises silicon oxide and said monolithic body
comprises a silicon substrate. 21. A monolithic body as defined by claim 20 wherein said monolithic body further includes an epitaxial layer and
said electrical device is formed in said epitaxial layer. 22. A monolithic body as defined by claim 21 wherein said isolation is provided by diffused regions through said epitaxial layer of said opposite conductivity type.
. A monolithic body as defined by claim 21 wherein said isolation is
formed by dielectric material extending through said epitaxial layer. 24. A monolithic body as defined by claim 23 wherein said dielectric
material is silicon oxide. 25. A monolithic semiconductor device comprising:
a semiconductor substrate of one conductivity type,
an epitaxial layer of opposite conductivity type, said epitaxial layer having a major surface, isolation means extending through said epitaxial layer and defined at least two isolated regions in said epitaxial layer,
one of said isolated regions including
a first double diffused field effect transistor having source, gate, and drain regions,
a second double diffused field effect transistor having source, gate, and drain regions,
means ohmically connecting said drain regions,
contact means for said gate regions,
an ohmic contact to said source region of said first field effect transistor, and
an ohmic contact to said source region of said second field effect transistor,
another of said isolated regions including
a third field effect transistor having source, gate, and drain regions, and
means electrically connecting said source region of said third transistor and said source region of said second transistor, said source region of said first transistor functions as an anode, said connected source regions of said second and third transistor function as a cathode, said gate regions of said first and second transistors function as an on gate, and said gate of said third field effect transistor functions as an off gate.
US06539111 1978-09-18 1983-12-05 Monolithic semiconductor switching device Expired - Lifetime USRE33209F1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US05/943,200 US4199774A (en) 1978-09-18 1978-09-18 Monolithic semiconductor switching device
US06539111 USRE33209F1 (en) 1978-09-18 1983-12-05 Monolithic semiconductor switching device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/943,200 US4199774A (en) 1978-09-18 1978-09-18 Monolithic semiconductor switching device
US06539111 USRE33209F1 (en) 1978-09-18 1983-12-05 Monolithic semiconductor switching device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US05/943,200 Reissue US4199774A (en) 1978-09-18 1978-09-18 Monolithic semiconductor switching device

Publications (2)

Publication Number Publication Date
USRE33209E true USRE33209E (en) 1990-05-01
USRE33209F1 USRE33209F1 (en) 1996-01-16

Family

ID=27066020

Family Applications (2)

Application Number Title Priority Date Filing Date
US05/943,200 Ceased US4199774A (en) 1978-09-18 1978-09-18 Monolithic semiconductor switching device
US06539111 Expired - Lifetime USRE33209F1 (en) 1978-09-18 1983-12-05 Monolithic semiconductor switching device

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US05/943,200 Ceased US4199774A (en) 1978-09-18 1978-09-18 Monolithic semiconductor switching device

Country Status (1)

Country Link
US (2) US4199774A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0520831A2 (en) 1991-06-28 1992-12-30 Texas Instruments Incorporated Gated thyristor and process for its simultaneous fabrication with an integrated circuit
US5336637A (en) * 1991-09-19 1994-08-09 International Business Machines Corporation Silicide interconnection with Schottky barrier diode isolation
US5598018A (en) * 1978-10-13 1997-01-28 International Rectifier Corporation High power MOSFET with low on-resistance and high breakdown voltage
US5686857A (en) * 1996-02-06 1997-11-11 Motorola, Inc. Zero-crossing triac and method
US5701023A (en) * 1994-08-03 1997-12-23 National Semiconductor Corporation Insulated gate semiconductor device typically having subsurface-peaked portion of body region for improved ruggedness
US5796126A (en) * 1995-06-14 1998-08-18 Samsung Electronics Co., Ltd. Hybrid schottky injection field effect transistor
US20050227461A1 (en) * 2000-05-05 2005-10-13 International Rectifier Corporation Semiconductor device having increased switching speed
US20140021522A1 (en) * 2008-12-26 2014-01-23 Megica Corporation Chip packages with power management integrated circuits and related techniques
US10600907B2 (en) * 2017-05-31 2020-03-24 Magnachip Semiconductor, Ltd. High voltage semiconductor device

Families Citing this family (113)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5191396B1 (en) * 1978-10-13 1995-12-26 Int Rectifier Corp High power mosfet with low on-resistance and high breakdown voltage
US4329705A (en) * 1979-05-21 1982-05-11 Exxon Research & Engineering Co. VMOS/Bipolar power switching device
DE2945366A1 (en) * 1979-11-09 1981-05-14 Siemens AG, 1000 Berlin und 8000 München THYRISTOR WITH CONTROLLABLE EMITTER SHORT CIRCUITS
DE2945380A1 (en) * 1979-11-09 1981-05-21 Siemens AG, 1000 Berlin und 8000 München TRIAC WITH A MULTILAYER SEMICONDUCTOR BODY
DE2945347A1 (en) * 1979-11-09 1981-05-21 Siemens AG, 1000 Berlin und 8000 München THYRISTOR WITH AUXILIARY ELECTRODE AND METHOD FOR ITS OPERATION
US4947232A (en) * 1980-03-22 1990-08-07 Sharp Kabushiki Kaisha High voltage MOS transistor
US4364073A (en) * 1980-03-25 1982-12-14 Rca Corporation Power MOSFET with an anode region
US4345265A (en) * 1980-04-14 1982-08-17 Supertex, Inc. MOS Power transistor with improved high-voltage capability
US4344081A (en) * 1980-04-14 1982-08-10 Supertex, Inc. Combined DMOS and a vertical bipolar transistor device and fabrication method therefor
DE3019883A1 (en) * 1980-05-23 1981-12-03 Siemens AG, 1000 Berlin und 8000 München DIRECTIONAL THYRISTOR
JPS56169368A (en) * 1980-05-30 1981-12-26 Sharp Corp High withstand voltage mos field effect semiconductor device
JPS56169369A (en) * 1980-05-30 1981-12-26 Sharp Corp High withstand voltage mos field effect semiconductor device
US4654680A (en) * 1980-09-24 1987-03-31 Semiconductor Energy Laboratory Co., Ltd. Sidewall gate IGFET
DD154049A1 (en) * 1980-10-30 1982-02-17 Siegfried Wagner CONTROLLABLE SEMICONDUCTOR ELEMENT
US4414560A (en) * 1980-11-17 1983-11-08 International Rectifier Corporation Floating guard region and process of manufacture for semiconductor reverse conducting switching device using spaced MOS transistors having a common drain region
US4441117A (en) * 1981-07-27 1984-04-03 Intersil, Inc. Monolithically merged field effect transistor and bipolar junction transistor
DE3200660A1 (en) * 1982-01-12 1983-07-21 Siemens AG, 1000 Berlin und 8000 München MIS FIELD EFFECT TRANSISTOR WITH CARRIER INJECTION
JPH0666421B2 (en) * 1982-02-09 1994-08-24 ウエスタ−ン エレクトリツク カムパニ−,インコ−ポレ−テツド Switching device
US4742380A (en) * 1982-02-09 1988-05-03 American Telephone And Telegraph Company, At&T Bell Laboratories Switch utilizing solid-state relay
US5014102A (en) * 1982-04-01 1991-05-07 General Electric Company MOSFET-gated bipolar transistors and thyristors with both turn-on and turn-off capability having single-polarity gate input signal
US4656493A (en) * 1982-05-10 1987-04-07 General Electric Company Bidirectional, high-speed power MOSFET devices with deep level recombination centers in base region
JPH0612823B2 (en) * 1982-05-10 1994-02-16 ゼネラル・エレクトリック・カンパニイ Bidirectional power high speed MOSFET device
US4574208A (en) * 1982-06-21 1986-03-04 Eaton Corporation Raised split gate EFET and circuitry
US4571513A (en) * 1982-06-21 1986-02-18 Eaton Corporation Lateral bidirectional dual notch shielded FET
US4612465A (en) * 1982-06-21 1986-09-16 Eaton Corporation Lateral bidirectional notch FET with gates at non-common potentials
US4574209A (en) * 1982-06-21 1986-03-04 Eaton Corporation Split gate EFET and circuitry
US4574207A (en) * 1982-06-21 1986-03-04 Eaton Corporation Lateral bidirectional dual notch FET with non-planar main electrodes
US4571512A (en) * 1982-06-21 1986-02-18 Eaton Corporation Lateral bidirectional shielded notch FET
US4571606A (en) * 1982-06-21 1986-02-18 Eaton Corporation High density, high voltage power FET
US4546367A (en) * 1982-06-21 1985-10-08 Eaton Corporation Lateral bidirectional notch FET with extended gate insulator
DE3224618A1 (en) * 1982-07-01 1984-01-05 Siemens AG, 1000 Berlin und 8000 München IGFET WITH CARRIAGE INJECTION
US4553151A (en) * 1982-09-23 1985-11-12 Eaton Corporation Bidirectional power FET with field shaping
US4542396A (en) * 1982-09-23 1985-09-17 Eaton Corporation Trapped charge bidirectional power FET
US4541001A (en) * 1982-09-23 1985-09-10 Eaton Corporation Bidirectional power FET with substrate-referenced shield
US4577208A (en) * 1982-09-23 1986-03-18 Eaton Corporation Bidirectional power FET with integral avalanche protection
EP0106147A1 (en) * 1982-10-04 1984-04-25 General Electric Company Thyristor with turn-off capability
EP0273030A3 (en) * 1982-12-13 1988-09-21 General Electric Company Lateral insulated-gate rectifier structures
DE3301648A1 (en) * 1983-01-19 1984-07-19 Siemens AG, 1000 Berlin und 8000 München MISFET WITH INPUT AMPLIFIER
BE897139A (en) * 1983-06-27 1983-12-27 Bell Telephone Mfg Cy Nov PROCESS FOR CREATING A SEMICONDUCTOR DEVICE AND OBTAINED THEREFROM
EP0144654A3 (en) * 1983-11-03 1987-10-07 General Electric Company Semiconductor device structure including a dielectrically-isolated insulated-gate transistor
US4644637A (en) * 1983-12-30 1987-02-24 General Electric Company Method of making an insulated-gate semiconductor device with improved shorting region
US4783694A (en) * 1984-03-16 1988-11-08 Motorola Inc. Integrated bipolar-MOS semiconductor device with common collector and drain
BR8507182A (en) * 1984-05-02 1987-04-22 Int Standard Electric Corp SEMICONDUCTOR DEVICE AND ARRANGEMENT
US4622568A (en) * 1984-05-09 1986-11-11 Eaton Corporation Planar field-shaped bidirectional power FET
US4558243A (en) * 1984-05-09 1985-12-10 Eaton Corporation Bidirectional power FET with shorting-channel off state
EP0207177A1 (en) * 1985-06-25 1987-01-07 Eaton Corporation Bidirectional power fet with shorting-channel off state
EP0166390B1 (en) * 1984-06-22 1991-08-28 Hitachi, Ltd. Semiconductor switch circuit
US4593458A (en) * 1984-11-02 1986-06-10 General Electric Company Fabrication of integrated circuit with complementary, dielectrically-isolated, high voltage semiconductor devices
EP0185837A1 (en) * 1984-11-16 1986-07-02 Eaton Corporation Efet, bidirectional lateral power fet
US4694313A (en) * 1985-02-19 1987-09-15 Harris Corporation Conductivity modulated semiconductor structure
GB2173037A (en) * 1985-03-29 1986-10-01 Philips Electronic Associated Semiconductor devices employing conductivity modulation
EP0205635A1 (en) * 1985-06-25 1986-12-30 Eaton Corporation Bidirectional power fet with bipolar on-state
US4989058A (en) * 1985-11-27 1991-01-29 North American Philips Corp. Fast switching lateral insulated gate transistors
US4963951A (en) * 1985-11-29 1990-10-16 General Electric Company Lateral insulated gate bipolar transistors with improved latch-up immunity
US4860072A (en) * 1986-03-05 1989-08-22 Ixys Corporation Monolithic semiconductor device and method of manufacturing same
US5262336A (en) * 1986-03-21 1993-11-16 Advanced Power Technology, Inc. IGBT process to produce platinum lifetime control
US4786958A (en) * 1986-11-17 1988-11-22 General Motors Corporation Lateral dual gate thyristor and method of fabricating same
US4717679A (en) * 1986-11-26 1988-01-05 General Electric Company Minimal mask process for fabricating a lateral insulated gate semiconductor device
JPH0821713B2 (en) * 1987-02-26 1996-03-04 株式会社東芝 Conduction modulation type MOSFET
US4888627A (en) * 1987-05-19 1989-12-19 General Electric Company Monolithically integrated lateral insulated gate semiconductor device
US4857983A (en) * 1987-05-19 1989-08-15 General Electric Company Monolithically integrated semiconductor device having bidirectional conducting capability and method of fabrication
US4847671A (en) * 1987-05-19 1989-07-11 General Electric Company Monolithically integrated insulated gate semiconductor device
US4857977A (en) * 1987-08-24 1989-08-15 General Electric Comapny Lateral metal-oxide-semiconductor controlled triacs
US4939566A (en) * 1987-10-30 1990-07-03 North American Philips Corporation Semiconductor switch with parallel DMOS and IGT
US4926074A (en) * 1987-10-30 1990-05-15 North American Philips Corporation Semiconductor switch with parallel lateral double diffused MOS transistor and lateral insulated gate transistor
US4947226A (en) * 1987-12-08 1990-08-07 Hoenywell, Inc. Bilateral switching device
CA1295053C (en) * 1987-12-08 1992-01-28 Jack S.T. Huang Bilateral switching device
US4861731A (en) * 1988-02-02 1989-08-29 General Motors Corporation Method of fabricating a lateral dual gate thyristor
EP0394859A1 (en) * 1989-04-28 1990-10-31 Asea Brown Boveri Ag Bidirectional turn-off semiconductor device
US5381025A (en) * 1989-08-17 1995-01-10 Ixys Corporation Insulated gate thyristor with gate turn on and turn off
US5278076A (en) * 1990-02-28 1994-01-11 At&T Bell Laboratories Method of marking a lateral mos controlled thyristor
US5016076A (en) * 1990-02-28 1991-05-14 At&T Bell Laboratories Lateral MOS controlled thyristor
DE59010855D1 (en) * 1990-06-05 1998-12-24 Siemens Ag Manufacturing process for a power MISFET
US5250450A (en) * 1991-04-08 1993-10-05 Micron Technology, Inc. Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance
US5122848A (en) * 1991-04-08 1992-06-16 Micron Technology, Inc. Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance
US5227653A (en) * 1991-08-07 1993-07-13 North American Philips Corp. Lateral trench-gate bipolar transistors
TW260816B (en) * 1991-12-16 1995-10-21 Philips Nv
US5323044A (en) * 1992-10-02 1994-06-21 Power Integrations, Inc. Bi-directional MOSFET switch
US5600160A (en) * 1993-04-14 1997-02-04 Hvistendahl; Douglas D. Multichannel field effect device
EP0689238B1 (en) * 1994-06-23 2002-02-20 STMicroelectronics S.r.l. MOS-technology power device manufacturing process
US5817546A (en) * 1994-06-23 1998-10-06 Stmicroelectronics S.R.L. Process of making a MOS-technology power device
DE69428894T2 (en) * 1994-08-02 2002-04-25 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno, Catania Bipolar transistor with isolated control electrode
JP3183055B2 (en) * 1994-08-08 2001-07-03 富士電機株式会社 Semiconductor bidirectional switch and driving method thereof
US6388272B1 (en) 1996-03-07 2002-05-14 Caldus Semiconductor, Inc. W/WC/TAC ohmic and rectifying contacts on SiC
US5929523A (en) * 1996-03-07 1999-07-27 3C Semiconductor Corporation Os rectifying Schottky and ohmic junction and W/WC/TiC ohmic contacts on SiC
US6023078A (en) * 1998-04-28 2000-02-08 North Carolina State University Bidirectional silicon carbide power devices having voltage supporting regions therein for providing improved blocking voltage capability
JP3857462B2 (en) 1999-03-19 2006-12-13 株式会社東芝 AC switch circuit
US6323090B1 (en) 1999-06-09 2001-11-27 Ixys Corporation Semiconductor device with trenched substrate and method
EP1137158A1 (en) * 2000-03-21 2001-09-26 Kabushiki Kaisha Toshiba AC switch device used for switching AC circuit and AC switch circuit having the AC switch device
US6342403B1 (en) * 2000-12-14 2002-01-29 Xerox Corporation Electrical detection of V-groove width
US6710405B2 (en) 2001-01-17 2004-03-23 Ixys Corporation Non-uniform power semiconductor device
US6800902B2 (en) * 2001-02-16 2004-10-05 Canon Kabushiki Kaisha Semiconductor device, method of manufacturing the same and liquid jet apparatus
US6492687B2 (en) * 2001-05-07 2002-12-10 Semiconductor Components Industries Llc Merged semiconductor device and method
JP4537646B2 (en) 2002-06-14 2010-09-01 株式会社東芝 Semiconductor device
WO2004070791A2 (en) * 2003-02-04 2004-08-19 Great Wall Semiconductor Bi-directional power switch
WO2004106891A2 (en) 2003-05-22 2004-12-09 University Of Hawaii Ultrasensitive biochemical sensor
WO2005059958A2 (en) 2003-12-12 2005-06-30 Great Wall Semiconductor Corporation Monolithic power semiconductor structures
US20050205891A1 (en) * 2004-03-18 2005-09-22 Holm-Kennedy James W Distributed channel bipolar devices and architectures
US8890248B2 (en) * 2004-08-26 2014-11-18 Texas Instruments Incorporation Bi-directional ESD protection circuit
JP4572795B2 (en) * 2005-02-10 2010-11-04 サンケン電気株式会社 Insulated gate bipolar transistor
JP4179292B2 (en) * 2005-02-21 2008-11-12 サンケン電気株式会社 Semiconductor device
EP1717849A1 (en) * 2005-04-27 2006-11-02 STMicroelectronics S.r.l. Process for manufacturing a MOS device with intercell ion implant
US7982528B2 (en) * 2006-05-18 2011-07-19 Stmicroelectronics, S.R.L. Three-terminal power device with high switching speed and manufacturing process
US7800143B2 (en) * 2006-07-13 2010-09-21 Globalfoundries Inc. Dynamic random access memory with an amplified capacitor
US7679955B2 (en) * 2006-08-02 2010-03-16 Advanced Micro Devices, Inc. Semiconductor switching device
WO2008022149A2 (en) 2006-08-14 2008-02-21 Ixys Corporation Video and content controlled backlight
ITTO20070163A1 (en) * 2007-03-02 2008-09-03 St Microelectronics Srl PROCESS OF MANUFACTURING A MISFET VERTICAL CONDUCTIVE DEVICE WITH DIELECTRIC STRUCTURE OF DOOR OF DIFFERENTIAL THICKNESS AND MISFET DEVICE WITH A VERTICAL CONDUCTION MADE THESE
US20090273006A1 (en) * 2008-04-30 2009-11-05 Wen-Yi Chen Bidirectional silicon-controlled rectifier
FR2934710B1 (en) * 2008-08-04 2010-09-10 St Microelectronics Sa CIRCUIT FOR PROTECTING AN INTEGRATED CIRCUIT AGAINST ELECTROSTATIC DISCHARGES IN CMOS TECHNOLOGY.
US20130043538A1 (en) * 2011-08-16 2013-02-21 Chao-Cheng Lu Switch
JP6142358B2 (en) * 2011-09-08 2017-06-07 株式会社タムラ製作所 Ga2O3 semiconductor device
WO2014120824A1 (en) * 2013-01-30 2014-08-07 Microchip Technology Incorporated Dmos semiconductor device with esd self-protection and lin bus driver comprising the same
US9647073B2 (en) * 2014-10-29 2017-05-09 Globalfoundries Inc. Transistor structures and fabrication methods thereof

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3845495A (en) * 1971-09-23 1974-10-29 Signetics Corp High voltage, high frequency double diffused metal oxide semiconductor device
US3909320A (en) * 1973-12-26 1975-09-30 Signetics Corp Method for forming MOS structure using double diffusion
US3926694A (en) * 1972-07-24 1975-12-16 Signetics Corp Double diffused metal oxide semiconductor structure with isolated source and drain and method
US3974486A (en) * 1975-04-07 1976-08-10 International Business Machines Corporation Multiplication mode bistable field effect transistor and memory utilizing same
US3996655A (en) * 1973-12-14 1976-12-14 Texas Instruments Incorporated Processes of forming insulated gate field effect transistors with channel lengths of one micron in integrated circuits with component isolated and product
US4072975A (en) * 1976-04-29 1978-02-07 Sony Corporation Insulated gate field effect transistor
US4119996A (en) * 1977-07-20 1978-10-10 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Complementary DMOS-VMOS integrated circuit structure
US4145703A (en) * 1977-04-15 1979-03-20 Supertex, Inc. High power MOS device and fabrication method therefor

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3845495A (en) * 1971-09-23 1974-10-29 Signetics Corp High voltage, high frequency double diffused metal oxide semiconductor device
US3926694A (en) * 1972-07-24 1975-12-16 Signetics Corp Double diffused metal oxide semiconductor structure with isolated source and drain and method
US3996655A (en) * 1973-12-14 1976-12-14 Texas Instruments Incorporated Processes of forming insulated gate field effect transistors with channel lengths of one micron in integrated circuits with component isolated and product
US3909320A (en) * 1973-12-26 1975-09-30 Signetics Corp Method for forming MOS structure using double diffusion
US3974486A (en) * 1975-04-07 1976-08-10 International Business Machines Corporation Multiplication mode bistable field effect transistor and memory utilizing same
US4072975A (en) * 1976-04-29 1978-02-07 Sony Corporation Insulated gate field effect transistor
US4145703A (en) * 1977-04-15 1979-03-20 Supertex, Inc. High power MOS device and fabrication method therefor
US4119996A (en) * 1977-07-20 1978-10-10 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Complementary DMOS-VMOS integrated circuit structure

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5598018A (en) * 1978-10-13 1997-01-28 International Rectifier Corporation High power MOSFET with low on-resistance and high breakdown voltage
US5742087A (en) * 1978-10-13 1998-04-21 International Rectifier Corporation High power MOSFET with low on-resistance and high breakdown voltage
EP0520831A2 (en) 1991-06-28 1992-12-30 Texas Instruments Incorporated Gated thyristor and process for its simultaneous fabrication with an integrated circuit
US5336637A (en) * 1991-09-19 1994-08-09 International Business Machines Corporation Silicide interconnection with Schottky barrier diode isolation
US5897355A (en) 1994-08-03 1999-04-27 National Semiconductor Corporation Method of manufacturing insulated gate semiconductor device to improve ruggedness
US5701023A (en) * 1994-08-03 1997-12-23 National Semiconductor Corporation Insulated gate semiconductor device typically having subsurface-peaked portion of body region for improved ruggedness
US5796126A (en) * 1995-06-14 1998-08-18 Samsung Electronics Co., Ltd. Hybrid schottky injection field effect transistor
US5686857A (en) * 1996-02-06 1997-11-11 Motorola, Inc. Zero-crossing triac and method
US20050227461A1 (en) * 2000-05-05 2005-10-13 International Rectifier Corporation Semiconductor device having increased switching speed
US8314002B2 (en) 2000-05-05 2012-11-20 International Rectifier Corporation Semiconductor device having increased switching speed
US20140021522A1 (en) * 2008-12-26 2014-01-23 Megica Corporation Chip packages with power management integrated circuits and related techniques
US8809951B2 (en) * 2008-12-26 2014-08-19 Megit Acquisition Corp. Chip packages having dual DMOS devices with power management integrated circuits
US10600907B2 (en) * 2017-05-31 2020-03-24 Magnachip Semiconductor, Ltd. High voltage semiconductor device

Also Published As

Publication number Publication date
USRE33209F1 (en) 1996-01-16
US4199774A (en) 1980-04-22

Similar Documents

Publication Publication Date Title
USRE33209E (en) Monolithic semiconductor switching device
US5014102A (en) MOSFET-gated bipolar transistors and thyristors with both turn-on and turn-off capability having single-polarity gate input signal
US4901132A (en) Semiconductor integrated circuit with switching bipolar transistors having high withstand voltage capability
US4969028A (en) Gate enhanced rectifier
US6091107A (en) Semiconductor devices
US5719411A (en) Three-terminal MOS-gate controlled thyristor structures with current saturation characteristics
US4860072A (en) Monolithic semiconductor device and method of manufacturing same
EP0084558B1 (en) Monolithically merged field effect transistor and bipolar junction transistor
US4989058A (en) Fast switching lateral insulated gate transistors
JPH0758784B2 (en) Lateral insulated gate bipolar transistor with improved latch-up prevention performance
US5430323A (en) Injection control-type Schottky barrier rectifier
US5032880A (en) Semiconductor device having an interposing layer between an electrode and a connection electrode
US6111289A (en) Semiconductor device
CA1252225A (en) Lateral insulated gate transistors with coupled anode and gate regions
EP0615292A1 (en) Insulated gate bipolar transistor
US4132996A (en) Electric field-controlled semiconductor device
EP0338312B1 (en) Insulated gate bipolar transistor
US5587595A (en) Lateral field-effect-controlled semiconductor device on insulating substrate
EP0630054A1 (en) Thyristor with insulated gate and method for operating the same
EP0115098B1 (en) Lateral dmos transistor device having an injector region
EP0065346A2 (en) Semiconductor switching device
US5608236A (en) Semiconductor device
US5331194A (en) Bipolar static induction transistor
EP0249088B1 (en) A semiconductor device
US4829349A (en) Transistor having voltage-controlled thermionic emission