USRE26087E - Multi-computer system including multiplexed memories. lookahead, and address interleaving features - Google Patents

Multi-computer system including multiplexed memories. lookahead, and address interleaving features Download PDF

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Publication number
USRE26087E
USRE26087E US26087DE USRE26087E US RE26087 E USRE26087 E US RE26087E US 26087D E US26087D E US 26087DE US RE26087 E USRE26087 E US RE26087E
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lookahead
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs

Definitions

  • TI-COMPUTER SYSTEM INCLUDING HULTIPLEXED IEIORIES. LOOKAHEAD, AND ADDRESS INTERLBAVING FEATURES 35 Sheets-Sheet Original Filed Dec. 30. 1959 5:2 ..
  • HAHN 1103 XM HA F5lR2l6-11) 3m AND" I ICTRUI) T noe l-DI- Sept. 20, 1966 s. w. DUNWELL ETAL Re. 26,087
  • FIG. 23 MONITOR REGISTER TO x. I. E. R1
  • HULTI-COHPUTER SYSTEM INCLUDING MULTIPLEXED MEMORIES, LOOKAHEAD, AND ADDRESS INTERLEAVING FEATURES Original Filad Dec. 30. 1959
  • Sheets-Sheet 18 F16
  • FIG. 33 INSTANTANEOUS END OPERATION F21 5101 11.11.11.
  • IULTIGOIPUTER SYSTEM INCLUDING IIUL'I'IPLEXED IEIIORIES. LOOKAHEAD, MID ADDRESS IN'I'BRLEAVING FEATURES 55 Sheets-Shut 19 lNHlBlT SAIPLE IEIH F9 INHIBIT IEII I F4 START HEN! F5 START "Ell Sept. 20, 1966 s. w. DUNWELL ETAL 26,087

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Micro-Organisms Or Cultivation Processes Thereof (AREA)
  • Multi Processors (AREA)
  • Medicines Containing Antibodies Or Antigens For Use As Internal Diagnostic Agents (AREA)
  • Debugging And Monitoring (AREA)

Description

Sept. 20, 1966 s. w. DUNWELL ETAL 26,037
WHIP-COMPUTER SYSTEM INCLUDING MULTIPLEXED MEMORIES, LOOKAHEAD, AND ADDRESS INTERLEAVING FEATURES Original Filed Dec. 30. 1959 :55 Sheets-Sheet 4 FIG-4 so T0 STORE CONTROL ()0 (a) F41 STORE BEHMID 0 STURE CYCLE 1X) 5 GO TO STORE CONTROL (4) RTHIH OR 60 T0 STORE CYCLE) N T611TL1 AND 2.3,4
Sept. 20, 1966 s. w. nuuwsu. ETAL 26,037
IULTI-COIPUTBR SYSTEK INCLUDING MULTIPLEXED IEIORIBS. LOOKAHEAD. AND ADDRESS INTERLEAVING FEATURES 35 Sheets-Sheet 5 Original Filed D00. 30, 1959 .1532. 2.. w 2.. 2...... 2...; z... H 2.. 2...; m... V 2.. z: 944 2. .5. 3 T E... 2.. 3. .2 J. .4 n .a .2... Y L b M 2...... E w: teams... 2...... .5 Q... .2 5.. :5 E. 2.... S 2.. 6. 6528 855. 20 op 8 :3 352... N .3 H 2.. @g 2.. V I -55 T 2.5.... .2. .1 E... 2.; n: E... 2.: n: :5 .2 5.. IL 2...
mo 12:... z... E 832...... :28... T 2 nz 2... 4 E... 2 .s z. 3.. 2. :E. :5 U E Z... .1 2:12.... .0 2; a. 2.1.2.: 2...... a... 3.. .I
Sept. 20, 1966 s. w. DUNWELL ETAL 26,037
TI-COMPUTER SYSTEM INCLUDING HULTIPLEXED IEIORIES. LOOKAHEAD, AND ADDRESS INTERLBAVING FEATURES 35 Sheets-Sheet Original Filed Dec. 30. 1959 5:2 ..||n|l. Q 5:5: 2 I1. 3;: w i TI! "2 z: i Ti: 51:: .2; 51mm .2 TI 5:258 NT; moT E252: n .535; V :E. :25 :0 .H. 61 1 7. ET l 2; v1.1 22 2; z; N; 2 E DE VIT T 5532: .P h C p 3 J i F F 2% 3858 Q2 2;: x0040 502m: E :5 v.1 0 GE E: E 2.3: :2:.E
was bi 5 ml 220 S:
222m :3 E: 3. 25 2: n2
's w. DUNWELL ETAL. 26,037
HULI'I-COMPUTER SYSTEM INCLUDING MULTIPLEXED MEMORIES, LOOKAHEAD. AND ADDRESS INTERLEAVING FEATURES Original Filed Due. 30, 1959 FIGJO Sept. 20. 1966 35 Sheets-Sheet '7 PRIORITY CONTROL 1001 m2 gagc0 TOOOPYCYCLE 1 1 7 M01 comou I mos l llgfigLREzF co m msr REF CYCLE 1oo9 AND uoroonmmz I QQ'Q co T0 mm STORE CYCLE I CNTL 3 /-NOT comma 1015 1021 r1019 W GOTOCONTROL ggsronc CYCLE CNTL 4 1022 1023 L 1021 1025 nor comm 1,2,5 ,1026 I i CNTL 5 100mm 1,2,s,4
I ms was CNTL to? 1W W "N DATA REF 6 f j CNTL 6 w /1058 norconmoL 1,2445 3 AND I 1059 um comm 1,255.55
co T0 msw REF cvcua W REF cNTm 1041/ Sept. 20, 1966 s. w. DUNWELL ETAL 26,037
MULTI-COPUTER SYSTEM INCLUDING MULTIPLEXED IEHORIBS, LOOKABEAD, AND ADDRESS INTHRLEAVING FEATURES Original Filed Doc. 30. 1959 35 Sheets-Sheet 8 CYCLE TIME GENERATOR FIG. 61 F9 mm on AND "Em rm 1/0 CHILE m2 F m on AND s1o4 s1oz\k T OR r2 so T0 COPY vm CYCLE i 6105 H2 A2.5(01) AND-J- FIG." GATING T0 MAB,ICTR, MAR
HAHN) 1103 XM HA F5lR2l6-11) 3m AND" I ICTRUI) T noe l-DI- Sept. 20, 1966 s. w. DUNWELL ETAL Re. 26,087
MULTI-COIIPUTER SYSTEM INCLUDING HULTIPLEXED IEIIORIES, LOOKAHEAD, AND ADDRESS INTERLEAVING FEATURES Original Filed Dec. 30. 1959 35 sheets 411m 9 FIG F9 3 MICRO SlEOCOND CIBOCK A2 I 1? 1" 1%05 12f 2&2? T T T i i if i i i FIG. 13
DELAY LINE FOR PRODUCING PULSE l2 mcnoszcouo CLOCK A0 M m u .5 T A2 666666 m 0.5SECDELAY 15 04 13 05 u na I I V I T T T q- T ll% n2 msasrnoumec cum I m no men 51:5[0 CLOCK r54 sum mm. CLOCK AND AND F was F59NORMALENO0FOPN T T pt 0. 1966 s. w. DUNWELL ETAL Re. 26,
IUL'l'I-COIPUTER SYSTEM INCLUDING MULTIPLEXED IBIIORIES, LOOKAHEAD, AND ADDRESS INTERLEAVING FEATURES Original Filed Dec. 30. 1959 35 Sheets-Sheet 10 CONTROL FOR MEMORY OR 2 TO MEM I: B OR TO X MEM FIG.15
SAMPUNG 0F MEM BUSES T0 MR AaB 0R x MR A OR B Sept. 20, 1966 S. W. DUNWELL ETAL Original Filed Dec. 30, 1959 CONTROL TO INDICATE MEMORY REGISTER A OR X MEMORY 55 Sheets-Sheet 1 1 REGISTER A EMPTY MEIIREGAEIIPTY H4 602 I m REG A LOADED 1606 HA HEIH IIEII m: A 1601 EMPTY H-I m2 nuAAEcA 0R T F. OR H? r59 am om momAAu AND TO RESET usz mm m A I605 I MEIIREGB EMPTY T "I603 xnEnREcA EMPTY F" I604 XHEM REcA LOADED AAA-woven 1611 MORE 6 IRA-HA0 OR-I 7 T IORENT,TV"F n4 MEN 1 -+x HEM REC A 1' A612 r14 usnz-uucmcA 0R IH I-I H F50! END 0m IIIORIIIIL) '1608 AND I TO RESET USE TOR F" XIIEH mac 8 EMPTY T m @609 FIGJG AAA-+AA00 AIR A no OR USE MR A A CONTROLS FOR SELECTING THE "m PROPER MEMORY REGISTER FOR READING INTO ADDER OR MQ F16 AAEAA REG A LoAuEu 1 FIZ I2.5(DI.0I AND T F16 masn m: A LOADED IGR use HR 8 I I F16 m REG 0 LUADED FIG. 17
CONTROLS FOR SELECTING THE PROPIER X MEMORY REGISTER FOR T READING INTO X ADDER OR X MO Sept. 20, 1966 s. w. DUNWELL ETAL 26,087
"ULTI-COMPUTER SYSTEM INCLUDING MULTIPLEXED MEMORIES, LOOKAHEAD, AND ADDRESS INTERLEAVING FEATURES Original Filed Dec. 30, 1959 :55 Sheets-Sheet 12 uszxmu VIBOI FIB RESET XIIII A LOADED TGR F" USE XMRB T 430 H6 x m REGB LOADED "3 JIZA 2 5 I I O) A T T HR RFQFT y I: l lmnrn nan ISIS ABC ADII IIEI I III BUFF II ADR- II II RI FI' F431 STORE ACCUII LOADING MEMORY READ IN BUFFERS FIG. 19
Sept. 20. 1966 s. w. DUNWELL ETAL 251037 HULTI-COMPUTER SYSTEM INCLUDING MULTIPLEXED MEMORIES, LOOKAHEAD, AND ADDRESS INTERLBAVING FEATURES Original Filed Dec. 30. 1959 55 Sheets-Sheet 13 FIG, CONTROL FOR MEMORY 1 0R 2 TO I/O REGISTER FOR WRITE COPY F61 WRITE COPY CYCLE FOR IIEIII AND 111E141 IS-35I-* V0 REG A F12 A1.5III1.0I 200' E61 WRITE COPY CYCLE FORIIEIIZ HQ 22 MONITOR REGISTER INST 11:1; svmcnss 1101111011 0P mom INST 5E6 svmcuzs COPY 115mm Posfi-1 P 11-1 H4 110111151111 Fm 1101111111111 s 5 I 2201 6 w 2204 18 z2os-. T 1- T T 1 2205 M i fi 5% M IL'IJT TI T'T T0 IIEII 8115* I10" REG III SWITCHES 112111010101 r H T 111 AND 11011111111 REGRESE os11us lccug II -i2 rzsnoun F WMQR m men EXIT T,.
msr 110 0? 1 1 FIG. 23 MONITOR REGISTER TO x. I. E. R1
F47 NOT LITGH "00E ZZIIONTIIRGOSI- A F36 X.I. .1 T0 .I.8.I."
1 2101 OR Wm AND F41 NOT LATCH MODE 1 =22 11011 TOR 1151; F08 111-1 E 25103 F55XI.I.R.1 EMPTY Sept. 20, 1966 s. w. DUNWELL ETAL ,0
MULTI-COMPUTER SYSTEM INCLUDING MULTIPLEXED MEMORIES. LOOKAHEAD. AND ADDRESS INTERLEAVING FEATURES Original Filed Dec. 30, 1959 35 Sheets-Sheet 14 g 41 0: g N w o N (9 DJ .J O n O m I- O 2 LU 2 n 2 r0 =5 E a 2-; i E 3 a g Q E v v 0 i F9 START MEN 1 Sept. 20, 1966 s. w. DUNWELL ETAL 25,087
MULTI-COIPUTER SYSTEM INCLUDING MULTIPI-IEXED IEIORIES, LOQKAHBAD; AND ADDRESS INTERLEAVING FEATURES Original Filed Dec. 30, 1959 55 Sheets-Sheet 15 F|G 4 CONTROLS FOR MEMORY IOR 2 TO MONITOR REG '6 ST REF CYCLE FOR IIEIII FIZ M5 (01.0) IIEII B I$(III(5'I8I- IOIIITOR RES (II) F22 HEIIIBUSIIIHS-III) 2401 F51 IIIST REF CYCLE IIEIIZ IIEIIZIIUSIIIHS-IB) xgqgg CONTROLS FOR MONITOR REGISTER TO INSTRUCTION REGS F52 MONITOR REG-*IIIST REGI FIG, 25 MoIIIToR REGIsTER STATUS TRIGGER MONITIJRREGFULL [a rIzIIIsIIIIoI I I F61 INST REFCYCLE IIEIII f T 2501 2502 F61 IIIsT REFCYCLE IIII2 ANG irzz IIoIIIIoII REGISTER RESET FIG-25 5 mum 2 CONTROL LINES FROM m I MONITOR REGISTER 3 con 0: n: EII.L g n: INSTANTANEOUSINSTRUCTIDN 8 e IIIIBIIIIII 0R 1 =F2I III 3 REM I IITIIIsTIIIsTRugTIoII W52 0. z IIEII 0 now Sept. 20, 1966 s. w. DUNWELL ETAL 26,037
MULTL-COMPUTER svs'rnm mcwnme MULTIPLEXED MEMORIES, LOOKAHBAD, AND ADDRESS INTERLEAVING FEATURES Original Filed Dec. 30, 1959 35 Sheets-Sheet 16 FIG'ZT BLOCK INSTRUCTION REFERENCE CYCLES msr INST m mm ,2105 msmn Egg 0? NOT BLOCK I IREFCYCLES In AND FIG. 29 COPY REGISTER 1 STATUS f P5; TR'GGER 009T REG 1 FULL if 2901 T n1 MR T0 an i H J'- r51 crmocaz JIHQF FIG. 30 new REG 2 EMPTY F 31 COPY REGISTER 2 STATUS OOPY REG2 FULL A TRIGGER T F 5: MR T0 CR 2 r31 cmmcaz 0R1 Sept. 20, 1966 s. w. DUNWELL ETAL Re. 26,087
' IIULTI-COIPUTER SYSTEM INCLUDING MULTIPLBXED IEHORIES, LOOKAHEAD. AND ADDRESS INTERLBAVING FEATURES Original Filad 08. 30. 1959 35 ShBBY-S-ShBGt 1? H623 INPUT T0 COPY REGISTERS T0 Posmom or COPY m2 9 T P051 OFCOPYRG zaos\ T T 2804 0 5% E m COPY nccwcorv m2 T T T m non REG +COPY am 1280 .l rzzuon ms r2 uonnzcn AND 2 rovosnmmormswncuzs m2 T0 P0512 or m svmcmzs zaos-k T H T, 2006 no COPY m2 smus m acsn T T T m 00PYREG1+COPY am (23? rza P051 or com um $51 now m COPY m2 r22 ms or MON REG ND L. 2808 F28 F051? 0F COPY m1 zaos AND rzzPosn or m are 2m FIG- 31 COPY REGISTER DUMPS COPY REM T0 COPY REGZ F29 3102 F31 Sept. 20, 1966 s. w. DUNWELL ETAL Re. 26,087
HULTI-COHPUTER SYSTEM INCLUDING MULTIPLEXED MEMORIES, LOOKAHEAD, AND ADDRESS INTERLEAVING FEATURES Original Filad Dec. 30. 1959 35 Sheets-Sheet 18 F16 32 STOP TRIGGER STOP TGR OFF F33 STOP TGR 0N T 121 STOP 11.11. 3202 11211.5 01 ANDlH l- H2 A2.0 01 A304 ANI5 szos FIG. 33 INSTANTANEOUS END OPERATION F21 5101 11.11. 1.1251111 1111011 AND 5302 1 1 3311s 111s11111111ooPro111111sTo1 F2 TR 11 OR in 1 ss os H A 1 a Y 2 200 OR 1115111110111 OP I a 121 1001* 11.11. F21 11m 11 11 52% F21 1111 11.11. am
1/0 111111 err l QR F21 11E11111111 11.11. m
1/0 1111111111 AND 121 SENSE 11.11.
1 F21 0011 11.11. I 129001 1115111 5111 111 AIiID 11115 Sept. 20. 1966 Original Filed Dec. 30, 1959 FIG. 34
INHIBIT SAMPLE GENERATOR s. w. DUNWELL ETAL Re. 26,087
IULTIGOIPUTER SYSTEM INCLUDING IIUL'I'IPLEXED IEIIORIES. LOOKAHEAD, MID ADDRESS IN'I'BRLEAVING FEATURES 55 Sheets-Shut 19 lNHlBlT SAIPLE IEIH F9 INHIBIT IEII I F4 START HEN! F5 START "Ell Sept. 20, 1966 s. w. DUNWELL ETAL 26,087
IULTI-COIPUTER SYSTEI IRCLUDING IULTIPLBXED IBIORIES, LDOKAHBAD. AND ADDRESS INTERLBAVIIIG FEATURES Original Filed Dec. so. 1959 :55 Sheets-Sheet. no
FIG. 35
STATUS INDICATOR rus. rua
rue n rs iris, rsiwk F G- 3 BUFFER REGISTER GATES mxm w x m2 35m xlans T0 m1 F55X|R1EHPTY 0R m r ma T m X3602 ma: T0 was rssx was [um OR F36 F36 X IBM T0 XIBR3 J 4503 am To an F23 rssx um um 0R rss mum none ,asos 4 rss x mm roman: AND 3 ma 8 W m :F m OR 36 F35X|BM cum Q 3606 m mcn nous ssoa m7 F36XIBR-BTOXIBR1 AND 1 6 XlBR-A 1 n r41 man no: rssxlan-a EMPTY AND{J369 m mun none m: TD mR-A rm PROLMGED snoo '1' Q 3m
US26087D 1959-12-30 Multi-computer system including multiplexed memories. lookahead, and address interleaving features Expired USRE26087E (en)

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Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3416139A (en) * 1966-02-14 1968-12-10 Burroughs Corp Interface control module for modular computer system and plural peripheral devices
US3426330A (en) * 1966-02-14 1969-02-04 Burroughs Corp Central data processor
US3435420A (en) * 1966-01-03 1969-03-25 Ibm Contiguous bulk storage addressing
US3478321A (en) * 1966-11-10 1969-11-11 Ibm Variable priority storage accessing control
US3490005A (en) * 1966-09-21 1970-01-13 Ibm Instruction handling unit for program loops
US3496551A (en) * 1967-07-13 1970-02-17 Ibm Task selection in a multi-processor computing system
US3573853A (en) * 1968-12-04 1971-04-06 Texas Instruments Inc Look-ahead control for operation of program loops
US3573852A (en) * 1968-08-30 1971-04-06 Texas Instruments Inc Variable time slot assignment of virtual processors
US3573854A (en) * 1968-12-04 1971-04-06 Texas Instruments Inc Look-ahead control for operation of program loops
US3623017A (en) * 1969-10-22 1971-11-23 Sperry Rand Corp Dual clocking arrangement for a digital computer
DE2542102A1 (en) * 1974-09-25 1976-04-08 Data General Corp DATA PROCESSING SYSTEM
EP0184791A1 (en) * 1984-12-07 1986-06-18 Nec Corporation Information processing device capable of rapidly processing instructions of different groups

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3307150A (en) * 1962-11-16 1967-02-28 Stromberg Carlson Corp Queue store
US3286239A (en) * 1962-11-30 1966-11-15 Burroughs Corp Automatic interrupt system for a data processor
US3349375A (en) * 1963-11-07 1967-10-24 Ibm Associative logic for highly parallel computer and data processing systems
US3334333A (en) * 1964-04-16 1967-08-01 Ncr Co Memory sharing between computer and peripheral units
US3343140A (en) * 1964-10-27 1967-09-19 Hughes Aircraft Co Banked memory system
US3348210A (en) * 1964-12-07 1967-10-17 Bell Telephone Labor Inc Digital computer employing plural processors
US3519842A (en) * 1964-12-17 1970-07-07 Matsushita Electric Ind Co Ltd Voltage switching device
FR1477814A (en) * 1965-04-05 1967-07-07
US3377621A (en) * 1965-04-14 1968-04-09 Gen Electric Electronic data processing system with time sharing of memory
US3373408A (en) * 1965-04-16 1968-03-12 Rca Corp Computer capable of switching between programs without storage and retrieval of the contents of operation registers
US3449723A (en) * 1966-09-12 1969-06-10 Ibm Control system for interleave memory
JPS514381B1 (en) * 1969-11-24 1976-02-10
US3713096A (en) * 1971-03-31 1973-01-23 Ibm Shift register interconnection of data processing system
BE789583A (en) * 1971-10-01 1973-02-01 Sanders Associates Inc PROGRAM CONTROL APPARATUS FOR DATA PROCESSING MACHINE
DE2717374C2 (en) * 1977-04-20 1985-06-20 Hughes Aircraft Co., Culver City, Calif. Data processing system
JPS5848146A (en) * 1981-09-18 1983-03-22 Toshiba Corp Instruction prefetch system
JPS5858653A (en) * 1981-10-02 1983-04-07 Hitachi Ltd Data processor

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE496518A (en) * 1949-06-22
US2925588A (en) * 1954-12-31 1960-02-16 Rca Corp Memory reading system
US2914248A (en) * 1956-03-07 1959-11-24 Ibm Program control for a data processing machine
US3070304A (en) * 1957-04-12 1962-12-25 Thompson Ramo Wooldridge Inc Arithmetic unit for digital control systems
US3058658A (en) * 1957-12-16 1962-10-16 Electronique Soc Nouv Control unit for digital computing systems
US3020525A (en) * 1958-04-04 1962-02-06 American Telephone & Telegraph Record controlled translator
US3061192A (en) * 1958-08-18 1962-10-30 Sylvania Electric Prod Data processing system

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3435420A (en) * 1966-01-03 1969-03-25 Ibm Contiguous bulk storage addressing
US3416139A (en) * 1966-02-14 1968-12-10 Burroughs Corp Interface control module for modular computer system and plural peripheral devices
US3426330A (en) * 1966-02-14 1969-02-04 Burroughs Corp Central data processor
US3490005A (en) * 1966-09-21 1970-01-13 Ibm Instruction handling unit for program loops
US3478321A (en) * 1966-11-10 1969-11-11 Ibm Variable priority storage accessing control
US3496551A (en) * 1967-07-13 1970-02-17 Ibm Task selection in a multi-processor computing system
US3573852A (en) * 1968-08-30 1971-04-06 Texas Instruments Inc Variable time slot assignment of virtual processors
US3573853A (en) * 1968-12-04 1971-04-06 Texas Instruments Inc Look-ahead control for operation of program loops
US3573854A (en) * 1968-12-04 1971-04-06 Texas Instruments Inc Look-ahead control for operation of program loops
US3623017A (en) * 1969-10-22 1971-11-23 Sperry Rand Corp Dual clocking arrangement for a digital computer
DE2542102A1 (en) * 1974-09-25 1976-04-08 Data General Corp DATA PROCESSING SYSTEM
EP0184791A1 (en) * 1984-12-07 1986-06-18 Nec Corporation Information processing device capable of rapidly processing instructions of different groups

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GB888732A (en)
DE1178623C2 (en) 1973-01-25
US3202969A (en) 1965-08-24
DE1178623B (en) 1964-09-24

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