USH1222H - Apparatus for determining sticky bit value in arithmetic operations - Google Patents

Apparatus for determining sticky bit value in arithmetic operations Download PDF

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Publication number
USH1222H
USH1222H US07/814,934 US81493491A USH1222H US H1222 H USH1222 H US H1222H US 81493491 A US81493491 A US 81493491A US H1222 H USH1222 H US H1222H
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United States
Prior art keywords
register
fraction
output
trailing
bit
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Abandoned
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US07/814,934
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English (en)
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Jeffrey D. Brown
Roy R. Faget
Scott A. Hilker
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International Business Machines Corp
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International Business Machines Corp
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Priority to US07/814,934 priority Critical patent/USH1222H/en
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION A CORPORATION OF NY reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION A CORPORATION OF NY ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: HILKER, SCOTT A., BROWN, JEFFREY D., FAGET, ROY R.
Priority to JP4299146A priority patent/JPH05241787A/ja
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Publication of USH1222H publication Critical patent/USH1222H/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49942—Significance control
    • G06F7/49947—Rounding
    • G06F7/49952—Sticky bit

Definitions

  • the present invention relates to an apparatus for performing certain floating point arithmetic operations in a data processing system. More particularly, the invention relates to an apparatus simplifying the completion of floating point arithmetic operations by processing the operands to form an early determination of the value of the "sticky bit" which appears in the floating point resultant value.
  • the typical floating point arithmetic operation may be accomplished in either single precision or double precision format.
  • Each of these formats utilizes a sign, exponent and fraction field, where the respective fields occupy predefined portions of the floating point number.
  • the sign field is a single bit occupying the most significant bit position
  • the exponent field is an 8-bit quantity occupying the next-most significant bit positions
  • the fraction field occupies the least significant 23-bit positions.
  • the sign field is a single bit occupying the most significant bit position
  • the exponent field is an 11-bit field occupying the next-most significant bit positions
  • the fraction field is a 52-bit field occupying the least significant bit positions.
  • each floating point answer After each floating point answer is developed, it must be normalized and then rounded. When the answer is normalized, the number of leading zeros in the fraction field is counted. This number is then subtracted from the exponent and the fraction is shifted left until a "1" resides in the most significant bit position of the fraction field.
  • indicator bits are injected into the fraction field of the floating point number, and are used by the arithmetic control logic to indicate when certain conditions exist in the floating point operation. For example, an "implicit" bit I is set to "1" by the arithmetic control logic when the exponent of the floating point number has a nonzero value.
  • the implicit bit I is created at the time a floating point number is loaded into the arithmetic registers, and the implicit bit I occupies the first bit position in the fraction field of the number.
  • a "guard" bit G is set by the floating point control logic during certain arithmetic operations, as an indicator of how to round.
  • the G bit occupies a position which is one bit less significant than the least significant bit (LSB) of the result before rounding.
  • a "sticky" bit S is an indicator bit which is set in all floating point arithmetic operations when any bit of lower precision than the guard (G) bit is a "1," as an indicator that the floating point number has lost some precision.
  • the extra bits in the fraction field are used exclusively for rounding operations, after the result has been normalized.
  • the guard (G) bit is treated as if it is a part of the fraction; it is shifted with the rest of the fraction, and included in all arithmetic.
  • the sticky (S) bit is not shifted with the fraction, but is included in the arithmetic. It acts as a "catcher" for 1's shifted off the right of the fraction; when a 1 is shifted off the right side of the fraction, the S bit will remain a 1 until normalization and rounding are finished.
  • the “round to nearest” mode means that the value nearest to the infinitely precise result should be delivered. If the two nearest representable values are equally near, the one with its least significant bit zero shall be delivered.
  • the “round to positive infinity” mode means that the value closest to and not less than the infinitely precise result should be delivered.
  • the “round to negative infinity” mode means that the value closest to and not greater than the infinitely precise result should be delivered.
  • the “round to zero” mode means that the result delivered should be the closest to but not greater in magnitude than the infinitely precise result.
  • U.S. Pat. No. 4,639,887 discloses an apparatus for decreasing the latency time associated with floating point addition and subtraction.
  • the invention uses duplicate hardware for the calculation of the arithmetic operation on the fraction portion of a floating point number, and then selects a resultant value based upon exponent differences.
  • any floating point operation in a data processing system it is desirable to increase the efficiency of one or more of the floating point operations, for an increase in this efficiency translates directly into a proportionate time savings in systems operation.
  • Certain efficiencies are possible in specialized situations, some of which are illustrated in the foregoing prior art disclosures, and it is important to take advantage of these efficiencies, particularly if the special situations may be encountered relatively frequently during the course of data processing operations. For example, floating point arithmetic calculations frequently require a normalize operation when an answer is developed, and a rounding operation if the answer is inexact. However, either or both of these operations may be skipped when certain result conditions exist, thereby saving the time otherwise required for executing these operations.
  • the states of the guard (G), sticky (S), and the least significant bit (LSB), the resultant sign, and the rounding mode are all used to determine whether or not the LSB should be incremented in order to deliver a correctly-rounded fraction result.
  • the state of the sticky (S) bit must usually be known prior to delivering a final result.
  • the present invention provides a method and apparatus for processing the operands to make a determination of the sticky (S) bit, independent of the floating point processing calculation, which may be ongoing simultaneously with the processing according to the teachings of the present invention.
  • the invention utilizes circuitry for detecting the number of trailing zeroes in each of the operands for which a floating point operation is underway.
  • the trailing zero detector logic for each operand is coupled into an adder to produce a sum value and a comparator compares this value against a predetermined value to determine the final value of the sticky bit required for the arithmetic floating point operation.
  • the invention may be used, with some variation, in conjunction with floating point multiply, divide and square root calculations.
  • FIG. 1 shows a block diagram of the apparatus for use in multiplication operations
  • FIG. 2 shows a block diagram of the apparatus for use in division operations
  • FIG. 3 shows a block diagram of the apparatus for use in square root operations.
  • the present invention is useful for determining the proper sticky bit (S) value for both multiplication and division arithmetic operations.
  • the invention may also be utilized for specialized division operations, such as square root arithmetic operations.
  • the invention will be described hereinafter, first with reference to a multiplication operation, and then with reference to a division operation, and finally with reference to a square root operation. For all operations, the implicit bit (1) is assumed to be a "1.”
  • an apparatus for practice of the invention in connection with a multiplication operation.
  • the apparatus illustrated operates independently and simultaneously with the circuitry for performing the actual multiplication calculation, and the apparatus produces a sticky bit value which is available simultaneously with the resultant value determined from the multiplication circuitry.
  • the sticky bit value is calculated by determining the value of trailing zero bits in both the multiplicand and multiplier fraction operands.
  • the number of trailing zero bits in a fraction is a direction measure of the precision of the operand; the precision of the input operands is used to predict the precision of the output fraction, as it would be represented if there were an unlimited number of bit positions.
  • the predicted resultant fraction precision is used to determine the state of the sticky bit. To pre-determine the precision of a product result, it is helpful to first consider the basic premises for multiplication of two binary values. If L A represents the length of a binary operand A which only encompasses the binary "1" values, all leading and trailing zeroes may be ignored along with the location of the binary point. Therefore, let L B and L C represent the length of operands B and C, in the same manner., If we examine the product C for the equation:
  • the apparatus illustrated in FIG. 1 performs the necessary comparisons and calculations for determining the sticky bit value for the product of any multiplicand fraction and any multiplier fraction.
  • the example illustrates a double precision arithmetic operation, but a similar example would apply to single precision, and single and double extended precision arithmetic operations, since the bit position location of the sticky bit is well known and established for all of these different arithmetic operations.
  • the multiplicand fraction is held in a register 10, and the multiplier fraction is held in a register 20.
  • the 52-bits of register 10 are monitored by a trailing zero detector logic circuit 12, which will produce a 6-bit binary output indicative of the number of trailing zeroes detected in circuit 12. Since any number of trailing zeroes may exist, from 1-52, the 6-bit output binary representation is adequate to represent any number of trailing zeroes which may occur.
  • the multiplier fraction held in register 20 is similarly monitored by a trailing zero detector logic circuit 22. Circuit 22 produces a 6-bit binary output value which is indicative of the number of trailing zeroes detected in the multiplier fraction.
  • the binary output values detected by circuits 12 and 22 are connected into an adder circuit 30 which produces the sum of the two inputs at output 31.
  • the sum of two 6-bit input values may produce a 7-bit output value, and output 31 is capable of representing any 7-bit output value which results from the addition operation.
  • Output 31 is coupled into a comparator circuit 40 which compares the output value to a constant numerical value "51,” which is connected as the second input into comparator 40.
  • the significance of the comparison relates to the size of the resultant fraction register, and the respective bit positions which have been selected to hold the guard bit (G) and the sticky bit (S). It is well recognized that the multiplication of two 53-bit fractions (including the implicit bit) will produce a 106-bit fractional result if absolute precision is to be maintained.
  • the actual resultant fraction occupies bit positions 2-53, i.e., a 52-bit field.
  • the guard bit (G) occupies bit position 54.
  • Comparator 40 determines whether the sum of the two input precisions is less than or equal to the precision measured out to the guard bit position. If the sum of the two input precisions is less than or equal to the precision measured out to the guard bit position, the sticky bit must be equal to zero, which is the value which the multiplication operation will assign to the sticky bit, via a signal on line 41, so the multiplication process will force the sticky bit value to become set equal to zero.
  • the sticky bit value is therefore simply equal to the value of the bit in the sticky bit position after a possible 1-bit normalization shift, and the circuit permits the sticky bit position value to be determined by the multiplication operation itself, by a signal on line 43.
  • the reciprocal of 0011 is 0.01010101010101 . . . , which is multiplied by 1100 to produce 0011.11111111111 . . . , which will be 1-bit in error in the least significant position wherever that position is.
  • FIG. 2 a block diagram of the logic circuits required for predicting the sticky (S) bit for a divide operation is shown.
  • the dividend fraction is held in a register 100
  • the divisor fraction is held in a register 120.
  • Register 100 and register 120 are each connected to trailing zero logic detection circuits, register 100 being connected to circuit 112, and register 120 being connected to circuit 122.
  • Each of the trailing zero logic detection circuits produces a binary output value which is indicative of the number of trailing zeros in the respective fractions.
  • the output values from circuits 112 and 122 are connected as inputs into a subtracter circuit 130, which is a two's complement adder, with a constant adjustment of +54; the output from circuit 122 is complemented.
  • the output from subtracter circuit 130 is connected as an input to comparator circuit 140.
  • Register 150 is connected to trailing zero logic detection circuit 152, which produces a binary output value indicative of the number of trailing zeros in the quotient fraction measured from the guard bit position.
  • the output from circuit 152 is connected as an input to comparator circuit 140.
  • Comparator circuit 140 produces an output which is connected to the sticky bit (S) position in the resultant register; i.e., if comparator 140 determines that the two input values are equal the output "S" on line 141 is zero, and if comparator 140 determines that the two input values are unequal the output "S" on line 141 is "1.”
  • a square root arithmetic operation may be thought of as a special case divide operation, wherein the dividend is known and a determination must be made to identify a divisor and quotient having equal values.
  • the "dividend” is referred to as the radicand fraction
  • the "divisor” and “quotient” are referred to as "root fractions.”
  • the significance of the radicand is the length of the fraction field minus the number of trailing zeros.
  • the significance of the root can never exceed 1/2 the fraction field length unless the root is irrational and has infinite length (for example, the square root of 2). Therefore, for all cases where the root significance is not infinite, the sticky bit (S) will be zero and the number of bits of significance L ROOT is determined as shown above. The problem then becomes one of determining when the root will have infinite significance, and thus have a sticky bit (S) of "1."
  • FIG. 3 shows a block diagram for determining the sticky bit (S) value in square root operations.
  • the radicand is held in register 200, and register 200 is connected to a trailing zero logic detection circuit 212.
  • Circuit 212 is connected to a "divide by 2" circuit 230, which may merely be a circuit for right shifting the output value by one position, prior to connecting the output value to an input of comparator 240.
  • the other input to comparator 240 is connected to the output from trailing zero logic detector circuit 252.
  • Circuit 252 receives its input from the resultant root fraction register 250.
  • comparator 240 determines that the number of trailing zeros from circuit 230 are equal to the number of trailing zeros from circuit 252, the signal on output line 241 forces the sticky bit (S) position to a zero; if comparator 240 determines that the number of trailing zeros from circuit 230 are not equal to the number of trailing zeros from circuit 252, the signal on output line 241 forces the sticky bit (S) position to a "1.”

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  • General Physics & Mathematics (AREA)
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  • Pure & Applied Mathematics (AREA)
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US07/814,934 1991-12-30 1991-12-30 Apparatus for determining sticky bit value in arithmetic operations Abandoned USH1222H (en)

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US07/814,934 USH1222H (en) 1991-12-30 1991-12-30 Apparatus for determining sticky bit value in arithmetic operations
JP4299146A JPH05241787A (ja) 1991-12-30 1992-10-13 算術演算におけるスティッキイ・ビット値の判別装置

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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5341319A (en) * 1993-02-10 1994-08-23 Digital Equipment Corporation Method and apparatus for controlling a rounding operation in a floating point multiplier circuit
US5434809A (en) * 1989-10-16 1995-07-18 Matsushita Electric Industrial Co., Ltd. Method and apparatus for performing floating point arithmetic operation and rounding the result thereof
US5471410A (en) * 1994-10-14 1995-11-28 International Business Machines Corporation Method and apparatus for sticky and leading one detection
US5732007A (en) * 1995-05-18 1998-03-24 Sun Microsystems, Inc. Computer methods and apparatus for eliminating leading non-significant digits in floating point computations
US5742537A (en) * 1995-06-30 1998-04-21 Wolrich; Gilbert M. Fast determination of floating point sticky bit from input operands
US5745744A (en) * 1995-10-12 1998-04-28 International Business Machines Corporation High speed mask generation using selection logic
US5808926A (en) * 1995-06-01 1998-09-15 Sun Microsystems, Inc. Floating point addition methods and apparatus
US5844830A (en) * 1996-08-07 1998-12-01 Sun Microsystems, Inc. Executing computer instrucrions by circuits having different latencies
US5944773A (en) * 1997-06-25 1999-08-31 Sun Microsystems, Inc. Floating-point multiplier circuit for generating the sticky-bit from the input operands
US6044391A (en) * 1997-06-25 2000-03-28 Sun Microsystems, Inc. Method of generating the sticky-bit from the input operands
US6516333B1 (en) * 1998-12-25 2003-02-04 Fujitsu Limited Sticky bit value predicting circuit

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100336014C (zh) * 2004-05-12 2007-09-05 中国人民解放军国防科学技术大学 并行粘接位计算部件设计方法

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5434809A (en) * 1989-10-16 1995-07-18 Matsushita Electric Industrial Co., Ltd. Method and apparatus for performing floating point arithmetic operation and rounding the result thereof
US5633818A (en) * 1989-10-16 1997-05-27 Matsushita Electric Industrial Co., Ltd. Method and apparatus for performing floating point arithmetic operation and rounding the result thereof
US5341319A (en) * 1993-02-10 1994-08-23 Digital Equipment Corporation Method and apparatus for controlling a rounding operation in a floating point multiplier circuit
US5471410A (en) * 1994-10-14 1995-11-28 International Business Machines Corporation Method and apparatus for sticky and leading one detection
US5732007A (en) * 1995-05-18 1998-03-24 Sun Microsystems, Inc. Computer methods and apparatus for eliminating leading non-significant digits in floating point computations
US5808926A (en) * 1995-06-01 1998-09-15 Sun Microsystems, Inc. Floating point addition methods and apparatus
US5742537A (en) * 1995-06-30 1998-04-21 Wolrich; Gilbert M. Fast determination of floating point sticky bit from input operands
US5745744A (en) * 1995-10-12 1998-04-28 International Business Machines Corporation High speed mask generation using selection logic
US5844830A (en) * 1996-08-07 1998-12-01 Sun Microsystems, Inc. Executing computer instrucrions by circuits having different latencies
US5963461A (en) * 1996-08-07 1999-10-05 Sun Microsystems, Inc. Multiplication apparatus and methods which generate a shift amount by which the product of the significands is shifted for normalization or denormalization
US6099158A (en) * 1996-08-07 2000-08-08 Sun Microsystems, Inc. Apparatus and methods for execution of computer instructions
US5944773A (en) * 1997-06-25 1999-08-31 Sun Microsystems, Inc. Floating-point multiplier circuit for generating the sticky-bit from the input operands
US6044391A (en) * 1997-06-25 2000-03-28 Sun Microsystems, Inc. Method of generating the sticky-bit from the input operands
US6516333B1 (en) * 1998-12-25 2003-02-04 Fujitsu Limited Sticky bit value predicting circuit

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