USH1041H - Method of reducing the surface leakage on a III-V semiconductor - Google Patents
Method of reducing the surface leakage on a III-V semiconductor Download PDFInfo
- Publication number
- USH1041H USH1041H US07/687,604 US68760491A USH1041H US H1041 H USH1041 H US H1041H US 68760491 A US68760491 A US 68760491A US H1041 H USH1041 H US H1041H
- Authority
- US
- United States
- Prior art keywords
- semiconductor
- gaas
- leakage
- fet
- reducing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H10P14/6312—
-
- H10P14/68—
Definitions
- This invention relates in general to a method of reducing the surface leakage on a III-V semiconductor and in particular to such a method where the III-V semiconductor is a gallium arsenide field effect transistor FET.
- GaAs In the instance when GaAs is the semiconductor, Ga 2 O 3 is selectively grown on the GaAs surface. GaAs can be oxidized by various oxidants forming a mixed gallium-arsenic oxide. This oxide has very poor electrical properties. Our desirable method forms the mixed oxide by photo oxidation in water. In pH neutral water, the arsenic oxide selectively dissolves leaving a gallium oxide. Auger and RBS analysis shows the oxide to be Ga 2 O 3 . This oxide passivates the GaAs surface and reduces the surface leakage. The amount of oxide required is only enough to give good coverage of the surface. Hence, there is very little etching of the GaAs during oxidation.
- the GaAs FET to be treated is placed in a container of deionized water.
- the immersed FET is illuminated with lamp light.
- the FET is removed when sufficient oxide has grown to effect the desired improvement of gate leakage and breakdown voltage, typically about 15 minutes. For a fixed voltage, there is an order of magnitude reduction in gate leakage.
- the aforesaid method of reducing gate leakage and increasing gate to drain breakdown voltage utilizes a post-fabrication surface treatment in contrast to imposing design constraints on the FET.
- the FET field-effect transistor
- the method is exceedingly simple to implement in that a light source and deionized water are the only equipment needed. Then too, the device to be treated needs no prior preparation. Also, the method is quick, typically requiring less than 30 minutes to complete.
- the method of the invention may be used whenever it is desired to reduce surface leakage on any GaAs semiconductor device.
- the most immediate application is to GaAs microwave FET's for both commercial and military use.
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
The surface leakage on a III-V semiconductor is reduced by selectively grng a mixed oxide on the surface of the semiconductor to passivate the semiconductor and reduce the surface leakage.
Description
The invention described herein may be manufactured, used, and licensed by or for the Government for governmental purposes without the payment to us of any royalty thereon.
This invention relates in general to a method of reducing the surface leakage on a III-V semiconductor and in particular to such a method where the III-V semiconductor is a gallium arsenide field effect transistor FET.
Gate leakage and gate to drain breakdown impose several constraints on the operation of GaAs FET's. In particular, maximum power gain of high frequency power transistors is limited by these quantities. The majority of techniques for extending these limits have involved design modifications of the FET such as locating the FET gate as far from the drain as is possible while maintaining good high frequency characteristics.
The general object of this invention is to provide a method of reducing the surface leakage on a III-V semiconductor. A more particular object of the invention is to provide such a method that will reduce the gate leakage and increase the gate to drain breakdown voltage of GaAs FET's. A still further object of the invention is to provide such a method in which there will be no design constraints placed on the FET. Another object of the invention is to provide such a method that is simple to implement.
It has now been found that the aforementioned objects can be attained by selectively growing an oxide on the semiconductor surface that passivates the semiconductor surface and reduces the surface leakage.
In the instance when GaAs is the semiconductor, Ga2 O3 is selectively grown on the GaAs surface. GaAs can be oxidized by various oxidants forming a mixed gallium-arsenic oxide. This oxide has very poor electrical properties. Our desirable method forms the mixed oxide by photo oxidation in water. In pH neutral water, the arsenic oxide selectively dissolves leaving a gallium oxide. Auger and RBS analysis shows the oxide to be Ga2 O3. This oxide passivates the GaAs surface and reduces the surface leakage. The amount of oxide required is only enough to give good coverage of the surface. Hence, there is very little etching of the GaAs during oxidation.
The GaAs FET to be treated is placed in a container of deionized water. The immersed FET is illuminated with lamp light. The FET is removed when sufficient oxide has grown to effect the desired improvement of gate leakage and breakdown voltage, typically about 15 minutes. For a fixed voltage, there is an order of magnitude reduction in gate leakage.
The aforesaid method of reducing gate leakage and increasing gate to drain breakdown voltage utilizes a post-fabrication surface treatment in contrast to imposing design constraints on the FET.
There are no design constraints on the FET according to the method of the invention. Moreover, the method is exceedingly simple to implement in that a light source and deionized water are the only equipment needed. Then too, the device to be treated needs no prior preparation. Also, the method is quick, typically requiring less than 30 minutes to complete.
The method of the invention may be used whenever it is desired to reduce surface leakage on any GaAs semiconductor device. The most immediate application is to GaAs microwave FET's for both commercial and military use.
We wish it to be understood that we do not desire to be limited to the exact details of construction shown and described for obvious modifications will occur to a person skilled in the art.
Claims (6)
1. Method of reducing the surface leakage on a III-V semiconductor comprising selectively growing a mixed oxide on the surface of the semiconductor to passivate the semiconductor and reduce the surface leakage.
2. Method according to claim 1 wherein the III-V semiconductor is a GaAs semiconductor.
3. Method of reducing the gate leakage and increasing the breakdown voltage of a GaAs field effect transistor (FET) comprising forming a mixed oxide by photo oxidation in water to passivate the surface of the GaAs and reduce the surface leakage.
4. Method according to claim 3 wherein the water is a pH neutral water in which arsenic oxide selectively dissolves leaving a gallium oxide Ga2 O3 that passivates the GaAs surface and reduces the surface leakage.
5. Method of reducing the gate leakage and increasing the breakdown voltage of a GaAs FET comprising immersing the FET in a container of deionized water and illuminating with a lamp and then removing the FET when sufficient oxide had grown to effect the desired improvement of gate leakage and breakdown voltage.
6. Method according to claim 5 wherein the method requires less than 30 minutes to complete.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/687,604 USH1041H (en) | 1991-04-15 | 1991-04-15 | Method of reducing the surface leakage on a III-V semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/687,604 USH1041H (en) | 1991-04-15 | 1991-04-15 | Method of reducing the surface leakage on a III-V semiconductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| USH1041H true USH1041H (en) | 1992-04-07 |
Family
ID=24761081
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US07/687,604 Abandoned USH1041H (en) | 1991-04-15 | 1991-04-15 | Method of reducing the surface leakage on a III-V semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| US (1) | USH1041H (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5877073A (en) * | 1996-05-07 | 1999-03-02 | Mosel Vitelic, Inc. | Modified poly-buffered locos forming technology avoiding the positive charge trapping at the beak of field oxide |
| US5880029A (en) * | 1996-12-27 | 1999-03-09 | Motorola, Inc. | Method of passivating semiconductor devices and the passivated devices |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2529384B1 (en) | 1982-06-25 | 1986-04-11 | Thomson Csf | METHOD FOR REDUCING A LAYERED COMPOUND ON A SUBSTRATE AND ITS APPLICATION TO THE MANUFACTURE OF A FIELD-EFFECT SEMICONDUCTOR STRUCTURE |
| US5021365A (en) | 1986-06-16 | 1991-06-04 | International Business Machines Corporation | Compound semiconductor interface control using cationic ingredient oxide to prevent fermi level pinning |
-
1991
- 1991-04-15 US US07/687,604 patent/USH1041H/en not_active Abandoned
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2529384B1 (en) | 1982-06-25 | 1986-04-11 | Thomson Csf | METHOD FOR REDUCING A LAYERED COMPOUND ON A SUBSTRATE AND ITS APPLICATION TO THE MANUFACTURE OF A FIELD-EFFECT SEMICONDUCTOR STRUCTURE |
| US5021365A (en) | 1986-06-16 | 1991-06-04 | International Business Machines Corporation | Compound semiconductor interface control using cationic ingredient oxide to prevent fermi level pinning |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5877073A (en) * | 1996-05-07 | 1999-03-02 | Mosel Vitelic, Inc. | Modified poly-buffered locos forming technology avoiding the positive charge trapping at the beak of field oxide |
| US5880029A (en) * | 1996-12-27 | 1999-03-09 | Motorola, Inc. | Method of passivating semiconductor devices and the passivated devices |
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| STCF | Information on status: patent grant |
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