USD958368S1 - Laminoplasty hinged plate with integrated spacer - Google Patents

Laminoplasty hinged plate with integrated spacer Download PDF

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Publication number
USD958368S1
USD958368S1 US29/817,150 US202129817150F USD958368S US D958368 S1 USD958368 S1 US D958368S1 US 202129817150 F US202129817150 F US 202129817150F US D958368 S USD958368 S US D958368S
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US
United States
Prior art keywords
laminoplasty
hinged plate
integrated spacer
spacer
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US29/817,150
Inventor
John Abe Perryman
Larry T. Khoo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Choice Spine LLC
Original Assignee
Choice Spine LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Choice Spine LLC filed Critical Choice Spine LLC
Priority to US29/817,150 priority Critical patent/USD958368S1/en
Assigned to CHOICE SPINE, LLC reassignment CHOICE SPINE, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: PERRYMAN, JOHN ABE, KHOO, LARRY T, DR.
Application granted granted Critical
Publication of USD958368S1 publication Critical patent/USD958368S1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/109—Control signal input circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0242—Structural details of individual signal conductors, e.g. related to the skin effect
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0243—Printed circuits associated with mounted high frequency components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/09327—Special sequence of power, ground and signal layers in multilayer PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10159—Memory
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10689—Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)

Description

FIG. 1 is an upper perspective view of a laminoplasty hinged plate with integrated spacer of our design.
FIG. 2 is a left side view thereof, the right side view being identical thereto; and,
FIG. 3 is a top view thereof.

Claims (1)

    CLAIM
  1. The ornamental design for a laminoplasty hinged plate with integrated spacer, as shown and described.
US29/817,150 2019-06-21 2021-11-29 Laminoplasty hinged plate with integrated spacer Active USD958368S1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US29/817,150 USD958368S1 (en) 2019-06-21 2021-11-29 Laminoplasty hinged plate with integrated spacer

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/448,541 US11107507B2 (en) 2019-06-21 2019-06-21 Transmitting data signals on separate layers of a memory module, and related methods, systems and apparatuses
US29/817,150 USD958368S1 (en) 2019-06-21 2021-11-29 Laminoplasty hinged plate with integrated spacer

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US16/448,541 Continuation US11107507B2 (en) 2019-06-21 2019-06-21 Transmitting data signals on separate layers of a memory module, and related methods, systems and apparatuses

Publications (1)

Publication Number Publication Date
USD958368S1 true USD958368S1 (en) 2022-07-19

Family

ID=73799562

Family Applications (3)

Application Number Title Priority Date Filing Date
US16/448,541 Active US11107507B2 (en) 2019-06-21 2019-06-21 Transmitting data signals on separate layers of a memory module, and related methods, systems and apparatuses
US17/443,673 Pending US20210358526A1 (en) 2019-06-21 2021-07-27 Transmitting data signals on separate layers of a memory module, and related methods and apparatuses
US29/817,150 Active USD958368S1 (en) 2019-06-21 2021-11-29 Laminoplasty hinged plate with integrated spacer

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US16/448,541 Active US11107507B2 (en) 2019-06-21 2019-06-21 Transmitting data signals on separate layers of a memory module, and related methods, systems and apparatuses
US17/443,673 Pending US20210358526A1 (en) 2019-06-21 2021-07-27 Transmitting data signals on separate layers of a memory module, and related methods and apparatuses

Country Status (2)

Country Link
US (3) US11107507B2 (en)
CN (1) CN112116930B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USD1028238S1 (en) * 2021-05-17 2024-05-21 M3 Health Industria E Comércio De Produtos Médicos, Odontológicos E Correlatos S.A. Dental implant applied to cranial fossa and minimally invasive plate
USD1028237S1 (en) * 2021-05-04 2024-05-21 M3 Health Indústria E Comércio De Produtos Médicos, Odontológicos E Correlatos S.A. Dental implant applied to cranial fossa and condylar plate
USD1028239S1 (en) * 2021-07-31 2024-05-21 M3 Health Industria E Comércio De Produtos Médicos, Odontológicos E Correlatos S.A. Dental implant applied to cranial fossa and condylar plate

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11887688B2 (en) * 2021-10-26 2024-01-30 Micron Technology, Inc. Techniques for indicating row activation

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US5376121A (en) * 1991-08-06 1994-12-27 Techmedica, Inc. Dual constraint elbow prosthesis
US20080208344A1 (en) * 2007-02-06 2008-08-28 Kilpela Thomas S Intervertebral Implant Devices and Methods for Insertion Thereof
US20190083146A1 (en) * 2017-09-15 2019-03-21 Choice Spine, Lp Laminoplasty Hinges
US20200000499A1 (en) * 2017-03-16 2020-01-02 Olympus Terumo Biomaterials Corp. Vertebral spacer and vertebral spacer kit

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Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5376121A (en) * 1991-08-06 1994-12-27 Techmedica, Inc. Dual constraint elbow prosthesis
US20080208344A1 (en) * 2007-02-06 2008-08-28 Kilpela Thomas S Intervertebral Implant Devices and Methods for Insertion Thereof
US20200000499A1 (en) * 2017-03-16 2020-01-02 Olympus Terumo Biomaterials Corp. Vertebral spacer and vertebral spacer kit
US20190083146A1 (en) * 2017-09-15 2019-03-21 Choice Spine, Lp Laminoplasty Hinges

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USD1028237S1 (en) * 2021-05-04 2024-05-21 M3 Health Indústria E Comércio De Produtos Médicos, Odontológicos E Correlatos S.A. Dental implant applied to cranial fossa and condylar plate
USD1028238S1 (en) * 2021-05-17 2024-05-21 M3 Health Industria E Comércio De Produtos Médicos, Odontológicos E Correlatos S.A. Dental implant applied to cranial fossa and minimally invasive plate
USD1028239S1 (en) * 2021-07-31 2024-05-21 M3 Health Industria E Comércio De Produtos Médicos, Odontológicos E Correlatos S.A. Dental implant applied to cranial fossa and condylar plate

Also Published As

Publication number Publication date
US20210358526A1 (en) 2021-11-18
US20200402547A1 (en) 2020-12-24
CN112116930A (en) 2020-12-22
US11107507B2 (en) 2021-08-31
CN112116930B (en) 2024-06-14

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