USD413109S - Processor package cover plate - Google Patents
Processor package cover plate Download PDFInfo
- Publication number
- USD413109S USD413109S US29/062,471 US6247196F USD413109S US D413109 S USD413109 S US D413109S US 6247196 F US6247196 F US 6247196F US D413109 S USD413109 S US D413109S
- Authority
- US
- United States
- Prior art keywords
- cover plate
- processor package
- package cover
- processor
- ornamental design
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Description
FIG. 1 is a perspective view of a processor package cover plate on a processor package including an indented area on the surface of the processor package cover plate;
FIG. 2-4 are front, top, and back views, respectively, of the processor package cover plate on the processor package;
FIG. 5-7 are right, left, and bottom views, respectively, of the processor package cover plate on the processor package; and,
FIG. 8 is a cross sectional view of the processor package cover plate on the processor package taken along line 8--8 of FIG. 2.
The processor package is shown in broken lines in the views for illustrative purposes only and forms no part of the claimed design.
Claims (1)
- The ornamental design for a processor package cover plate, as shown and described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US29/062,471 USD413109S (en) | 1996-11-15 | 1996-11-15 | Processor package cover plate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US29/062,471 USD413109S (en) | 1996-11-15 | 1996-11-15 | Processor package cover plate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| USD413109S true USD413109S (en) | 1999-08-24 |
Family
ID=71725226
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US29/062,471 Expired - Lifetime USD413109S (en) | 1996-11-15 | 1996-11-15 | Processor package cover plate |
Country Status (1)
| Country | Link |
|---|---|
| US (1) | USD413109S (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USD753120S1 (en) * | 2013-12-04 | 2016-04-05 | Cisco Technology, Inc. | Electrical equipment housing |
| USD866560S1 (en) * | 2018-01-12 | 2019-11-12 | Intel Corporation | Peripheral component interconnect card panel |
-
1996
- 1996-11-15 US US29/062,471 patent/USD413109S/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USD753120S1 (en) * | 2013-12-04 | 2016-04-05 | Cisco Technology, Inc. | Electrical equipment housing |
| USD866560S1 (en) * | 2018-01-12 | 2019-11-12 | Intel Corporation | Peripheral component interconnect card panel |
| USD876443S1 (en) * | 2018-01-12 | 2020-02-25 | Intel Corporation | Peripheral component interconnect card panel set |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |