USB550693I5 - - Google Patents
Info
- Publication number
- USB550693I5 USB550693I5 US55069375A USB550693I5 US B550693 I5 USB550693 I5 US B550693I5 US 55069375 A US55069375 A US 55069375A US B550693 I5 USB550693 I5 US B550693I5
- Authority
- US
- United States
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US05/550,693 US3982194A (en) | 1975-02-18 | 1975-02-18 | Phase lock loop with delay circuits for relative digital decoding over a range of frequencies |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US05/550,693 US3982194A (en) | 1975-02-18 | 1975-02-18 | Phase lock loop with delay circuits for relative digital decoding over a range of frequencies |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| USB550693I5 true USB550693I5 (en:Method) | 1976-01-20 |
| US3982194A US3982194A (en) | 1976-09-21 |
Family
ID=24198222
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US05/550,693 Expired - Lifetime US3982194A (en) | 1975-02-18 | 1975-02-18 | Phase lock loop with delay circuits for relative digital decoding over a range of frequencies |
Country Status (1)
| Country | Link |
|---|---|
| US (1) | US3982194A (en:Method) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2912406A1 (de) * | 1978-03-31 | 1979-10-18 | Citizen Watch Co Ltd | Frequenzteilersystem |
| US4320527A (en) * | 1978-08-18 | 1982-03-16 | Hitachi, Ltd. | Bit synchronizing system for pulse signal transmission |
| DE2906200C3 (de) * | 1979-02-17 | 1982-02-11 | Philips Patentverwaltung Gmbh, 2000 Hamburg | Synchronisieranordnung |
| US4365210A (en) * | 1980-06-26 | 1982-12-21 | Motorola, Inc. | Data and clock recovery system having a phase-locked-loop and which controls dynamic loop response of a data stream of unknown data format |
| US4574243A (en) * | 1984-01-03 | 1986-03-04 | Motorola, Inc. | Multiple frequency digital phase locked loop |
| JPS60200635A (ja) * | 1984-03-26 | 1985-10-11 | Victor Co Of Japan Ltd | デジタル信号復調装置のビツトクロツク信号発生装置 |
| GB2191068A (en) * | 1986-05-28 | 1987-12-02 | Marconi Instruments Ltd | Electrical apparatus for extracting clock signals |
| GB2352373B (en) * | 1999-06-11 | 2004-02-18 | Ibm | PLL substitution by time measurement |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3599110A (en) * | 1970-03-31 | 1971-08-10 | Ibm | Self-clocking system having a variable frequency oscillator locked to leading edge of data and clock |
| US3614635A (en) * | 1969-12-31 | 1971-10-19 | Ibm | Variable frequency control system and data standardizer |
| US3840821A (en) * | 1967-07-27 | 1974-10-08 | Sperry Rand Corp | Phase lock loop with sampling techniques for regenerating clock signal associated with data input signals |
-
1975
- 1975-02-18 US US05/550,693 patent/US3982194A/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3840821A (en) * | 1967-07-27 | 1974-10-08 | Sperry Rand Corp | Phase lock loop with sampling techniques for regenerating clock signal associated with data input signals |
| US3614635A (en) * | 1969-12-31 | 1971-10-19 | Ibm | Variable frequency control system and data standardizer |
| US3599110A (en) * | 1970-03-31 | 1971-08-10 | Ibm | Self-clocking system having a variable frequency oscillator locked to leading edge of data and clock |
Also Published As
| Publication number | Publication date |
|---|---|
| US3982194A (en) | 1976-09-21 |