US9865625B2 - Array substrate and method of manufacturing the same, and display device - Google Patents
Array substrate and method of manufacturing the same, and display device Download PDFInfo
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- US9865625B2 US9865625B2 US14/801,531 US201514801531A US9865625B2 US 9865625 B2 US9865625 B2 US 9865625B2 US 201514801531 A US201514801531 A US 201514801531A US 9865625 B2 US9865625 B2 US 9865625B2
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 238000000034 method Methods 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 5
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 3
- 230000002411 adverse Effects 0.000 abstract description 8
- 230000008054 signal transmission Effects 0.000 abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
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- 239000011295 pitch Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
Definitions
- Embodiments of the present disclosure generally relate to the technical field of semiconductor technologies, and particularly, to an array substrate and a method of manufacturing the same, and a display device comprising the array substrate.
- FIG. 1 a and FIG. 1 b where FIG. 1 b is a cross sectional view taken along an A-A′ direction in FIG. 1 a , the source signal lines 2 and the gate signal lines 1 cross and overlap with each other. Since the underlying gate signal line 1 has a thickness, the upper source signal line 2 span over the gate signal line 1 like a bridge at the overlapping region, thereby a step difference is present on the source signal line 2 within the overlapping region, that is, there is a distance difference h between the highest portion and the lowest portion of the source signal line 2 .
- embodiments of the present disclosure provide an array substrate and a method of manufacturing the same, and a display device comprising the array substrate, which are intended to solve the problem in prior arts that the signal lines will be easily broken within the overlapping region and thus transmission of signal is adversely affected.
- an embodiment of the present disclosure provides an array substrate, comprising a base substrate, first signal lines and second signal lines arranged in different layers on the base substrate, and an insulating layer between the first signal lines and the second signal lines;
- the second signal lines are located above the first signal lines, and the first signal lines and the second signal lines extend in different directions so as to form overlapping regions therebetween;
- connecting portions are further provided between the insulating layer and a layer where the second signal lines are located, and at least cover one of the overlapping regions;
- the connecting portions are electrically conductive, and the connecting portions directly contact the second signal lines.
- the above array substrate provided according to embodiments of the present disclosure may further comprise pixel electrodes between the insulating layer and the layer where the second signal lines are located, the connecting portions are made of the same material and provided in the same layer as the pixel electrodes.
- the thickness of the connecting portions is the same as that of the pixel electrodes.
- the material of the pixel electrodes is indium tin oxide.
- the first signal lines may include source signal lines, and the second signal lines may include gate signal lines; or, the first signal lines may include gate signal lines, and the second signal lines may include source signal lines.
- the first signal lines further comprise a common electrode line, or the second signal lines further comprise the common electrode line.
- one of the connecting portions is provided to correspond to one of the overlapping regions, and the connecting portions are electrically insulated from each other.
- an embodiment of the present disclosure further provides a method of manufacturing an array substrate, comprising steps of: forming a pattern of first signal lines on a base substrate; forming an insulating layer on the first signal lines; and forming a pattern of second signal lines on the insulating layer, the first signal lines and the second signal lines extending in different directions so as to form overlapping regions therebetween; wherein after forming the insulating layer and before forming the pattern of the second signal lines, the method further comprises a step of: forming a pattern of connecting portions on the insulating layer to at least cover one of the overlapping regions, the connecting portions being electrically conductive and directly contacting the second signal lines.
- the step of forming the pattern of the connecting portions may include:
- an embodiment of the present disclosure further provides a display device, comprising the array substrate provide according to any one of the embodiments of the present disclosure.
- the connecting portion is provided within the overlapping region between the first signal line and the second signal line, is electrically conductive and directly contacts the second signal line, thus even when the upper second signal line is broken due to the large step difference within the overlapping region between the first signal line and the second signal line, the connecting portion electrically connected with the broken second signal line can still electrically connect and conduct the broken second signal line, thereby avoiding transmission of signal from being adversely affected by the broken signal line within the overlapping region.
- FIG. 1 a is a schematic structural top view of an existing array substrate
- FIG. 1 b is a schematic structural cross-sectional view of the array substrate taken along an A-A′ direction shown in FIG. 1 a;
- FIG. 2 a is a schematic structural top view of an array substrate provided according to one exemplary embodiment of the present disclosure
- FIG. 2 b is a schematic structural cross-sectional view of the array substrate taken along a B-B′ direction shown in FIG. 2 a;
- FIG. 3 a is a schematic structural top view of an array substrate in a liquid crystal display provided according to another exemplary embodiment of the present disclosure.
- FIG. 3 b is a schematic structural cross-sectional view of the array substrate taken along a C-C′ direction shown in FIG. 3 a.
- An array substrate provided according to one exemplary embodiment of the present disclosure, as shown in FIG. 2 a and FIG. 2 b , comprises a base substrate 10 , first signal lines 11 and second signal lines 13 arranged in different layers on the base substrate 10 , and an insulating layer 12 between the first signal lines 11 and the second signal lines 13 ; wherein the second signal lines 13 are located above the first signal lines 11 , and the first signal lines 11 and the second signal lines 13 extend in different directions so as to form overlapping regions therebetween; connecting portions 14 are further provided between the insulating layer 12 and a layer where the second signal lines 13 are located, and cover at least one of the overlapping regions; and the connecting portions 14 are electrically conductive, and directly contact the second signal lines 13 .
- the connecting portion is provided to at least cover the overlapping region between the first signal line and the second signal line, that is, the connecting portion at least overlaps with the corresponding overlapping region.
- This connecting portion is electrically conductive and directly contacts the second signal line, thus even when the upper second signal line is broken due to the large step difference within the overlapping region between the first signal line and the second signal line, the connecting portion electrically connected with the broken second signal line can still function to electrically connect and conduct the broken second signal line, thereby avoiding transmission of signal from being adversely affected by the broken signal line within the overlapping region.
- the connecting portion may be formed at least within a region where the signal line is easily broken due to step difference, for example, within a region corresponding to a step of the signal line, so that when the signal line is broken in the region, the connecting portion electrically connected with the signal line can still electrically connect and conduct the signal line.
- the thickness of the photoresist layer can be reduced within a region where the step difference of second signal lines is formed, thereby reducing difficulty of peeling off the photoresist located within the region where the step difference is formed when forming the second signal lines, and thus reducing the breaking problem of the second signal lines due to large difficulty in peeling off the photoresist layer.
- the connecting portion may has a circular, elliptic, rectangular or other irregular shape, which is not limited herein.
- the above array substrate may be any array substrate which has first signal lines and second signal lines insulated from each other and having overlapping regions therebetween, for example, an array substrate of a liquid crystal display panel having source signal lines and gate signal lines (which are respectively the first signal lines and the second signal lines), an array substrate of a mutual capacitance touch panel having touch drive lines and drive sensing lines (which are respectively the first signal lines and the second signal lines), or the like, which is not limited herein.
- the connecting portions may be made of metal material, transparent conductive oxide material or other conductive materials, which is not limited herein.
- the above array substrate provided according to embodiments of the present disclosure when the above array substrate provided according to embodiments of the present disclosure is applied in a crystal display panel, the above array substrate provided according to embodiments of the present disclosure may further comprises pixel electrodes between the insulating layer and the layer where the second signal lines are located, the connecting portions are made of the same material and provided in the same layer as the pixel electrodes.
- the connecting portions and pixel electrodes may be manufactured in the same layer, no new manufacturing process is added, and it only needs to modify patterns of corresponding film layers, thereby simplifying process steps, saving production cost, and improving production efficiency.
- the thickness of the connecting portions may be the same as that of the pixel electrodes.
- the material of the pixel electrodes may be indium tin oxide, which is not limited herein.
- the first signal lines include source signal lines and the second signal lines include gate signal lines, that is, the gate signal lines are located above the source signal lines; or the first signal lines include gate signal lines, and the second signal lines include source signal lines, that is, the source signal lines are located above the gate signal lines.
- the first signal lines may further comprise a common electrode line, that is, the common electrode line and the source signal lines are arranged in the same layer, and connecting portions are also provided within overlapping regions between the common electrode line and the gate signal lines; or the second signal lines further comprise the common electrode line, that is, the common electrode line and the gate signal lines are arranged in the same layer, and connecting portions are also provided within overlapping regions between the common electrode line and the source signal lines.
- the array substrate applied in the crystal display panel comprises gate signal lines 111 and a common electrode line 112 arranged in the same layer, a gate insulating layer 121 , connecting portions 14 and pixel electrodes 15 arranged in the same layer, source signal lines 131 and a source insulating layer 16 , all of which are arranged on a base substrate 10 in order.
- Overlapping regions between the common electrode line 112 and the source signal lines 131 extending in different directions, and overlapping regions between the gate signal lines 111 and the source signal lines 131 extending in different directions are covered by the connecting portions 14 respectively.
- the connecting portions not only the probability that the source signal lines are to be broken within regions where the step difference is present can be reduced, but also the connecting portions can still electrically connect and conduct the source signal lines even when the source signal lines are broken, thereby avoiding transmission of signal from being adversely affected by the broken source signal lines.
- an embodiment of the present disclosure further provides a method of manufacturing an array substrate, comprising steps of: forming a pattern of first signal lines on a base substrate; forming an insulating layer on the first signal lines; and forming a pattern of second signal lines on the insulating layer; the first signal lines and the second signal lines extend in different directions so as to form overlapping regions therebetween; wherein after forming the insulating layer and before forming the pattern of the second signal lines, the method further comprises forming a pattern of connecting portions on the insulating layer to at least cover one of the overlapping regions, the connecting portions being electrically conductive.
- the connecting portion is provided within the overlapping region between the first signal line and the second signal line, is electrically conductive, thus even when the upper second signal line is broken due to the large step difference within the overlapping region between the first signal line and the second signal line, the connecting portion electrically connected with the broken second signal line can still electrically connect and conduct the broken second signal line, thereby avoiding transmission of signal from being adversely affected by the broken signal line within the overlapping region.
- the thickness of the photoresist layer can be reduced within a region where the step difference of second signal lines is formed, thereby reducing difficulty of peeling off the photoresist located within the region where the step difference is formed when forming the second signal lines, and thus reducing the breaking problem of the second signal lines due to large difficulty in peeling off the photoresist layer.
- the step of forming the pattern of the connecting portions may comprise: forming a conductive layer on the insulating layer, and forming a pattern including pixel electrodes and the connecting portions in the conductive layer by performing a patterning process one time.
- an embodiment of the present disclosure further provides a display device, comprising the above array substrate provided according to embodiments of the present disclosure.
- the display device may be display panel, a mobile phone, a tablet computer, a TV, a display, a notebook computer, a digital photo frame, a navigator, or any other products or components having a display function. Implementation of the display device may be achieved with reference to the above embodiments of the display panel, and the same parts will not be repeatedly described.
- the display panel provided according to the embodiments of present disclosure may be a Liquid Crystal Display (LCD) panel, or an Organic Light Emitting Diode (OLED) display panel, which will not be limited here.
- LCD Liquid Crystal Display
- OLED Organic Light Emitting Diode
- the connecting portion is provided within the overlapping region between the first signal line and the second signal line, is electrically conductive and directly contacts the second signal line, thus even when the upper second signal line is broken due to the large step difference within the overlapping region between the first signal line and the second signal line, the connecting portion electrically connected with the broken second signal line can still electrically connect and conduct the broken second signal line, thereby avoiding transmission of signal from being adversely affected by the broken signal line within the overlapping region.
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Abstract
The present disclosure provides an array substrate and a method of manufacturing the same, and a display device. TA connecting portion is provided within the overlapping region between the first signal line and the second signal line, is electrically conductive and directly contacts the second signal line. Thus, even when the upper second signal line is broken due to the large step difference within the overlapping region between the first signal line and the second signal line, the connecting portion electrically connected with the broken second signal line can still electrically connect and conduct the broken second signal line, thereby avoiding transmission of signal from being adversely affected by the broken signal line within the overlapping region.
Description
This application claims the benefit of Chinese Patent Application No. 201410857208.5 filed on Dec. 31, 2014 in the State Intellectual Property Office of China, the whole disclosure of which is incorporated herein by reference.
Field of the Invention
Embodiments of the present disclosure generally relate to the technical field of semiconductor technologies, and particularly, to an array substrate and a method of manufacturing the same, and a display device comprising the array substrate.
Description of the Related Art
With the continuous development of display technologies, requirements to resolution (Pixel per inch, PPI) and pixel aperture ratio of display products become ever higher. Thus, pixel sizes and pixel pitches on the array substrate in a display panel become smaller, and thereupon, signal lines become thinner.
For example, in a crystal display panel where source signal lines and gate signal lines on the array substrate are thinner, as shown in FIG. 1a and FIG. 1b , where FIG. 1b is a cross sectional view taken along an A-A′ direction in FIG. 1a , the source signal lines 2 and the gate signal lines 1 cross and overlap with each other. Since the underlying gate signal line 1 has a thickness, the upper source signal line 2 span over the gate signal line 1 like a bridge at the overlapping region, thereby a step difference is present on the source signal line 2 within the overlapping region, that is, there is a distance difference h between the highest portion and the lowest portion of the source signal line 2. Generally, the larger the thickness of the gate signal line 1 below the source signal line 2 is, the larger the step difference present on source signal line 2 within the overlapping region is. Due to the presence of the step difference, the source signal line 2 will be easily broken within a region where the step difference is larger, adversely affecting signal transmission.
In view of the above, embodiments of the present disclosure provide an array substrate and a method of manufacturing the same, and a display device comprising the array substrate, which are intended to solve the problem in prior arts that the signal lines will be easily broken within the overlapping region and thus transmission of signal is adversely affected.
Thus, an embodiment of the present disclosure provides an array substrate, comprising a base substrate, first signal lines and second signal lines arranged in different layers on the base substrate, and an insulating layer between the first signal lines and the second signal lines;
the second signal lines are located above the first signal lines, and the first signal lines and the second signal lines extend in different directions so as to form overlapping regions therebetween;
connecting portions are further provided between the insulating layer and a layer where the second signal lines are located, and at least cover one of the overlapping regions; and
the connecting portions are electrically conductive, and the connecting portions directly contact the second signal lines.
In one example, the above array substrate provided according to embodiments of the present disclosure may further comprise pixel electrodes between the insulating layer and the layer where the second signal lines are located, the connecting portions are made of the same material and provided in the same layer as the pixel electrodes.
In one example, in the above array substrate provided according to embodiments of the present disclosure, the thickness of the connecting portions is the same as that of the pixel electrodes.
In one example, in the above array substrate provided according to embodiments of the present disclosure, the material of the pixel electrodes is indium tin oxide.
In one example, in the above array substrate provided according to embodiments of the present disclosure, the first signal lines may include source signal lines, and the second signal lines may include gate signal lines; or, the first signal lines may include gate signal lines, and the second signal lines may include source signal lines.
In one example, in the above array substrate provided according to embodiments of the present disclosure, the first signal lines further comprise a common electrode line, or the second signal lines further comprise the common electrode line.
In one example, in the above array substrate provided according to embodiments of the present disclosure, one of the connecting portions is provided to correspond to one of the overlapping regions, and the connecting portions are electrically insulated from each other.
Correspondingly, an embodiment of the present disclosure further provides a method of manufacturing an array substrate, comprising steps of: forming a pattern of first signal lines on a base substrate; forming an insulating layer on the first signal lines; and forming a pattern of second signal lines on the insulating layer, the first signal lines and the second signal lines extending in different directions so as to form overlapping regions therebetween; wherein after forming the insulating layer and before forming the pattern of the second signal lines, the method further comprises a step of: forming a pattern of connecting portions on the insulating layer to at least cover one of the overlapping regions, the connecting portions being electrically conductive and directly contacting the second signal lines.
In one example, in the method provided according to the embodiment of the present disclosure, in order to simplify manufacturing process and reduce production cost, the step of forming the pattern of the connecting portions may include:
forming a conductive layer on the insulating layer; and
forming a pattern including pixel electrodes and the connecting portions in the conductive layer by performing a patterning process one time.
Correspondingly, an embodiment of the present disclosure further provides a display device, comprising the array substrate provide according to any one of the embodiments of the present disclosure.
With the above array substrate and method of manufacturing the same, and the display device provided according to embodiments of the present disclosure, the connecting portion is provided within the overlapping region between the first signal line and the second signal line, is electrically conductive and directly contacts the second signal line, thus even when the upper second signal line is broken due to the large step difference within the overlapping region between the first signal line and the second signal line, the connecting portion electrically connected with the broken second signal line can still electrically connect and conduct the broken second signal line, thereby avoiding transmission of signal from being adversely affected by the broken signal line within the overlapping region.
Exemplary embodiments of the present invention will be described hereinafter in detail with reference to the attached drawings, wherein the like reference numbers refer to the like elements. In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawings.
Sizes and shapes of parts shown in the drawings do not indicate real proportion of the array substrate, but are only intended to schematically illustrate the present disclosure.
An array substrate provided according to one exemplary embodiment of the present disclosure, as shown in FIG. 2a and FIG. 2b , comprises a base substrate 10, first signal lines 11 and second signal lines 13 arranged in different layers on the base substrate 10, and an insulating layer 12 between the first signal lines 11 and the second signal lines 13; wherein the second signal lines 13 are located above the first signal lines 11, and the first signal lines 11 and the second signal lines 13 extend in different directions so as to form overlapping regions therebetween; connecting portions 14 are further provided between the insulating layer 12 and a layer where the second signal lines 13 are located, and cover at least one of the overlapping regions; and the connecting portions 14 are electrically conductive, and directly contact the second signal lines 13.
With the above array substrate provided according to embodiments of the present disclosure, the connecting portion is provided to at least cover the overlapping region between the first signal line and the second signal line, that is, the connecting portion at least overlaps with the corresponding overlapping region. This connecting portion is electrically conductive and directly contacts the second signal line, thus even when the upper second signal line is broken due to the large step difference within the overlapping region between the first signal line and the second signal line, the connecting portion electrically connected with the broken second signal line can still function to electrically connect and conduct the broken second signal line, thereby avoiding transmission of signal from being adversely affected by the broken signal line within the overlapping region. Alternatively, the connecting portion may be formed at least within a region where the signal line is easily broken due to step difference, for example, within a region corresponding to a step of the signal line, so that when the signal line is broken in the region, the connecting portion electrically connected with the signal line can still electrically connect and conduct the signal line.
Further, when patterning the second signal lines during manufacturing the above array substrate, since a distance between a surface of a photoresist layer covering over the second signal lines and the base substrate is constant, that is, the thickness of the photoresist layer is small within a region where the distance between a surface of the second signal lines and the base substrate is large, and is large within a region where the distance between the surface of the second signal lines and the base substrate is small, and since the connecting portions are arranged between the insulating layer and the second signal lines and at least cover the overlapping regions, the thickness of the photoresist layer can be reduced within a region where the step difference of second signal lines is formed, thereby reducing difficulty of peeling off the photoresist located within the region where the step difference is formed when forming the second signal lines, and thus reducing the breaking problem of the second signal lines due to large difficulty in peeling off the photoresist layer.
Specifically, in the above array substrate provided according to embodiments of the present disclosure, the connecting portion may has a circular, elliptic, rectangular or other irregular shape, which is not limited herein.
It is noted that the above array substrate provided according to embodiments of the present disclosure may be any array substrate which has first signal lines and second signal lines insulated from each other and having overlapping regions therebetween, for example, an array substrate of a liquid crystal display panel having source signal lines and gate signal lines (which are respectively the first signal lines and the second signal lines), an array substrate of a mutual capacitance touch panel having touch drive lines and drive sensing lines (which are respectively the first signal lines and the second signal lines), or the like, which is not limited herein.
Specifically, in the above array substrate provided according to embodiments of the present disclosure, the connecting portions may be made of metal material, transparent conductive oxide material or other conductive materials, which is not limited herein.
In one example, when the above array substrate provided according to embodiments of the present disclosure is applied in a crystal display panel, the above array substrate provided according to embodiments of the present disclosure may further comprises pixel electrodes between the insulating layer and the layer where the second signal lines are located, the connecting portions are made of the same material and provided in the same layer as the pixel electrodes.
As such, during manufacturing the array substrate, the connecting portions and pixel electrodes may be manufactured in the same layer, no new manufacturing process is added, and it only needs to modify patterns of corresponding film layers, thereby simplifying process steps, saving production cost, and improving production efficiency.
In one example, in the above array substrate provided according to embodiments of the present disclosure, the thickness of the connecting portions may be the same as that of the pixel electrodes.
In one example, in the above array substrate provided according to embodiments of the present disclosure, the material of the pixel electrodes may be indium tin oxide, which is not limited herein.
Further, when the above array substrate provided according to embodiments of the present disclosure is applied in the liquid crystal display panel, the first signal lines include source signal lines and the second signal lines include gate signal lines, that is, the gate signal lines are located above the source signal lines; or the first signal lines include gate signal lines, and the second signal lines include source signal lines, that is, the source signal lines are located above the gate signal lines.
Further, in the above array substrate provided according to embodiments of the present disclosure, the first signal lines may further comprise a common electrode line, that is, the common electrode line and the source signal lines are arranged in the same layer, and connecting portions are also provided within overlapping regions between the common electrode line and the gate signal lines; or the second signal lines further comprise the common electrode line, that is, the common electrode line and the gate signal lines are arranged in the same layer, and connecting portions are also provided within overlapping regions between the common electrode line and the source signal lines.
The above array substrate provided according to embodiments of the present disclosure will be illustrated with reference to a specific example. As shown in FIG. 3a and FIG. 3b , the array substrate applied in the crystal display panel comprises gate signal lines 111 and a common electrode line 112 arranged in the same layer, a gate insulating layer 121, connecting portions 14 and pixel electrodes 15 arranged in the same layer, source signal lines 131 and a source insulating layer 16, all of which are arranged on a base substrate 10 in order. Overlapping regions between the common electrode line 112 and the source signal lines 131 extending in different directions, and overlapping regions between the gate signal lines 111 and the source signal lines 131 extending in different directions are covered by the connecting portions 14 respectively. As such, with the connecting portions, not only the probability that the source signal lines are to be broken within regions where the step difference is present can be reduced, but also the connecting portions can still electrically connect and conduct the source signal lines even when the source signal lines are broken, thereby avoiding transmission of signal from being adversely affected by the broken source signal lines.
Based on the same inventive concept, an embodiment of the present disclosure further provides a method of manufacturing an array substrate, comprising steps of: forming a pattern of first signal lines on a base substrate; forming an insulating layer on the first signal lines; and forming a pattern of second signal lines on the insulating layer; the first signal lines and the second signal lines extend in different directions so as to form overlapping regions therebetween; wherein after forming the insulating layer and before forming the pattern of the second signal lines, the method further comprises forming a pattern of connecting portions on the insulating layer to at least cover one of the overlapping regions, the connecting portions being electrically conductive.
In the above method provided according to the embodiment of the present disclosure, the connecting portion is provided within the overlapping region between the first signal line and the second signal line, is electrically conductive, thus even when the upper second signal line is broken due to the large step difference within the overlapping region between the first signal line and the second signal line, the connecting portion electrically connected with the broken second signal line can still electrically connect and conduct the broken second signal line, thereby avoiding transmission of signal from being adversely affected by the broken signal line within the overlapping region. Further, when patterning the second signal lines during manufacturing the above array substrate, since a distance between a surface of a photoresist layer covering over the second signal lines and the base substrate is constant, that is, the thickness of the photoresist layer is small within a region where the distance between a surface of the second signal lines and the base substrate is large, and is large within a region where the distance between the surface of the second signal lines and the base substrate is small, and since the connecting portions are arranged between the insulating layer and the second signal lines and at least cover the overlapping regions, the thickness of the photoresist layer can be reduced within a region where the step difference of second signal lines is formed, thereby reducing difficulty of peeling off the photoresist located within the region where the step difference is formed when forming the second signal lines, and thus reducing the breaking problem of the second signal lines due to large difficulty in peeling off the photoresist layer.
In one example, in the above method provided according to the embodiment of the present disclosure, in order to simplify manufacturing process, the step of forming the pattern of the connecting portions may comprise: forming a conductive layer on the insulating layer, and forming a pattern including pixel electrodes and the connecting portions in the conductive layer by performing a patterning process one time. As such, no new manufacturing process is added, and it only needs to modify patterns of corresponding film layers, thereby simplifying process steps, saving production cost, and improving production efficiency.
Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, comprising the above array substrate provided according to embodiments of the present disclosure. The display device may be display panel, a mobile phone, a tablet computer, a TV, a display, a notebook computer, a digital photo frame, a navigator, or any other products or components having a display function. Implementation of the display device may be achieved with reference to the above embodiments of the display panel, and the same parts will not be repeatedly described.
Specifically, the display panel provided according to the embodiments of present disclosure may be a Liquid Crystal Display (LCD) panel, or an Organic Light Emitting Diode (OLED) display panel, which will not be limited here. When implemented in practice, other necessary components of the display panel would be understood by those skilled in the art, and will not be repeatedly described and are not intended to limit the present disclosure.
With the above array substrate and the method of manufacturing the same, and the display device provided according to embodiments of the present disclosure, the connecting portion is provided within the overlapping region between the first signal line and the second signal line, is electrically conductive and directly contacts the second signal line, thus even when the upper second signal line is broken due to the large step difference within the overlapping region between the first signal line and the second signal line, the connecting portion electrically connected with the broken second signal line can still electrically connect and conduct the broken second signal line, thereby avoiding transmission of signal from being adversely affected by the broken signal line within the overlapping region.
Although several exemplary embodiments of the present disclosure have been shown and described, it would be appreciated by those skilled in the art that various changes or modifications may be made in these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined in the claims and their equivalents.
Claims (12)
1. An array substrate, comprising a base substrate, first signal lines and second signal lines arranged in different layers on the base substrate, and an insulating layer between the first signal lines and the second signal lines; wherein
the second signal lines are located above the first signal lines, and the first signal lines and the second signal lines extend in different directions so as to form overlapping regions therebetween;
electrically conductive connecting portions are further provided between the insulating layer and a layer where the second signal lines are located, and each only cover one of the overlapping regions; and
the connecting portions electrically contact only the corresponding second signal lines only within the overlapping regions and only extend within regions corresponding to the overlapping regions, the connecting portions located within the overlapping regions formed by one of the first signal lines and all of the second signal lines are electrically insulated from each other, and the connecting portions located within the overlapping regions formed by one of the second signal lines and all of the first signal lines are electrically insulated from each other.
2. The array substrate according to claim 1 , further comprising pixel electrodes between the insulating layer and the layer where the second signal lines are located; wherein the connecting portions are made of the same material and provided in the same layer as the pixel electrodes.
3. The array substrate according to claim 2 , wherein a thickness of the connecting portions is the same as that of the pixel electrodes.
4. The array substrate according to claim 3 , wherein
the first signal lines include source signal lines, and the second signal lines include gate signal lines; or
the first signal lines include gate signal lines, and the second signal lines include source signal lines.
5. The array substrate according to claim 2 , wherein the material of the pixel electrodes is indium tin oxide.
6. The array substrate according to claim 5 , wherein
the first signal lines include source signal lines, and the second signal lines include gate signal lines; or
the first signal lines include gate signal lines, and the second signal lines include source signal lines.
7. The array substrate according to claim 2 , wherein
the first signal lines include source signal lines, and the second signal lines include gate signal lines; or
the first signal lines include gate signal lines, and the second signal lines include source signal lines.
8. The array substrate according to claim 1 , wherein
the first signal lines include source signal lines, and the second signal lines include gate signal lines; or
the first signal lines include gate signal lines, and the second signal lines include source signal lines.
9. The array substrate according to claim 8 , wherein the first signal lines further comprise a common electrode line, or the second signal lines further comprise the common electrode line.
10. A display device, comprising the array substrate according to claim 1 .
11. A method of manufacturing an array substrate, comprising steps of:
forming a pattern of first signal lines on a base substrate;
forming an insulating layer on the first signal lines; and
forming a pattern of second signal lines on the insulating layer, the first signal lines and the second signal lines extending in different directions so as to form overlapping regions therebetween;
wherein after forming the insulating layer and before forming the pattern of the second signal lines, the method further comprises a step of:
forming a pattern of electrically conductive connecting portions on the insulating layer that at least cover one of the overlapping regions, such that the connecting portions electrically contact only the corresponding second signal lines only within the overlapping regions and only extend within regions corresponding to the overlapping regions, the connecting portions located within the overlapping regions formed by one of the first signal lines and all of the second signal lines are electrically insulated from each other, and the connecting portions located within the overlapping regions formed by one of the second signal lines and all of the first signal lines are electrically insulated from each other.
12. The method according to claim 11 , wherein the step of forming the pattern of the connecting portions comprises:
forming a conductive layer on the insulating layer; and
forming a pattern including pixel electrodes and the connecting portions in the conductive layer through one single patterning process.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410857208.5A CN104503178A (en) | 2014-12-31 | 2014-12-31 | Array substrate, manufacturing method thereof and display device |
| CN201410857208 | 2014-12-31 | ||
| CN201410857208.5 | 2014-12-31 |
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| US20160190162A1 US20160190162A1 (en) | 2016-06-30 |
| US9865625B2 true US9865625B2 (en) | 2018-01-09 |
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Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05119345A (en) | 1991-10-25 | 1993-05-18 | Nec Corp | Liquid crystal display device |
| US5287206A (en) | 1990-11-30 | 1994-02-15 | Sharp Kabushiki Kaisha | Active matrix display device |
| JPH0829805A (en) | 1994-07-20 | 1996-02-02 | Nec Corp | Active matrix substrate |
| US20030151711A1 (en) * | 1997-11-03 | 2003-08-14 | Jin-Tae Yuh | Liquid crystal display having a modified electrode array |
| CN101097320A (en) | 2006-06-29 | 2008-01-02 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and method of fabricating the same |
| CN102629573A (en) | 2011-07-11 | 2012-08-08 | 北京京东方光电科技有限公司 | Thin film transistor liquid crystal display array substrate and manufacturing method thereof |
| WO2012133158A1 (en) | 2011-03-30 | 2012-10-04 | シャープ株式会社 | Array substrate for liquid crystal panel and liquid crystal panel |
| CN103513482A (en) | 2013-10-25 | 2014-01-15 | 京东方科技集团股份有限公司 | Display device, array substrate and manufacture method of array substrate |
| US20140049455A1 (en) * | 2012-08-14 | 2014-02-20 | Samsung Display Co., Ltd. | Organic light emitting diode display |
| CN103605242A (en) | 2013-11-21 | 2014-02-26 | 合肥京东方光电科技有限公司 | Array substrate, method for manufacturing same and display device |
-
2014
- 2014-12-31 CN CN201410857208.5A patent/CN104503178A/en active Pending
-
2015
- 2015-07-16 US US14/801,531 patent/US9865625B2/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5287206A (en) | 1990-11-30 | 1994-02-15 | Sharp Kabushiki Kaisha | Active matrix display device |
| JPH05119345A (en) | 1991-10-25 | 1993-05-18 | Nec Corp | Liquid crystal display device |
| JPH0829805A (en) | 1994-07-20 | 1996-02-02 | Nec Corp | Active matrix substrate |
| US20030151711A1 (en) * | 1997-11-03 | 2003-08-14 | Jin-Tae Yuh | Liquid crystal display having a modified electrode array |
| CN101097320A (en) | 2006-06-29 | 2008-01-02 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and method of fabricating the same |
| US20080002125A1 (en) * | 2006-06-29 | 2008-01-03 | Lg Philips Lcd Co., Ltd. | Liquid crystal display device and method of fabricating the same |
| WO2012133158A1 (en) | 2011-03-30 | 2012-10-04 | シャープ株式会社 | Array substrate for liquid crystal panel and liquid crystal panel |
| CN102629573A (en) | 2011-07-11 | 2012-08-08 | 北京京东方光电科技有限公司 | Thin film transistor liquid crystal display array substrate and manufacturing method thereof |
| US20140049455A1 (en) * | 2012-08-14 | 2014-02-20 | Samsung Display Co., Ltd. | Organic light emitting diode display |
| CN103513482A (en) | 2013-10-25 | 2014-01-15 | 京东方科技集团股份有限公司 | Display device, array substrate and manufacture method of array substrate |
| CN103605242A (en) | 2013-11-21 | 2014-02-26 | 合肥京东方光电科技有限公司 | Array substrate, method for manufacturing same and display device |
Non-Patent Citations (5)
| Title |
|---|
| Chinese Rejection Decision, for Chinese Patent Application No. 201410857208.5, dated Sep. 26, 2017, 19 pages. |
| First Chinese Office Action (including English translation) dated Nov. 1, 2016, for corresponding Chinese Application No. 201410857208.5. |
| Fourth Chinese Office Action, for Chinese Patent Application No. 201410857208.5, dated Jul. 13, 2017, 13 pages. |
| Second Chinese Office Action, for Chinese Patent Application No. 201410857208.5, dated Mar. 17, 2017, 10 pages. |
| Third Chinese Office Action, for Chinese Patent Application No. 201410857208.5, dated May 22, 2017, 11 pages. |
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| US20160190162A1 (en) | 2016-06-30 |
| CN104503178A (en) | 2015-04-08 |
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