US9818642B2 - Method of forming inter-level dielectric structures on semiconductor devices - Google Patents
Method of forming inter-level dielectric structures on semiconductor devices Download PDFInfo
- Publication number
- US9818642B2 US9818642B2 US14/687,360 US201514687360A US9818642B2 US 9818642 B2 US9818642 B2 US 9818642B2 US 201514687360 A US201514687360 A US 201514687360A US 9818642 B2 US9818642 B2 US 9818642B2
- Authority
- US
- United States
- Prior art keywords
- conductor
- layer
- self
- supporting film
- air gap
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active, expires
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76874—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroless plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/7688—Filling of holes, grooves or trenches, e.g. vias, with conductive material by deposition over sacrificial masking layer, e.g. lift-off
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53276—Conductive materials containing carbon, e.g. fullerenes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (16)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/687,360 US9818642B2 (en) | 2015-04-15 | 2015-04-15 | Method of forming inter-level dielectric structures on semiconductor devices |
EP16165360.5A EP3082161B1 (en) | 2015-04-15 | 2016-04-14 | Method of forming inter-level dielectric structures on semiconductor devices |
US15/723,374 US10262893B2 (en) | 2015-04-15 | 2017-10-03 | Method of forming inter-level dielectric structures on semiconductor devices |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/687,360 US9818642B2 (en) | 2015-04-15 | 2015-04-15 | Method of forming inter-level dielectric structures on semiconductor devices |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/723,374 Division US10262893B2 (en) | 2015-04-15 | 2017-10-03 | Method of forming inter-level dielectric structures on semiconductor devices |
Publications (2)
Publication Number | Publication Date |
---|---|
US20160307791A1 US20160307791A1 (en) | 2016-10-20 |
US9818642B2 true US9818642B2 (en) | 2017-11-14 |
Family
ID=55755418
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/687,360 Active 2035-07-13 US9818642B2 (en) | 2015-04-15 | 2015-04-15 | Method of forming inter-level dielectric structures on semiconductor devices |
US15/723,374 Active 2035-04-26 US10262893B2 (en) | 2015-04-15 | 2017-10-03 | Method of forming inter-level dielectric structures on semiconductor devices |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/723,374 Active 2035-04-26 US10262893B2 (en) | 2015-04-15 | 2017-10-03 | Method of forming inter-level dielectric structures on semiconductor devices |
Country Status (2)
Country | Link |
---|---|
US (2) | US9818642B2 (en) |
EP (1) | EP3082161B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20180047616A1 (en) * | 2015-04-15 | 2018-02-15 | Nxp Usa Inc. | Method of forming inter-level dielectric structures on semiconductor devices |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10354955B2 (en) * | 2017-06-19 | 2019-07-16 | Qualcomm Incorporated | Graphene as interlayer dielectric |
EP3654372B1 (en) * | 2018-11-13 | 2021-04-21 | IMEC vzw | Method of forming an integrated circuit with airgaps and corresponding integrated circuit |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5324683A (en) | 1993-06-02 | 1994-06-28 | Motorola, Inc. | Method of forming a semiconductor structure having an air region |
US6307265B1 (en) | 1995-12-28 | 2001-10-23 | Kabushiki Kaisha Toshiba | Feasible, gas-dielectric interconnect process |
US6387818B1 (en) | 2000-07-21 | 2002-05-14 | Advanced Micro Devices, Inc. | Method of porous dielectric formation with anodic template |
US6423629B1 (en) | 2000-05-31 | 2002-07-23 | Kie Y. Ahn | Multilevel copper interconnects with low-k dielectrics and air gaps |
US6509623B2 (en) * | 2000-06-15 | 2003-01-21 | Newport Fab, Llc | Microelectronic air-gap structures and methods of forming the same |
US8742478B2 (en) | 2011-11-02 | 2014-06-03 | Samsung Electronics Co., Ltd. | Graphene transistor having air gap, hybrid transistor having the same, and methods of fabricating the same |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9818642B2 (en) * | 2015-04-15 | 2017-11-14 | Nxp Usa, Inc. | Method of forming inter-level dielectric structures on semiconductor devices |
-
2015
- 2015-04-15 US US14/687,360 patent/US9818642B2/en active Active
-
2016
- 2016-04-14 EP EP16165360.5A patent/EP3082161B1/en active Active
-
2017
- 2017-10-03 US US15/723,374 patent/US10262893B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5324683A (en) | 1993-06-02 | 1994-06-28 | Motorola, Inc. | Method of forming a semiconductor structure having an air region |
US6307265B1 (en) | 1995-12-28 | 2001-10-23 | Kabushiki Kaisha Toshiba | Feasible, gas-dielectric interconnect process |
US6423629B1 (en) | 2000-05-31 | 2002-07-23 | Kie Y. Ahn | Multilevel copper interconnects with low-k dielectrics and air gaps |
US6509623B2 (en) * | 2000-06-15 | 2003-01-21 | Newport Fab, Llc | Microelectronic air-gap structures and methods of forming the same |
US6387818B1 (en) | 2000-07-21 | 2002-05-14 | Advanced Micro Devices, Inc. | Method of porous dielectric formation with anodic template |
US8742478B2 (en) | 2011-11-02 | 2014-06-03 | Samsung Electronics Co., Ltd. | Graphene transistor having air gap, hybrid transistor having the same, and methods of fabricating the same |
Non-Patent Citations (15)
Title |
---|
"Breakthrough synthesis method to speed commercialization of graphene"; http://phys.org/news/2014-04-breakthrough-synthesis-method-commercialization-graphene.html#jCp, Apr. 6, 2014. |
"Graphene" from Wikipedia; http://en.wikipedia.org/wiki/Graphene; downloaded Jun. 29, 2017. |
Chandler, D., "A new way to make sheets of graphene, Technique might enable advances in display screens, solar cells, or other devices"; MIT News Office, May 23, 2014. |
Extended European Search Report dated Jul. 11, 2016 in EP Application No. 16165360.5. |
Frank, I.W., et al., "Mechanical properties of suspended graphene sheets"; http://www.lassp.cornell.edu/lassp-data/mceuen/homepage/Publications/JVSTB-Pushing-Graphene.pdf; 2007 American Vacuum Society, J. Vac. Sci. Technol. B 25(6), Nov./Dec. 2007. |
Frank, I.W., et al., "Mechanical properties of suspended graphene sheets"; http://www.lassp.cornell.edu/lassp—data/mceuen/homepage/Publications/JVSTB—Pushing—Graphene.pdf; 2007 American Vacuum Society, J. Vac. Sci. Technol. B 25(6), Nov./Dec. 2007. |
Gomez De Arco, L., et al., "Continuous, Highly Flexible, and Transparent Graphene Films by CVD for Organic Photovoltaics", ACS Nano Publications, 2010, 4 (5), pp. 2865-2873, doi: 10.1021/nn901587x; 2010 American Chemical Society. |
Johnson, D., "First Wafer-Scale, Single-Crystal, Monolayer Graphene Made in Bulk"; http://spectrum.ieee.org/nanoclast/serniconductors/rnaterials/singlecrystal-monolayer-graphene-produced-in-bulk-for-first-time; Apr. 4, 2014. |
Johnson, R. C., "Graphene wafers ready to fab carbon chips"; http://www.eetimes.com/document.asp?doc-id=1172918, EETimes Feb. 1, 2010. |
Johnson, R. C., "Graphene wafers ready to fab carbon chips"; http://www.eetimes.com/document.asp?doc—id=1172918, EETimes Feb. 1, 2010. |
Kim, "A role for graphene in silicon-based semiconductor devices", http://www.nature.com/nature/journal/v479/n7373/full/nature10680.html, Nature: International weekly journal of science, vol. 479, Issue 7373, Nov. 17, 2011, Figure 1. |
Kim, B., et al., "Three dimensional graphene foam based transparent conductive electrodes in GaN based blue light-emitting diodes", Applied Physics Letters, 2013, vol. 102, Issue 16, 161902 (2013); doi: 10.1063/1.4801763, Apr. 2013. |
Korczynski, "Air-gaps in Copper Interconnects for Logic", http://semimd.com/blog/2014/10/31/air-gaps-in-copper-interconnects-for-logic/, Oct. 31, 2014. |
Miao, X., et al., "High Efficiency Graphene solar Cells by Chemical Doping", Nano Letters Publications; May 3, 2012, 12 (6), pp. 2745-2750; doi: 10.1021/nl204414u; 2012 American Chemical Society. |
Monolayer Graphene on PET (4″ Wafer); http://www.graphenea.com/products/monolayer-graphene-on-pet-60-mm-x-40-mm, downloaded Jun. 29, 2017. |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20180047616A1 (en) * | 2015-04-15 | 2018-02-15 | Nxp Usa Inc. | Method of forming inter-level dielectric structures on semiconductor devices |
US10262893B2 (en) * | 2015-04-15 | 2019-04-16 | Nxp Usa, Inc. | Method of forming inter-level dielectric structures on semiconductor devices |
Also Published As
Publication number | Publication date |
---|---|
US20180047616A1 (en) | 2018-02-15 |
EP3082161A1 (en) | 2016-10-19 |
US10262893B2 (en) | 2019-04-16 |
US20160307791A1 (en) | 2016-10-20 |
EP3082161B1 (en) | 2018-06-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20240079266A1 (en) | Air gap spacer formation for nano-scale semiconductor devices | |
US8471343B2 (en) | Parasitic capacitance reduction in MOSFET by airgap ild | |
US7816231B2 (en) | Device structures including backside contacts, and methods for forming same | |
US8748308B2 (en) | Through wafer vias and method of making same | |
US10373905B2 (en) | Integrating metal-insulator-metal capacitors with air gap process flow | |
US7326642B2 (en) | Method of fabricating semiconductor device using low dielectric constant material film | |
US8518787B2 (en) | Through wafer vias and method of making same | |
US10290708B2 (en) | Field effect transistors and methods of forming same | |
CN105870102A (en) | Damascene structure and formation method of damascene structure | |
US9472512B1 (en) | Integrated circuits with contacts through a buried oxide layer and methods of producing the same | |
US10062748B1 (en) | Segmented guard-ring and chip edge seals | |
US10262893B2 (en) | Method of forming inter-level dielectric structures on semiconductor devices | |
US20210098292A1 (en) | Metallic interconnect structure | |
TWI525746B (en) | Semiconductor device with self-aligned interconnects | |
US10714389B2 (en) | Structure and method using metal spacer for insertion of variable wide line implantation in SADP/SAQP integration | |
US6277705B1 (en) | Method for fabricating an air-gap with a hard mask | |
KR20040052353A (en) | Fabricating method of semiconductor device | |
US6180507B1 (en) | Method of forming interconnections | |
US9202758B1 (en) | Method for manufacturing a contact for a semiconductor component and related structure | |
US9613906B2 (en) | Integrated circuits including modified liners and methods for fabricating the same | |
US8513780B2 (en) | Semiconductor device having inter-level dielectric layer with hole-sealing and method for manufacturing the same | |
US10381432B2 (en) | Advanced metal insulator metal capacitor | |
US6563221B1 (en) | Connection structures for integrated circuits and processes for their formation | |
US20130299993A1 (en) | Interconnection of semiconductor device and fabrication method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:REBER, DOUGLAS M.;SHROFF, MEHUL D.;REEL/FRAME:035415/0836 Effective date: 20150414 |
|
AS | Assignment |
Owner name: CITIBANK, N.A., AS NOTES COLLATERAL AGENT, NEW YORK Free format text: SUPPLEMENT TO IP SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:036284/0339 Effective date: 20150724 Owner name: CITIBANK, N.A., AS NOTES COLLATERAL AGENT, NEW YORK Free format text: SUPPLEMENT TO IP SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:036284/0363 Effective date: 20150724 Owner name: CITIBANK, N.A., AS NOTES COLLATERAL AGENT, NEW YORK Free format text: SUPPLEMENT TO IP SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:036284/0105 Effective date: 20150724 Owner name: CITIBANK, N.A., AS NOTES COLLATERAL AGENT, NEW YOR Free format text: SUPPLEMENT TO IP SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:036284/0105 Effective date: 20150724 Owner name: CITIBANK, N.A., AS NOTES COLLATERAL AGENT, NEW YOR Free format text: SUPPLEMENT TO IP SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:036284/0339 Effective date: 20150724 Owner name: CITIBANK, N.A., AS NOTES COLLATERAL AGENT, NEW YOR Free format text: SUPPLEMENT TO IP SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:036284/0363 Effective date: 20150724 |
|
AS | Assignment |
Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: PATENT RELEASE;ASSIGNOR:CITIBANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:037357/0859 Effective date: 20151207 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS;ASSIGNOR:CITIBANK, N.A.;REEL/FRAME:037565/0527 Effective date: 20151207 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS;ASSIGNOR:CITIBANK, N.A.;REEL/FRAME:037565/0510 Effective date: 20151207 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: SUPPLEMENT TO THE SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:039138/0001 Effective date: 20160525 |
|
AS | Assignment |
Owner name: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC., NETHERLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:040925/0001 Effective date: 20160912 Owner name: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC., NE Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:040925/0001 Effective date: 20160912 |
|
AS | Assignment |
Owner name: NXP B.V., NETHERLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:040928/0001 Effective date: 20160622 |
|
AS | Assignment |
Owner name: NXP USA, INC., TEXAS Free format text: CHANGE OF NAME;ASSIGNOR:FREESCALE SEMICONDUCTOR INC.;REEL/FRAME:040626/0683 Effective date: 20161107 |
|
AS | Assignment |
Owner name: NXP USA, INC., TEXAS Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME;ASSIGNOR:FREESCALE SEMICONDUCTOR INC.;REEL/FRAME:041414/0883 Effective date: 20161107 Owner name: NXP USA, INC., TEXAS Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016;ASSIGNORS:NXP SEMICONDUCTORS USA, INC. (MERGED INTO);FREESCALE SEMICONDUCTOR, INC. (UNDER);SIGNING DATES FROM 20161104 TO 20161107;REEL/FRAME:041414/0883 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: NXP B.V., NETHERLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:050744/0097 Effective date: 20190903 |
|
AS | Assignment |
Owner name: NXP B.V., NETHERLANDS Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVEAPPLICATION 11759915 AND REPLACE IT WITH APPLICATION11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITYINTEREST;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:052915/0001 Effective date: 20160622 |
|
AS | Assignment |
Owner name: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC., NETHERLANDS Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVEAPPLICATION 11759915 AND REPLACE IT WITH APPLICATION11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITYINTEREST;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:052917/0001 Effective date: 20160912 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |