US9589841B2 - Electronic package and fabrication method thereof - Google Patents

Electronic package and fabrication method thereof Download PDF

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Publication number
US9589841B2
US9589841B2 US14/981,364 US201514981364A US9589841B2 US 9589841 B2 US9589841 B2 US 9589841B2 US 201514981364 A US201514981364 A US 201514981364A US 9589841 B2 US9589841 B2 US 9589841B2
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packaging substrate
conductors
layer
insulating layer
packaging
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US20160240466A1 (en
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Yan-Heng Chen
Yi-Feng Chang
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Assigned to SILICONWARE PRECISION INDUSTRIES CO., LTD. reassignment SILICONWARE PRECISION INDUSTRIES CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHANG, YI-FENG, CHEN, YAN-HENG
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H01L21/78—
    • H01L21/4853—
    • H01L21/563—
    • H01L21/565—
    • H01L23/3114—
    • H01L23/3128—
    • H01L23/49811—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/016—Manufacture or treatment using moulds
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H01L21/568—
    • H01L2224/131—
    • H01L2224/16227—
    • H01L2224/32225—
    • H01L2224/73204—
    • H01L2224/81005—
    • H01L2224/83005—
    • H01L2224/92125—
    • H01L23/5389—
    • H01L2924/00014—
    • H01L2924/014—
    • H01L2924/15311—
    • H01L2924/3511—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07202—Connecting or disconnecting of bump connectors using auxiliary members
    • H10W72/07204—Connecting or disconnecting of bump connectors using auxiliary members using temporary auxiliary members, e.g. sacrificial coatings
    • H10W72/07207—Temporary substrates, e.g. removable substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07302—Connecting or disconnecting of die-attach connectors using an auxiliary member
    • H10W72/07304—Connecting or disconnecting of die-attach connectors using an auxiliary member the auxiliary member being temporary, e.g. a sacrificial coating
    • H10W72/07307—Connecting or disconnecting of die-attach connectors using an auxiliary member the auxiliary member being temporary, e.g. a sacrificial coating the auxiliary member being a temporary substrate, e.g. a removable substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the present invention relates to packaging technologies, and more particularly, to semiconductor packaging technologies.
  • PoP package on package
  • FO PoP fan out package on package
  • Such a packaging method allows merging of heterogeneous technologies in a system-in-package (SiP) so as to systematically integrate a plurality of electronic elements having different functions, such as a memory, a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), an image application processor and so on, and therefore is applicable to various thin type electronic products.
  • SiP system-in-package
  • FIG. 1 is a schematic cross-sectional view of a conventional semiconductor package 1 for a PoP structure.
  • the semiconductor package 1 includes a packaging substrate 10 having at least a circuit layer 101 and a semiconductor element 11 flip-chip bonded to the circuit layer 101 .
  • the semiconductor element 11 has an active surface 11 a with a plurality of electrode pads 110 and an inactive surface 11 b opposite to the active surface 11 a .
  • the electrode pads 110 of the semiconductor element 11 are electrically connected to the circuit layer 101 through a plurality of, for example, solder bumps 12 . Further, an underfill 13 is formed between the semiconductor element 11 and the circuit layer 101 for encapsulating the solder bumps 12 .
  • an encapsulant 14 is formed on the packaging substrate 10 to encapsulate the underfill 13 and the semiconductor element 11 , and a plurality of conductive through holes 17 are formed in the encapsulant 14 .
  • One ends of the conductive through holes 17 are exposed from the encapsulant 14 for mounting an electronic device such as an interposer or a packaging substrate (not shown).
  • the area of the encapsulant 14 is required to correspond to the area of the packaging substrate 10 .
  • the area of the packaging substrate 10 cannot be reduced, thus resulting in a very large width of the semiconductor package 1 and hindering miniaturization of the semiconductor package 1 .
  • the present invention provides an electronic package, which comprises: a packaging substrate having opposite first and second sides; an electronic element disposed on the first side of the packaging substrate; a plurality of conductors formed on the first side of the packaging substrate; an insulating layer encapsulating the packaging substrate, the electronic element and the conductors, wherein the second side of the packaging substrate is exposed from the insulating layer; and an RDL (Redistribution Layer) structure formed on the insulating layer and electrically connected to the conductors.
  • a packaging substrate having opposite first and second sides
  • an electronic element disposed on the first side of the packaging substrate
  • a plurality of conductors formed on the first side of the packaging substrate
  • an insulating layer encapsulating the packaging substrate, the electronic element and the conductors, wherein the second side of the packaging substrate is exposed from the insulating layer
  • an RDL Distribution Layer
  • the present invention further provides a method for fabricating an electronic package, which comprises the steps of: providing at least a packaging structure, wherein the packaging structure has a packaging substrate having opposite first and second sides, an electronic element disposed on the first side of the packaging substrate and a plurality of conductors formed on the first side of the packaging substrate; encapsulating the packaging structure with an insulating layer, wherein the insulating layer covers the packaging substrate; and forming an RDL structure on the insulating layer, wherein the RDL structure is electrically connected to the conductors.
  • the above-described method can further comprise forming a bonding layer on the RDL structure.
  • a metal frame can be disposed on an edge of the bonding layer.
  • the method can further comprise removing the bonding layer first and then performing a singulation process.
  • the above-described method can further comprise performing a singulation process.
  • each of the conductors can have a ball shape, a post shape or a stud shape.
  • the conductors can be formed at an outer periphery of the electronic element.
  • the RDL structure can have at least a dielectric layer and at least a circuit layer formed on the dielectric layer and directly electrically connected to the conductors.
  • the RDL structure can have at least a dielectric layer, at least a circuit layer formed on the dielectric layer, and a plurality of conductive vias formed in the insulating layer for electrically connecting the circuit layer and the conductors.
  • the second side of the packaging substrate can be exposed from the insulating layer, allowing a plurality of conductive elements to be formed thereon and electrically connected to the packaging substrate.
  • the conductors are formed first and then the packaging structure is encapsulated with the insulating layer in a manner that the insulating layer covers a side surface of the packaging substrate.
  • the invention replaces a conventional electronic device such as an interposer or a packaging substrate with the RDL structure.
  • the area of the insulating layer is not required to correspond to the area of the packaging substrate, thus allowing the area of the packaging substrate to be reduced according to the practical need so as to reduce the width of the electronic package and meet the miniaturization requirement.
  • FIG. 1 is a schematic cross-sectional view of a conventional semiconductor package
  • FIGS. 2A and 2F are schematic cross-sectional views showing a method for fabricating an electronic package according to the present invention, wherein FIG. 2C ′ show another embodiment of FIG. 2C .
  • FIGS. 2A to 2F are schematic cross-sectional views showing a method for fabricating an electronic package 2 according to the present invention.
  • the packaging structure 2 a has a packaging substrate 20 having a first side 20 a and a second side 20 b opposite to the first side 20 a , an electronic element 21 disposed on the first side 20 a of the packaging substrate 20 , and a plurality of conductors 27 formed on the first side 20 a of the packaging substrate 20 .
  • the packaging substrate 20 has a plurality of dielectric layers 200 and a plurality of circuit layers 201 formed on the dielectric layers 200 and electrically connected to the electronic element 21 and the conductors 27 . It should be noted that although only some circuit layers 201 on the first side 20 a of the packaging substrate 20 are shown in the drawings, the present invention is not limited thereto. For example, a plurality of circuit layers can be formed on the second side 20 b of the packaging substrate 20 and inside the packaging substrate 20 according to the practical need.
  • the electronic element 21 is an active element such as a semiconductor chip, a passive element such as a resistor, a capacitor or an inductor, or a combination thereof.
  • the electronic element 21 is a semiconductor chip having an active surface 21 a with a plurality of electrode pads 210 and an inactive surface 21 b opposite to the active surface 21 a .
  • the electronic element 21 is flip-chip disposed on the packaging substrate 20 , and the electrode pads 210 of the electronic element 21 are electrically connected to the circuit layers 201 through a plurality of solder bumps 22 . Further, an underfill 23 is formed between the electronic element 21 and the circuit layers 201 to encapsulate the solder bumps 22 .
  • Each of the conductors 27 can have a ball shape, a post shape or a stud shape.
  • the conductors 27 can be solder balls, copper posts, solder bumps, or studs formed by a wire bonder.
  • the carrier 30 is a circular substrate made of glass having a diameter of 12 inch or 300 mm.
  • a release layer 31 and an adhesive layer 32 are sequentially formed on the carrier 30 by coating, and the second side 20 b of the packaging substrate 20 is attached to the carrier 30 through the adhesive layer 22 .
  • an insulating layer 24 is formed on the carrier 30 to encapsulate the packaging structure 2 a.
  • the insulating layer 24 covers a side surface 20 c of the packaging substrate 20 that is adjacent to and connecting the first side 20 a and the second side 20 b of the packaging substrate 20 .
  • the insulating layer 24 can be made of an encapsulant such as an epoxy resin and formed by lamination or molding.
  • an RDL (Redistribution Layer) structure 25 is formed on the insulating layer 24 and electrically connected to the conductors 27 .
  • the RDL structure 25 has at least a dielectric layer 250 and at least a circuit layer 251 formed on the dielectric layer 251 and directly electrically connected to the conductors 27 .
  • the RDL structure 25 ′ further has a plurality of conductive vias 252 are formed in the insulating layer 24 for electrically connecting the circuit layer 251 and the conductors 27 .
  • the circuit layer 251 is made of copper, and the dielectric layer 250 is made of a photoresist material or polybenzoxazole (PBO).
  • a bonding layer 28 such as a tape is formed on the RDL structure 25 , and then the carrier 30 and the adhesive layer 32 are removed.
  • ultraviolet or laser light passes through the carrier 30 and irradiates the release layer 31 (made of a photosensitive material) so as to cause removal of the release layer 31 , thereby allowing removal of the carrier 30 .
  • a metal frame 29 such as an iron ring is disposed on an edge of the bonding layer 28 to prevent warping of the bonding layer 28 .
  • a plurality of conductive elements 26 such as solder balls are formed on the second side 20 b of the packaging substrate 20 for mounting another package or an electronic device such as a circuit board or an interposer.
  • the conductive elements 26 are electrically connected to the circuit layers 201 of the packaging substrate 20 .
  • a singulation process is performed along cutting paths S of FIG. 2E , with the metal frame 29 being removed. Further, the bonding layer 28 is removed from the RDL structure 25 . As such, an electronic package 2 is obtained.
  • the conductors 27 are formed on the packaging substrate 20 first and then the packaging structure 2 a is encapsulated with the insulating layer 24 in a manner that the insulating layer 24 covers the side surface 20 c of the packaging substrate 20 .
  • the area of the insulating layer 24 is required to correspond to the area of the carrier 30 instead of the packaging substrate 20 . Therefore, the area of the packaging substrate 20 can be reduced according to the practical need so as to reduce the width of the electronic package 2 and meet the miniaturization requirement.
  • the invention allows the packaging substrate 20 to be reduced according to the practical need so as to reduce the width of the electronic package 2 and meet the miniaturization requirement.
  • the present invention further provides an electronic package 2 , which has: a packaging substrate 20 having opposite first and second sides 20 a , 20 b ; an electronic element 21 disposed on the first side 20 a of the packaging substrate 20 ; a plurality of conductors 27 formed on the first side 20 a of the packaging substrate 20 ; an insulating layer 24 encapsulating the packaging substrate 20 , the electronic element 21 and the conductors 27 , wherein the second side 20 b of the packaging substrate 20 is exposed from the insulating layer 24 ; and an RDL structure 25 , 25 ′ formed on the insulating layer 24 and electrically connected to the conductors 27 .
  • the conductors 27 can be formed at an outer periphery of the electronic element 21 .
  • the conductors 27 can be metal posts.
  • the insulating layer 24 can cover the side surface 20 c of the packaging substrate 20 .
  • the RDL structure 25 has at least a dielectric layer 250 and at least a circuit layer 251 formed on the dielectric layer 250 and directly electrically connected to the conductors 27 .
  • the RDL structure 25 ′ has at least a dielectric layer 250 , at least a circuit layer 251 formed on the dielectric layer 250 , and a plurality of conductive vias 252 formed in the insulating layer 24 for electrically connecting the circuit layer 251 and the conductors 27 .
  • the electronic package 2 further has a plurality of conductive elements 26 formed on the second side 20 b of the packaging substrate 20 and electrically connected to the packaging substrate 20 .
  • the present invention forms the conductors first and then encapsulates the packaging structure with the insulating layer so as to allow the insulating layer to cover the side surface of the packaging substrate. Further, the invention replaces the conventional electronic device such as an interposer or a packaging substrate with the RDL structure. As such, the area of the insulating layer is not required to correspond to the area of the packaging substrate, and hence the area of the packaging substrate can be reduced according to the practical need so as to reduce the width of the electronic package and meet the miniaturization requirement.

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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)

Abstract

A method for fabricating an electronic package is provided, including the steps of: providing at least a packaging structure, wherein the packaging structure has a packaging substrate having opposite first and second sides, an electronic element disposed on the first side of the packaging substrate and a plurality of conductors formed on the first side of the packaging substrate; encapsulating the packaging structure with an insulating layer, wherein the insulating layer covers the packaging substrate; and forming an RDL (Redistribution Layer) structure on the insulating layer, wherein the RDL structure is electrically connected to the conductors. Therefore, the area of the insulating layer is not required to correspond to the area of the packaging substrate, thus allowing the area of the packaging substrate to be reduced according to the practical need so as to reduce the width of the electronic package.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS
This application claims under 35 U.S.C. §119(a) the benefit of Taiwanese Application No. 104104985, filed Feb. 13, 2015, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to packaging technologies, and more particularly, to semiconductor packaging technologies.
2. Description of Related Art
Along with the progress of semiconductor packaging technologies, various package types have been developed for semiconductor devices. To improve electrical performance and save space, a plurality of packages can be stacked to form a package on package (PoP) structure, for example, a fan out package on package (FO PoP) structure, thereby greatly increasing the I/O count and integrating integrated circuits having different functions. Such a packaging method allows merging of heterogeneous technologies in a system-in-package (SiP) so as to systematically integrate a plurality of electronic elements having different functions, such as a memory, a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), an image application processor and so on, and therefore is applicable to various thin type electronic products.
FIG. 1 is a schematic cross-sectional view of a conventional semiconductor package 1 for a PoP structure.
Referring to FIG. 1, the semiconductor package 1 includes a packaging substrate 10 having at least a circuit layer 101 and a semiconductor element 11 flip-chip bonded to the circuit layer 101.
The semiconductor element 11 has an active surface 11 a with a plurality of electrode pads 110 and an inactive surface 11 b opposite to the active surface 11 a. The electrode pads 110 of the semiconductor element 11 are electrically connected to the circuit layer 101 through a plurality of, for example, solder bumps 12. Further, an underfill 13 is formed between the semiconductor element 11 and the circuit layer 101 for encapsulating the solder bumps 12.
Furthermore, an encapsulant 14 is formed on the packaging substrate 10 to encapsulate the underfill 13 and the semiconductor element 11, and a plurality of conductive through holes 17 are formed in the encapsulant 14. One ends of the conductive through holes 17 are exposed from the encapsulant 14 for mounting an electronic device such as an interposer or a packaging substrate (not shown).
However, during formation of the encapsulant 14, since the packaging substrate 10 serves as a carrier, the area of the encapsulant 14 is required to correspond to the area of the packaging substrate 10. As such, the area of the packaging substrate 10 cannot be reduced, thus resulting in a very large width of the semiconductor package 1 and hindering miniaturization of the semiconductor package 1.
Therefore, how to overcome the above-described drawbacks has become critical.
SUMMARY OF THE INVENTION
In view of the above-described drawbacks, the present invention provides an electronic package, which comprises: a packaging substrate having opposite first and second sides; an electronic element disposed on the first side of the packaging substrate; a plurality of conductors formed on the first side of the packaging substrate; an insulating layer encapsulating the packaging substrate, the electronic element and the conductors, wherein the second side of the packaging substrate is exposed from the insulating layer; and an RDL (Redistribution Layer) structure formed on the insulating layer and electrically connected to the conductors.
The present invention further provides a method for fabricating an electronic package, which comprises the steps of: providing at least a packaging structure, wherein the packaging structure has a packaging substrate having opposite first and second sides, an electronic element disposed on the first side of the packaging substrate and a plurality of conductors formed on the first side of the packaging substrate; encapsulating the packaging structure with an insulating layer, wherein the insulating layer covers the packaging substrate; and forming an RDL structure on the insulating layer, wherein the RDL structure is electrically connected to the conductors.
The above-described method can further comprise forming a bonding layer on the RDL structure. A metal frame can be disposed on an edge of the bonding layer. The method can further comprise removing the bonding layer first and then performing a singulation process.
After forming the RDL structure, the above-described method can further comprise performing a singulation process.
In the above-described electronic package and method, each of the conductors can have a ball shape, a post shape or a stud shape.
In the above-described electronic package and method, the conductors can be formed at an outer periphery of the electronic element.
In the above-described electronic package and method, the RDL structure can have at least a dielectric layer and at least a circuit layer formed on the dielectric layer and directly electrically connected to the conductors.
In the above-described electronic package and method, the RDL structure can have at least a dielectric layer, at least a circuit layer formed on the dielectric layer, and a plurality of conductive vias formed in the insulating layer for electrically connecting the circuit layer and the conductors.
In the above-described electronic package and method, the second side of the packaging substrate can be exposed from the insulating layer, allowing a plurality of conductive elements to be formed thereon and electrically connected to the packaging substrate.
According to the present invention, the conductors are formed first and then the packaging structure is encapsulated with the insulating layer in a manner that the insulating layer covers a side surface of the packaging substrate. Further, the invention replaces a conventional electronic device such as an interposer or a packaging substrate with the RDL structure. Compared with the prior art, the area of the insulating layer is not required to correspond to the area of the packaging substrate, thus allowing the area of the packaging substrate to be reduced according to the practical need so as to reduce the width of the electronic package and meet the miniaturization requirement.
BRIEF DESCRIPTION OF DRAWINGS
FIG. 1 is a schematic cross-sectional view of a conventional semiconductor package; and
FIGS. 2A and 2F are schematic cross-sectional views showing a method for fabricating an electronic package according to the present invention, wherein FIG. 2C′ show another embodiment of FIG. 2C.
 DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparent to those in the art after reading this specification.
It should be noted that all the drawings are not intended to limit the present invention. Various modifications and variations can be made without departing from the spirit of the present invention. Further, terms such as “first”, “second”, “on”, “a” etc. are merely for illustrative purposes and should not be construed to limit the scope of the present invention.
FIGS. 2A to 2F are schematic cross-sectional views showing a method for fabricating an electronic package 2 according to the present invention.
Referring to FIG. 2A, at least a packaging structure 2 a is provided and disposed on a carrier 30. The packaging structure 2 a has a packaging substrate 20 having a first side 20 a and a second side 20 b opposite to the first side 20 a, an electronic element 21 disposed on the first side 20 a of the packaging substrate 20, and a plurality of conductors 27 formed on the first side 20 a of the packaging substrate 20.
In the present embodiment, the packaging substrate 20 has a plurality of dielectric layers 200 and a plurality of circuit layers 201 formed on the dielectric layers 200 and electrically connected to the electronic element 21 and the conductors 27. It should be noted that although only some circuit layers 201 on the first side 20 a of the packaging substrate 20 are shown in the drawings, the present invention is not limited thereto. For example, a plurality of circuit layers can be formed on the second side 20 b of the packaging substrate 20 and inside the packaging substrate 20 according to the practical need.
The electronic element 21 is an active element such as a semiconductor chip, a passive element such as a resistor, a capacitor or an inductor, or a combination thereof. For example, the electronic element 21 is a semiconductor chip having an active surface 21 a with a plurality of electrode pads 210 and an inactive surface 21 b opposite to the active surface 21 a. The electronic element 21 is flip-chip disposed on the packaging substrate 20, and the electrode pads 210 of the electronic element 21 are electrically connected to the circuit layers 201 through a plurality of solder bumps 22. Further, an underfill 23 is formed between the electronic element 21 and the circuit layers 201 to encapsulate the solder bumps 22.
Each of the conductors 27 can have a ball shape, a post shape or a stud shape. For example, the conductors 27 can be solder balls, copper posts, solder bumps, or studs formed by a wire bonder.
The carrier 30 is a circular substrate made of glass having a diameter of 12 inch or 300 mm. A release layer 31 and an adhesive layer 32 are sequentially formed on the carrier 30 by coating, and the second side 20 b of the packaging substrate 20 is attached to the carrier 30 through the adhesive layer 22.
Referring to FIG. 2B, an insulating layer 24 is formed on the carrier 30 to encapsulate the packaging structure 2 a.
In the present embodiment, the insulating layer 24 covers a side surface 20 c of the packaging substrate 20 that is adjacent to and connecting the first side 20 a and the second side 20 b of the packaging substrate 20.
The insulating layer 24 can be made of an encapsulant such as an epoxy resin and formed by lamination or molding.
Referring to FIG. 2C, an RDL (Redistribution Layer) structure 25 is formed on the insulating layer 24 and electrically connected to the conductors 27.
In the present embodiment, the RDL structure 25 has at least a dielectric layer 250 and at least a circuit layer 251 formed on the dielectric layer 251 and directly electrically connected to the conductors 27.
In another embodiment, referring to FIG. 2C′, the RDL structure 25′ further has a plurality of conductive vias 252 are formed in the insulating layer 24 for electrically connecting the circuit layer 251 and the conductors 27.
The circuit layer 251 is made of copper, and the dielectric layer 250 is made of a photoresist material or polybenzoxazole (PBO).
Referring to FIG. 2D, continued from FIG. 2C, a bonding layer 28 such as a tape is formed on the RDL structure 25, and then the carrier 30 and the adhesive layer 32 are removed.
In the present embodiment, ultraviolet or laser light passes through the carrier 30 and irradiates the release layer 31 (made of a photosensitive material) so as to cause removal of the release layer 31, thereby allowing removal of the carrier 30.
Further, a metal frame 29 such as an iron ring is disposed on an edge of the bonding layer 28 to prevent warping of the bonding layer 28.
Referring to FIG. 2E, a plurality of conductive elements 26 such as solder balls are formed on the second side 20 b of the packaging substrate 20 for mounting another package or an electronic device such as a circuit board or an interposer. The conductive elements 26 are electrically connected to the circuit layers 201 of the packaging substrate 20.
Referring to FIG. 2F, a singulation process is performed along cutting paths S of FIG. 2E, with the metal frame 29 being removed. Further, the bonding layer 28 is removed from the RDL structure 25. As such, an electronic package 2 is obtained.
According to the present invention, the conductors 27 are formed on the packaging substrate 20 first and then the packaging structure 2 a is encapsulated with the insulating layer 24 in a manner that the insulating layer 24 covers the side surface 20 c of the packaging substrate 20. As such, the area of the insulating layer 24 is required to correspond to the area of the carrier 30 instead of the packaging substrate 20. Therefore, the area of the packaging substrate 20 can be reduced according to the practical need so as to reduce the width of the electronic package 2 and meet the miniaturization requirement.
Further, by replacing a conventional electronic device such as an interposer or a packaging substrate with the RDL structure 25, 25′, the invention allows the packaging substrate 20 to be reduced according to the practical need so as to reduce the width of the electronic package 2 and meet the miniaturization requirement.
The present invention further provides an electronic package 2, which has: a packaging substrate 20 having opposite first and second sides 20 a, 20 b; an electronic element 21 disposed on the first side 20 a of the packaging substrate 20; a plurality of conductors 27 formed on the first side 20 a of the packaging substrate 20; an insulating layer 24 encapsulating the packaging substrate 20, the electronic element 21 and the conductors 27, wherein the second side 20 b of the packaging substrate 20 is exposed from the insulating layer 24; and an RDL structure 25, 25′ formed on the insulating layer 24 and electrically connected to the conductors 27.
The conductors 27 can be formed at an outer periphery of the electronic element 21. The conductors 27 can be metal posts.
The insulating layer 24 can cover the side surface 20 c of the packaging substrate 20.
In an embodiment, the RDL structure 25 has at least a dielectric layer 250 and at least a circuit layer 251 formed on the dielectric layer 250 and directly electrically connected to the conductors 27.
In an embodiment, the RDL structure 25′ has at least a dielectric layer 250, at least a circuit layer 251 formed on the dielectric layer 250, and a plurality of conductive vias 252 formed in the insulating layer 24 for electrically connecting the circuit layer 251 and the conductors 27.
In an embodiment, the electronic package 2 further has a plurality of conductive elements 26 formed on the second side 20 b of the packaging substrate 20 and electrically connected to the packaging substrate 20.
Therefore, the present invention forms the conductors first and then encapsulates the packaging structure with the insulating layer so as to allow the insulating layer to cover the side surface of the packaging substrate. Further, the invention replaces the conventional electronic device such as an interposer or a packaging substrate with the RDL structure. As such, the area of the insulating layer is not required to correspond to the area of the packaging substrate, and hence the area of the packaging substrate can be reduced according to the practical need so as to reduce the width of the electronic package and meet the miniaturization requirement.
The above-described descriptions of the detailed embodiments are only to illustrate the preferred implementation according to the present invention, and it is not to limit the scope of the present invention. Accordingly, all modifications and variations completed by those with ordinary skill in the art should fall within the scope of present invention defined by the appended claims.

Claims (16)

What is claimed is:
1. An electronic package, comprising:
a packaging substrate having opposite first and second sides;
an electronic element disposed on the first side of the packaging substrate;
a plurality of conductors formed on the first side of the packaging substrate;
an insulating layer encapsulating the packaging substrate, the electronic element and the conductors, wherein the insulating layer covers side surfaces of the packaging substrate and the second side of the packaging substrate is exposed from the insulating layer; and
an RDL (Redistribution Layer) structure formed on the insulating layer and electrically connected to the conductors.
2. The package of claim 1, wherein each of the conductors has a ball shape, a post shape or a stud shape.
3. The package of claim 1, wherein the conductors are formed at an outer periphery of the electronic element.
4. The package of claim 1, wherein the RDL structure has at least a dielectric layer and at least a circuit layer formed on the dielectric layer and directly electrically connected to the conductors.
5. The package of claim 1, wherein the RDL structure has at least a dielectric layer, at least a circuit layer formed on the dielectric layer, and a plurality of conductive vias formed in the insulating layer for electrically connecting the circuit layer and the conductors.
6. The package of claim 1, further comprising a plurality of conductive elements formed on the second side of the packaging substrate and electrically connected to the packaging substrate.
7. A method for fabricating an electronic package, comprising the steps of:
providing at least a packaging structure, wherein the packaging structure has a packaging substrate having opposite first and second sides, an electronic element disposed on the first side of the packaging substrate and a plurality of conductors formed on the first side of the packaging substrate;
encapsulating the packaging structure with an insulating layer, wherein the insulating layer covers side surfaces of the packaging substrate; and
forming an RDL (Redistribution Layer) structure on the insulating layer, wherein the RDL structure is electrically connected to the conductors.
8. The method of claim 7, wherein each of the conductors has a ball shape, a post shape or a stud shape.
9. The method of claim 7, wherein the conductors are formed at an outer periphery of the electronic element.
10. The method of claim 7, wherein the RDL structure has at least a dielectric layer and at least a circuit layer formed on the dielectric layer and directly electrically connected to the conductors.
11. The method of claim 7, wherein the RDL structure has at least a dielectric layer, at least a circuit layer formed on the dielectric layer, and a plurality of conductive vias formed in the insulating layer for electrically connecting the circuit layer and the conductors.
12. The method of claim 7, wherein the second side of the packaging substrate is exposed from the insulating layer, allowing a plurality of conductive elements to be formed thereon and electrically connected to the packaging substrate.
13. The method of claim 7, further comprising forming a bonding layer on the RDL structure.
14. The method of claim 13, wherein a metal frame is disposed on an edge of the bonding layer.
15. The method of claim 13, further comprising removing the bonding layer first and then performing a singulation process.
16. The method of claim 7, after forming the RDL structure, further comprising performing a singulation process.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10700008B2 (en) * 2018-05-30 2020-06-30 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure having redistribution layer structures
US20200279786A1 (en) * 2019-02-28 2020-09-03 Hon Hai Precision Industry Co., Ltd. Chip packaging structure and method for manufacturing the same
US11004827B2 (en) * 2018-09-18 2021-05-11 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method of semiconductor package
US11373954B2 (en) 2019-08-21 2022-06-28 Samsung Electronics Co., Ltd. Semiconductor package

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI620296B (en) * 2015-08-14 2018-04-01 矽品精密工業股份有限公司 Electronic package and its manufacturing method
US9570369B1 (en) * 2016-03-14 2017-02-14 Inotera Memories, Inc. Semiconductor package with sidewall-protected RDL interposer and fabrication method thereof
US9837359B1 (en) * 2016-09-30 2017-12-05 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
TWI602275B (en) * 2016-10-14 2017-10-11 恆勁科技股份有限公司 Package structure and manufacturing method thereof
US10276536B2 (en) * 2017-04-28 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of chip package with fan-out structure
US11410897B2 (en) * 2019-06-27 2022-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure having a dielectric layer edge covering circuit carrier
CN112786540A (en) * 2019-11-06 2021-05-11 富泰华工业（深圳）有限公司 Fan-out type packaging structure and manufacturing method thereof
TWI753561B (en) * 2020-09-02 2022-01-21 矽品精密工業股份有限公司 Electronic package and manufacturing method thereof
TWI855382B (en) * 2022-09-19 2024-09-11 大陸商芯愛科技（南京）有限公司 Packaging substrate and fabrication method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7642128B1 (en) * 2008-12-12 2010-01-05 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US20140138791A1 (en) * 2012-11-20 2014-05-22 Siliconware Precision Industries Co., Ltd. Semiconductor package and fabrication method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI505757B (en) * 2012-07-19 2015-10-21 A circuit board with embedded components
CN203118928U (en) * 2012-12-13 2013-08-07 欣兴电子股份有限公司 Packaging structure

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7642128B1 (en) * 2008-12-12 2010-01-05 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US20140138791A1 (en) * 2012-11-20 2014-05-22 Siliconware Precision Industries Co., Ltd. Semiconductor package and fabrication method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10700008B2 (en) * 2018-05-30 2020-06-30 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure having redistribution layer structures
US11004827B2 (en) * 2018-09-18 2021-05-11 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method of semiconductor package
US20200279786A1 (en) * 2019-02-28 2020-09-03 Hon Hai Precision Industry Co., Ltd. Chip packaging structure and method for manufacturing the same
US11056411B2 (en) * 2019-02-28 2021-07-06 Socle Technology Corp. Chip packaging structure
US11373954B2 (en) 2019-08-21 2022-06-28 Samsung Electronics Co., Ltd. Semiconductor package
US12062621B2 (en) 2019-08-21 2024-08-13 Samsung Electronics Co., Ltd. Semiconductor package

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TWI555098B (en) 2016-10-21

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