US9324428B1 - Memory device and operation method thereof - Google Patents

Memory device and operation method thereof Download PDF

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US9324428B1
US9324428B1 US14/727,953 US201514727953A US9324428B1 US 9324428 B1 US9324428 B1 US 9324428B1 US 201514727953 A US201514727953 A US 201514727953A US 9324428 B1 US9324428 B1 US 9324428B1
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pulse
current
memory device
operation state
set verification
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Wei-Chih Chien
Yung-Han Ho
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Macronix International Co Ltd
International Business Machines Corp
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Macronix International Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0097—Erasing, e.g. resetting, circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1677—Verifying circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5607—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using magnetic storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5678—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using amorphous/crystalline phase transition storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0064—Verifying circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0076—Write operation performed depending on read result
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0092—Write characterized by the shape, e.g. form, length, amplitude of the write pulse

Definitions

  • the disclosure relates in general to a memory device and an operation method thereof.
  • the storage class memory may be used for reducing system latency, and thus draws more intention.
  • SCM storage class memory
  • MLC multi-level control
  • a memory device and an operation method thereof which may improve the performance of the memory device, for example, short write latency and low write power consumption.
  • the disclosure is directed to a memory device and an operation method thereof which programs the memory device by at least an incremental pulse set verification current and/or at least an identical pulse set verification current to reduce write latency and write power consumption.
  • an operation method for a memory device includes: determining an operation state of the memory device; when the memory device is determined to be operated in a first operation state, applying a reset pulse to the memory device; when the memory device is determined to be operated in a second operation state, applying the reset pulse and at least a first incremental pulse set verification current to the memory device, an allowable maximum current of the first incremental pulse set verification current being lower than a melt current; when the memory device is determined to be operated in a third operation state, applying the reset pulse and at least a first identical pulse set verification current to the memory device, an allowable maximum current of the first identical pulse set verification current being lower than the melt current; and when the memory device is determined to be operated in a fourth operation state, applying a set pulse to the memory device.
  • a memory device includes: a memory array; a control circuit, determining an operation state of the memory array according to an input data; and a pulse generation circuit, coupled to the memory array and the control circuit, and controlled by the control circuit.
  • the control circuit determines the memory array to be operated in a first operation state
  • the pulse generation circuit applies a reset pulse to the memory array.
  • the pulse generation circuit applies the reset pulse and at least a first incremental pulse set verification current to the memory array, an allowable maximum current of the first incremental pulse set verification current being lower than a melt current.
  • the pulse generation circuit applies the reset pulse and at least a first identical pulse set verification current to the memory array, an allowable maximum current of the first identical pulse set verification current being lower than the melt current.
  • the pulse generation circuit applies a set pulse to the memory device.
  • FIG. 1 shows a functional block diagram of a memory device according to an embodiment of the application.
  • FIG. 2 shows an operation method for a memory device according to an embodiment of the application.
  • FIG. 3A shows waveforms of pulse currents applied in an embodiment of the application.
  • FIG. 3B shows a relationship between the resistance of the memory array and the normalized memory cell counts after the operation method of the embodiment of the application is applied.
  • FIG. 3C shows a relationship between the pulse counts and the normalized memory cell counts after the operation method of the embodiment of the application is applied.
  • FIG. 4 shows other possible waveforms of the pulse currents applied in an embodiment of the application.
  • FIG. 5 shows a relationship between the resistance and the current, for showing the definition of the melting current.
  • FIG. 1 shows a functional block diagram of a memory device according to an embodiment of the application.
  • the memory device 100 includes: a memory array 110 , a pulse generation circuit 120 and a control circuit 130 .
  • the memory device 100 is for example but not limited by a 2-terminal memory device.
  • the 2-terminal memory device for example includes a resistive type memory device.
  • the resistive type memory device for example includes a phase change memory (PCM) device, a magnetoresistive random access memory (MRAM) device or a resistive random access memory (RRAM, ReRAM) device.
  • PCM phase change memory
  • MRAM magnetoresistive random access memory
  • RRAM resistive random access memory
  • the memory array 110 includes a plurality of memory cells arranged in an array.
  • the memory cells may be the MLC (multi-level control) phase change memory cells, which store data by different resistance levels. For example, if programmed to high resistance, the memory cells may store bit “1”; and if programmed to low resistance, the memory cells may store bit “0”.
  • a single memory cell may store at least 2 bits.
  • the control circuit 130 determines the operation state of the memory based on the input data IN and generates a state signal SS.
  • the pulse generation circuit 120 is coupled to the memory array 110 and the control circuit 130 . Based on the state signal SS from the control circuit 130 , the pulse generation circuit 120 generates pulses to the memory array 110 , for programming the memory array 110 to different states.
  • the memory array 110 may have 4 different states 00, 01, 10 and 11.
  • the state 00 refers that the memory cells are programmed for storing bits 00, and so on.
  • FIG. 2 shows an operation method for a memory device according to an embodiment of the application.
  • the state of the memory array 110 is determined.
  • the control circuit 130 determines the operation state (one of the states 00, 01, 10 and 11) of the memory array 110 based on the input data IN. If the memory array 110 is to be programmed to the state 11, as shown in step 220 , a reset pulse RESET_P is applied to the memory array 110 . If the memory array 110 is to be programmed to the state 10, as shown in step 240 - 248 , the reset pulse RESET_P and incremental pulse set verification currents S_IN 1 +S_IN 2 + . . . are applied to the memory array 110 .
  • the reset pulse RESET_P and identical pulse set verification currents S_ID 1 +S_ID 2 + . . . are applied to the memory array 110 .
  • a set pulse SET_P is applied to the memory array 110 .
  • the reset pulse RESET_P is applied to the memory array 110 .
  • incremental pulse set verification currents S_IN 1 +S_IN 2 + . . . S_IN i are applied to the memory array 110 .
  • whether the memory array 110 passes the verification is checked (that is, whether the memory array 110 is already programmed to the state 10 is checked). If yes, then the operation is ended.
  • the reset pulse RESET_P is applied to the memory array 110 .
  • the identical pulse set verification currents S_ID 1 +S_ID 2 + . . . S_ID k are applied to the memory array 110 .
  • whether the memory array 110 passes the verification is checked (that is, whether the memory array 110 is already programmed to the state 01 is checked). If yes, then the operation is ended.
  • FIG. 3A shows waveforms of pulse currents applied in an embodiment of the application.
  • the set pulse SET_P is in a staircase waveform having a pulse width for example 800 ns and an initial current 200 ⁇ A.
  • the set pulse SET_P may be referred to a single staircase set pulse. That is to say, during the pulse width, the set pulse SET_P is reduced from the initial current 200 ⁇ A to a value (for example, 0 A).
  • the reset pulse RESET_P has a pulse width for example 40 ns and an initial current 400 ⁇ A.
  • a high current (the reset pulse RESET_P) is applied in a short interval to program the memory cells in amorphous state, for programming the memory cells to the state 11.
  • the incremental pulse set verification currents S_IN 1 , S_IN 2 , . . . and S_IN i are shown in FIG. 3A .
  • the incremental pulse set verification currents S_IN 1 , S_IN 2 , . . . and S_IN i have pulse widths of 160 ns and are in staircase waveforms.
  • the incremental pulse set verification currents S_IN 1 , S_IN 2 , . . . and S_IN i in FIG. 3A may be referred to the incremental staircase pulse set verification currents.
  • the incremental pulse set verification current S_IN 1 has the lowest initial current value (for example, 25 ⁇ A)
  • the later-applied incremental pulse set verification current S_IN i has higher initial current than the former-applied incremental pulse set verification current S_IN (i+1) .
  • the allowable maximum initial current of the incremental pulse set verification currents cannot be higher than the melting current (which is for example 45 ⁇ A).
  • the incremental pulse set verification current S_IN i during the pulse width, the current value is reduced from the initial current to a value (for example, 0 ⁇ A).
  • the identical pulse set verification currents S_ID 1 , S_ID 2 , . . . and S_ID j are shown in FIG. 3A .
  • the identical pulse set verification currents S_ID 1 , S_ID 2 , . . . and S_ID j have pulse widths of 160 ns and are in staircase waveforms.
  • the identical pulse set verification currents S_ID 1 , S_ID 2 , . . . and S_ID j in FIG. 3A may be referred to the identical staircase pulse set verification currents.
  • the identical pulse set verification currents S_ID 1 , S_ID 2 , . . . and S_ID j have the same initial current value (for example, 45 ⁇ A).
  • the allowable maximum initial current of the identical pulse set verification currents cannot be higher than the melting current (which is for example 45 ⁇ A).
  • the identical pulse set verification current S_IN i during the pulse width, the current value is reduced from the initial current to a value (for example, 0 ⁇ A).
  • the identical pulse set verification currents S_ID 1 , S_ID 2 , . . . and S_ID j are the same.
  • the reset pulse RESET_P is applied to the memory array 110 .
  • the incremental pulse set verification current S_IN 1 is applied to the memory array 110 and whether the memory array 110 passes the verification is determined. If not, which means the resistance of the memory array 110 is still too high, more incremental pulse set verification currents are to be applied to the memory array 110 .
  • the incremental pulse set verification current S_IN 1 and S_IN 2 are applied to the memory array 110 (that is, one more incremental pulse set verification current is applied) and whether the memory array 110 passes the verification is determined. The loop is repeated until the memory array 110 passes the verification.
  • the reset pulse RESET_P is applied to the memory array 110 .
  • the identical pulse set verification current S_ID 1 is applied to the memory array 110 and whether the memory array 110 passes the verification is determined. If not, which means the resistance of the memory array 110 is still too high, more identical pulse set verification currents are to be applied to the memory array 110 .
  • the identical pulse set verification currents S_ID 1 and S_ID 2 are applied to the memory array 110 (that is, one more identical pulse set verification current is applied) and whether the memory array 110 passes the verification is determined. The loop is repeated until the memory array 110 passes the verification.
  • FIG. 3B shows a relationship between the resistance of the memory array and the normalized memory cell counts after the operation method of the embodiment of the application is applied.
  • the normalized memory cell counts refer to that the normalized percentage of the memory cells in the resistance range.
  • the percentage of the memory cells in the state 11 is 98.3%
  • the percentage of the memory cells in the state 10 is 97.4%
  • the percentage of the memory cells in the state 01 is 98.9%
  • the percentage of the memory cells in the state 00 is 99.9%.
  • FIG. 3B after the embodiment of the application is applied, a large number of the memory cells are effectively programmed to the desired state, and thus the performance of the memory device is improved.
  • FIG. 3C shows a relationship between the pulse counts (the parameters “i” and/or “j”) and the normalized memory cell counts after the operation method of the embodiment of the application is applied.
  • the pulse counts the parameters “i” and/or “j”
  • FIG. 3C shows a relationship between the pulse counts (the parameters “i” and/or “j”) and the normalized memory cell counts after the operation method of the embodiment of the application is applied.
  • the embodiment of the application may effectively reduce the number of the applied pulses and accordingly, the power consumption and the write latency are reduced.
  • FIG. 4 shows other possible waveforms of the pulse currents applied in an embodiment of the application.
  • the set pulse SET_P and the reset pulse RESET_P in FIG. 4 are the same or similar to the set pulse SET_P and the reset pulse RESET_P in FIG. 3 and thus the details are omitted.
  • the incremental pulse set verification currents S_IN 1 ′, S_IN 2 ′, . . . and S_IN i ′ have pulse widths of 40 ns and are in box waveforms.
  • the incremental pulse set verification currents S_IN 1 ′, S_IN 2 ′, . . . and S_IN i ′ in FIG. 4 may be referred to the incremental box pulse set verification currents.
  • the incremental pulse set verification current S_IN 1 ′ has the lowest initial current value (for example, 25 ⁇ A)
  • the later-applied incremental pulse set verification current S_IN i ′ has higher initial current than the former-applied incremental pulse set verification current S_IN (i+1) ′.
  • the allowable maximum initial current of the incremental pulse set verification currents cannot be higher than the melting current (which is for example 45 ⁇ A).
  • the identical pulse set verification currents S_ID 1 ′, S_ID 2 ′, . . . and S_ID j ′ are shown in FIG. 4 .
  • the identical pulse set verification currents S_ID 1 ′, S_ID 2 ′, . . . and S_ID j ′ have pulse widths of 40 ns and are in box waveforms.
  • the identical pulse set verification currents S_ID 1 ′, S_ID 2 ′, . . . and S_ID j ′ in FIG. 4 may be referred to the identical box pulse set verification currents.
  • S_ID 1 ′, S_ID 2 ′, . . . and S_ID j ′ have the same initial current value (for example, 45 ⁇ A).
  • the allowable maximum initial current of the identical pulse set verification currents cannot be higher than the melting current (which is for example 45 ⁇ A).
  • the identical pulse set verification currents S_ID 1 ′, S_ID 2 ′, . . . and S_ID j ′ are the same.
  • the set verification currents S — ID/S — ID′/S — IN/S_IN′ are for example in staircase or box waveforms, the application is not limited by this.
  • the set verification currents S_ID/S_ID′/S_IN/S_IN′ may be in triangular waveforms, or trapezium waveforms.
  • the later-applied incremental pulse set verification currents S_IN/S_IN′ have higher initial currents.
  • the identical pulse set verification currents S_ID/S_ID′ are the same.
  • FIG. 5 shows a relationship between the resistance and the current, for showing the definition of the melting current.
  • the left drawing in FIG. 5 shows that when the pulse having 40 ns pulse width is applied, the relationship between the resistance and the current (from 10 ⁇ A to 100 ⁇ A) is shown.
  • the middle drawing in FIG. 5 shows that when the pulse having 160 ns pulse width is applied, the relationship between the resistance and the current (from 10 ⁇ A to 100 ⁇ A) is shown.
  • the right drawing in FIG. 5 shows that when the pulse having 480 ns pulse width is applied, the relationship between the resistance and the current (from 10 ⁇ A to 100 ⁇ A) is shown.
  • the resistance value will be suddenly changed from a low value to a high value.
  • This threshold value is called as the melting current. That is, if the operation current is above the melting current, the resistance value will be suddenly changed from a low value to a high value.
  • the applied current in order to prevent the resistance have a sudden change, in programming the memory array to the state 10/01, the applied current cannot be above the melting current.
  • the memory device has advantages, such as short write latency, low write power consumption, high performance, high reliability, and fast and correct programming.

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  • Engineering & Computer Science (AREA)
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  • Chemical & Material Sciences (AREA)
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  • Semiconductor Memories (AREA)

Abstract

An operation method for a memory device is disclosed. An operation state of the memory device is determined. If to be operated in a first operation state, the memory device is applied by a reset pulse. If to be operated in a second operation state, the memory device is applied by the reset pulse and at least a first incremental pulse set verification current, and an allowable maximum current of the first incremental pulse set verification current is lower than a melt current. If to be operated in a third operation state, the memory device is applied by the reset pulse and at least a first identical pulse set verification current, and an allowable maximum current of the first identical pulse set verification current is lower than the melt current. If to be operated in a fourth operation state, the memory device is applied by a set pulse.

Description

This application claims the benefit of U.S. Provisional application Ser. No. 62/107,489, filed Jan. 25, 2015, the disclosure of which is incorporated by reference herein in its entirety.
TECHNICAL FIELD
The disclosure relates in general to a memory device and an operation method thereof.
BACKGROUND
The storage class memory (SCM) may be used for reducing system latency, and thus draws more intention. However, because of long write latency and high write power consumption, it is difficult to apply the multi-level control (MLC) phase control memory in the SCM.
Thus, there needs a memory device and an operation method thereof, which may improve the performance of the memory device, for example, short write latency and low write power consumption.
SUMMARY
The disclosure is directed to a memory device and an operation method thereof which programs the memory device by at least an incremental pulse set verification current and/or at least an identical pulse set verification current to reduce write latency and write power consumption.
According to one embodiment, an operation method for a memory device is provided. The operation method for a memory device includes: determining an operation state of the memory device; when the memory device is determined to be operated in a first operation state, applying a reset pulse to the memory device; when the memory device is determined to be operated in a second operation state, applying the reset pulse and at least a first incremental pulse set verification current to the memory device, an allowable maximum current of the first incremental pulse set verification current being lower than a melt current; when the memory device is determined to be operated in a third operation state, applying the reset pulse and at least a first identical pulse set verification current to the memory device, an allowable maximum current of the first identical pulse set verification current being lower than the melt current; and when the memory device is determined to be operated in a fourth operation state, applying a set pulse to the memory device.
According to another embodiment, a memory device is provided. The memory device includes: a memory array; a control circuit, determining an operation state of the memory array according to an input data; and a pulse generation circuit, coupled to the memory array and the control circuit, and controlled by the control circuit. When the control circuit determines the memory array to be operated in a first operation state, the pulse generation circuit applies a reset pulse to the memory array. When the control circuit determines the memory array to be operated in a second operation state, the pulse generation circuit applies the reset pulse and at least a first incremental pulse set verification current to the memory array, an allowable maximum current of the first incremental pulse set verification current being lower than a melt current. When the control circuit determines the memory array to be operated in a third operation state, the pulse generation circuit applies the reset pulse and at least a first identical pulse set verification current to the memory array, an allowable maximum current of the first identical pulse set verification current being lower than the melt current. When the control circuit determines the memory array to be operated in a fourth operation state, the pulse generation circuit applies a set pulse to the memory device.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a functional block diagram of a memory device according to an embodiment of the application.
FIG. 2 shows an operation method for a memory device according to an embodiment of the application.
FIG. 3A shows waveforms of pulse currents applied in an embodiment of the application.
FIG. 3B shows a relationship between the resistance of the memory array and the normalized memory cell counts after the operation method of the embodiment of the application is applied.
FIG. 3C shows a relationship between the pulse counts and the normalized memory cell counts after the operation method of the embodiment of the application is applied.
FIG. 4 shows other possible waveforms of the pulse currents applied in an embodiment of the application.
FIG. 5 shows a relationship between the resistance and the current, for showing the definition of the melting current.
In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing.
DETAILED DESCRIPTION
Technical terms of the disclosure are based on general definition in the technical field of the disclosure. If the disclosure describes or explains one or some terms, definition of the terms is based on the description or explanation of the disclosure. Each of the disclosed embodiments has one or more technical features. In possible implementation, one skilled person in the art would selectively implement part or all technical features of any embodiment of the disclosure or selectively combine part or all technical features of the embodiments of the disclosure.
FIG. 1 shows a functional block diagram of a memory device according to an embodiment of the application. As shown in FIG. 1, the memory device 100 includes: a memory array 110, a pulse generation circuit 120 and a control circuit 130. The memory device 100 is for example but not limited by a 2-terminal memory device. Further, the 2-terminal memory device for example includes a resistive type memory device. The resistive type memory device for example includes a phase change memory (PCM) device, a magnetoresistive random access memory (MRAM) device or a resistive random access memory (RRAM, ReRAM) device.
The memory array 110 includes a plurality of memory cells arranged in an array. The memory cells may be the MLC (multi-level control) phase change memory cells, which store data by different resistance levels. For example, if programmed to high resistance, the memory cells may store bit “1”; and if programmed to low resistance, the memory cells may store bit “0”. A single memory cell may store at least 2 bits.
The control circuit 130 determines the operation state of the memory based on the input data IN and generates a state signal SS.
The pulse generation circuit 120 is coupled to the memory array 110 and the control circuit 130. Based on the state signal SS from the control circuit 130, the pulse generation circuit 120 generates pulses to the memory array 110, for programming the memory array 110 to different states. In here, the memory array 110 may have 4 different states 00, 01, 10 and 11. The state 00 refers that the memory cells are programmed for storing bits 00, and so on.
Now explain the programming of the memory array in the embodiment of the application.
FIG. 2 shows an operation method for a memory device according to an embodiment of the application. As shown in FIG. 2, in step 210, the state of the memory array 110 is determined. For example, the control circuit 130 determines the operation state (one of the states 00, 01, 10 and 11) of the memory array 110 based on the input data IN. If the memory array 110 is to be programmed to the state 11, as shown in step 220, a reset pulse RESET_P is applied to the memory array 110. If the memory array 110 is to be programmed to the state 10, as shown in step 240-248, the reset pulse RESET_P and incremental pulse set verification currents S_IN1+S_IN2+ . . . are applied to the memory array 110. If the memory array 110 is to be programmed to the state 01, as shown in step 260-268, the reset pulse RESET_P and identical pulse set verification currents S_ID1+S_ID2+ . . . are applied to the memory array 110. If the memory array 110 is to be programmed to the state 00, as shown in step 280, a set pulse SET_P is applied to the memory array 110.
Details of programming the memory array 110 to the state 10 are described. As shown in step 240, the reset pulse RESET_P is applied to the memory array 110. As shown in step 242, a parameter “i” is set as an initial value (i=1), and the parameter “i” refers to the count of the incremental pulse set verification currents applied to the memory array. In the step 244, incremental pulse set verification currents S_IN1+S_IN2+ . . . S_INi are applied to the memory array 110. In the step 246, whether the memory array 110 passes the verification is checked (that is, whether the memory array 110 is already programmed to the state 10 is checked). If yes, then the operation is ended. If no, in the step 248, the parameter “i” is added by 1 (i=i+1) and the flow returns to the step 244. That is to say, if the memory array 110 is not programmed to the state 10 yet, then the count of the applied incremental pulse set verification currents is increased (for example, increased by 1).
Details of programming the memory array 110 to the state 01 are described. Similarly, as shown in step 260, the reset pulse RESET_P is applied to the memory array 110. As shown in step 262, a parameter “j” is set as an initial value (j=1), and the parameter “j” refers to the count of the identical pulse set verification currents applied to the memory array. In the step 264, the identical pulse set verification currents S_ID1+S_ID2+ . . . S_IDk are applied to the memory array 110. In the step 266, whether the memory array 110 passes the verification is checked (that is, whether the memory array 110 is already programmed to the state 01 is checked). If yes, then the operation is ended. If no, in the step 268, the parameter “j” is added by 1 (j=j+1) and the flow returns to the step 264. That is to say, if the memory array 110 is not programmed to the state 01 yet, then the count of the applied identical pulse set verification currents is increased (for example, increased by 1).
FIG. 3A shows waveforms of pulse currents applied in an embodiment of the application. As shown in FIG. 3A, in the embodiment of the application, the set pulse SET_P is in a staircase waveform having a pulse width for example 800 ns and an initial current 200 μA. The set pulse SET_P may be referred to a single staircase set pulse. That is to say, during the pulse width, the set pulse SET_P is reduced from the initial current 200 μA to a value (for example, 0 A).
The reset pulse RESET_P has a pulse width for example 40 ns and an initial current 400 μA. In the embodiment of the application, a high current (the reset pulse RESET_P) is applied in a short interval to program the memory cells in amorphous state, for programming the memory cells to the state 11.
The incremental pulse set verification currents S_IN1, S_IN2, . . . and S_INi are shown in FIG. 3A. The incremental pulse set verification currents S_IN1, S_IN2, . . . and S_INi have pulse widths of 160 ns and are in staircase waveforms. Thus, the incremental pulse set verification currents S_IN1, S_IN2, . . . and S_INi in FIG. 3A may be referred to the incremental staircase pulse set verification currents. Among the incremental pulse set verification currents S_IN1, S_IN2, . . . and S_INi, the incremental pulse set verification current S_IN1 has the lowest initial current value (for example, 25 μA), the incremental pulse set verification current S_IN2 has the second lowest initial current value (for example, 25 μA+2 μA=27 μA) and so on. That is, in the embodiment, “incremental” refers to that the later-applied incremental pulse set verification current has higher initial current. As shown in the drawing, the later-applied incremental pulse set verification current S_INi has higher initial current than the former-applied incremental pulse set verification current S_IN(i+1). In here, the allowable maximum initial current of the incremental pulse set verification currents cannot be higher than the melting current (which is for example 45 μA).
Similarly, the incremental pulse set verification current S_INi, during the pulse width, the current value is reduced from the initial current to a value (for example, 0 μA).
The identical pulse set verification currents S_ID1, S_ID2, . . . and S_IDj are shown in FIG. 3A. The identical pulse set verification currents S_ID1, S_ID2, . . . and S_IDj have pulse widths of 160 ns and are in staircase waveforms. Thus, the identical pulse set verification currents S_ID1, S_ID2, . . . and S_IDj in FIG. 3A may be referred to the identical staircase pulse set verification currents. The identical pulse set verification currents S_ID1, S_ID2, . . . and S_IDj have the same initial current value (for example, 45 μA). In here, the allowable maximum initial current of the identical pulse set verification currents cannot be higher than the melting current (which is for example 45 μA). Similarly, the identical pulse set verification current S_INi, during the pulse width, the current value is reduced from the initial current to a value (for example, 0 μA). In fact, the identical pulse set verification currents S_ID1, S_ID2, . . . and S_IDj are the same.
Now refer to FIG. 2 and FIG. 3A. For programming the memory array 110 to the state 10, the reset pulse RESET_P is applied to the memory array 110. Then, in the first loop, the incremental pulse set verification current S_IN1 is applied to the memory array 110 and whether the memory array 110 passes the verification is determined. If not, which means the resistance of the memory array 110 is still too high, more incremental pulse set verification currents are to be applied to the memory array 110. Thus, in the second loop, the incremental pulse set verification current S_IN1 and S_IN2 are applied to the memory array 110 (that is, one more incremental pulse set verification current is applied) and whether the memory array 110 passes the verification is determined. The loop is repeated until the memory array 110 passes the verification.
Similarly, for programming the memory array 110 to the state 01, the reset pulse RESET_P is applied to the memory array 110. Then, in the first loop, the identical pulse set verification current S_ID1 is applied to the memory array 110 and whether the memory array 110 passes the verification is determined. If not, which means the resistance of the memory array 110 is still too high, more identical pulse set verification currents are to be applied to the memory array 110. Thus, in the second loop, the identical pulse set verification currents S_ID1 and S_ID2 are applied to the memory array 110 (that is, one more identical pulse set verification current is applied) and whether the memory array 110 passes the verification is determined. The loop is repeated until the memory array 110 passes the verification.
FIG. 3B shows a relationship between the resistance of the memory array and the normalized memory cell counts after the operation method of the embodiment of the application is applied. The normalized memory cell counts refer to that the normalized percentage of the memory cells in the resistance range. As shown in FIG. 3B, after the embodiment of the application is applied, the percentage of the memory cells in the state 11 is 98.3%, the percentage of the memory cells in the state 10 is 97.4%, the percentage of the memory cells in the state 01 is 98.9%, and the percentage of the memory cells in the state 00 is 99.9%. As shown in FIG. 3B, after the embodiment of the application is applied, a large number of the memory cells are effectively programmed to the desired state, and thus the performance of the memory device is improved.
FIG. 3C shows a relationship between the pulse counts (the parameters “i” and/or “j”) and the normalized memory cell counts after the operation method of the embodiment of the application is applied. As shown in FIG. 3C, in the state 01, a large number of the memory cells are programmed to the state 01 under the pulse number is 3 (j=3); similarly, in the state 10, a large number of the memory cells are programmed to the state 01 under the pulse number is 4 (i=4). Thus, as shown in FIG. 3C, the embodiment of the application may effectively reduce the number of the applied pulses and accordingly, the power consumption and the write latency are reduced.
FIG. 4 shows other possible waveforms of the pulse currents applied in an embodiment of the application. The set pulse SET_P and the reset pulse RESET_P in FIG. 4 are the same or similar to the set pulse SET_P and the reset pulse RESET_P in FIG. 3 and thus the details are omitted.
In FIG. 4, the incremental pulse set verification currents S_IN1′, S_IN2′, . . . and S_INi′ have pulse widths of 40 ns and are in box waveforms. Thus, the incremental pulse set verification currents S_IN1′, S_IN2′, . . . and S_INi′ in FIG. 4 may be referred to the incremental box pulse set verification currents. Among the incremental pulse set verification currents S_IN1′, S_IN2′, . . . and S_INi′, the incremental pulse set verification current S_IN1′ has the lowest initial current value (for example, 25 μA), the incremental pulse set verification current S_IN2′ has the second lowest initial current value (for example, 25 μA+2 μA=27 μA) and so on. As shown in the drawing, the later-applied incremental pulse set verification current S_INi′ has higher initial current than the former-applied incremental pulse set verification current S_IN(i+1)′. In here, the allowable maximum initial current of the incremental pulse set verification currents cannot be higher than the melting current (which is for example 45 μA).
The identical pulse set verification currents S_ID1′, S_ID2′, . . . and S_IDj′ are shown in FIG. 4. The identical pulse set verification currents S_ID1′, S_ID2′, . . . and S_IDj′ have pulse widths of 40 ns and are in box waveforms. Thus, the identical pulse set verification currents S_ID1′, S_ID2′, . . . and S_IDj′ in FIG. 4 may be referred to the identical box pulse set verification currents. The identical pulse set verification currents S_ID1′, S_ID2′, . . . and S_IDj′ have the same initial current value (for example, 45 μA). In here, the allowable maximum initial current of the identical pulse set verification currents cannot be higher than the melting current (which is for example 45 μA). In fact, the identical pulse set verification currents S_ID1′, S_ID2′, . . . and S_IDj′ are the same.
Further, in the above example, although the set verification currents S— ID/S— ID′/S— IN/S_IN′ are for example in staircase or box waveforms, the application is not limited by this. For example, in other possible embodiment of the application, the set verification currents S_ID/S_ID′/S_IN/S_IN′ may be in triangular waveforms, or trapezium waveforms. The later-applied incremental pulse set verification currents S_IN/S_IN′ have higher initial currents. The identical pulse set verification currents S_ID/S_ID′ are the same.
FIG. 5 shows a relationship between the resistance and the current, for showing the definition of the melting current. The left drawing in FIG. 5 shows that when the pulse having 40 ns pulse width is applied, the relationship between the resistance and the current (from 10 μA to 100 μA) is shown. The middle drawing in FIG. 5 shows that when the pulse having 160 ns pulse width is applied, the relationship between the resistance and the current (from 10 μA to 100 μA) is shown. The right drawing in FIG. 5 shows that when the pulse having 480 ns pulse width is applied, the relationship between the resistance and the current (from 10 μA to 100 μA) is shown. As shown in the middle and the right drawings in FIG. 5, if the operation current is above a threshold value (about 50 μA), the resistance value will be suddenly changed from a low value to a high value. This threshold value is called as the melting current. That is, if the operation current is above the melting current, the resistance value will be suddenly changed from a low value to a high value.
Thus, in the embodiment of the application, in order to prevent the resistance have a sudden change, in programming the memory array to the state 10/01, the applied current cannot be above the melting current.
As above described, the memory device according to the embodiment of the application has advantages, such as short write latency, low write power consumption, high performance, high reliability, and fast and correct programming.
It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments. It is intended that the specification and examples be considered as exemplary only, with a true scope of the disclosure being indicated by the following claims and their equivalents.

Claims (15)

What is claimed is:
1. An operation method for a memory device, including:
determining an operation state of the memory device;
when the memory device is determined to be operated in a first operation state, applying a reset pulse to the memory device;
when the memory device is determined to be operated in a second operation state, applying the reset pulse and at least a first incremental pulse set verification current to the memory device, an allowable maximum current of the first incremental pulse set verification current being lower than a melt current;
when the memory device is determined to be operated in a third operation state, applying the reset pulse and at least a first identical pulse set verification current to the memory device, an allowable maximum current of the first identical pulse set verification current being lower than the melt current; and
when the memory device is determined to be operated in a fourth operation state, applying a set pulse to the memory device.
2. The operation method for the memory device according to claim 1, wherein
the operation state of the memory device is determined according to an input data.
3. The operation method for the memory device according to claim 1, wherein the reset pulse includes a single staircase reset pulse for programming a plurality of memory cells of the memory device as amorphous; and
the set pulse includes a single staircase set pulse.
4. The operation method for the memory device according to claim 1, wherein
a plurality of memory cells in the first operation state have a highest resistance;
the memory cells in the second operation state have a second highest resistance;
the memory cells in the third operation state have a third highest resistance; and
the memory cells in the fourth operation state have a lowest resistance.
5. The operation method for the memory device according to claim 1, wherein
when the memory device is determined to be operated in the second operation state, after applying the reset pulse and the first incremental pulse set verification current to the memory device, checking whether the memory device is already programmed in the second operation state;
if not, applying a second incremental pulse set verification current to the memory device and checking whether the memory device is already programmed in the second operation state;
an allowable maximum current of the second incremental pulse set verification current is lower than the melt current; and
the allowable maximum current of the second incremental pulse set verification current is higher than the allowable maximum current of the first incremental pulse set verification current.
6. The operation method for the memory device according to claim 5, wherein
the first and the second incremental pulse set verification currents are chosen from a group of a staircase pulse, a rectangular pulse, a triangular pulse, and a trapezium pulse.
7. The operation method for the memory device according to claim 1, wherein
when the memory device is determined to be operated in the third operation state, after applying the reset pulse and the first identical pulse set verification current to the memory device, checking whether the memory device is already programmed in the third operation state;
if not, applying a second identical pulse set verification current to the memory device and checking whether the memory device is already programmed in the third operation state;
an allowable maximum current of the second identical pulse set verification current is lower than the melt current; and
the allowable maximum current of the second identical pulse set verification current is higher than the allowable maximum current of the first identical pulse set verification current.
8. The operation method for the memory device according to claim 7, wherein
the first and the second identical pulse set verification currents are chosen from a group of a staircase pulse, a rectangular pulse, a triangular pulse, and a trapezium pulse.
9. A memory device, including:
a memory array;
a control circuit, determining an operation state of the memory array according to an input data; and
a pulse generation circuit, coupled to the memory array and the control circuit, and controlled by the control circuit,
wherein
when the control circuit determines the memory array to be operated in a first operation state, the pulse generation circuit applies a reset pulse to the memory array;
when the control circuit determines the memory array to be operated in a second operation state, the pulse generation circuit applies the reset pulse and at least a first incremental pulse set verification current to the memory array, an allowable maximum current of the first incremental pulse set verification current being lower than a melt current;
when the control circuit determines the memory array to be operated in a third operation state, the pulse generation circuit applies the reset pulse and at least a first identical pulse set verification current to the memory array, an allowable maximum current of the first identical pulse set verification current being lower than the melt current; and
when the control circuit determines the memory array to be operated in a fourth operation state, the pulse generation circuit applies a set pulse to the memory device.
10. The memory device according to claim 9, wherein
the reset pulse includes a single staircase reset pulse for programming a plurality of memory cells of the memory array as amorphous; and
the set pulse includes a single staircase set pulse.
11. The memory device according to claim 9, wherein
a plurality of memory cells in the first operation state have a highest resistance;
the memory cells in the second operation state have a second highest resistance;
the memory cells in the third operation state have a third highest resistance; and
the memory cells in the fourth operation state have a lowest resistance.
12. The memory device according to claim 9, wherein
when the control circuit determines the memory array to be operated in the second operation state, after the pulse generation circuit applies the reset pulse and the first incremental pulse set verification current to the memory array, checking whether the memory array is already programmed in the second operation state;
if not, after the pulse generation circuit applies a second incremental pulse set verification current to the memory array, the control circuit checks whether the memory array is already programmed in the second operation state;
an allowable maximum current of the second incremental pulse set verification current is lower than the melt current; and
the allowable maximum current of the second incremental pulse set verification current is higher than the allowable maximum current of the first incremental pulse set verification current.
13. The memory device according to claim 12, wherein
the first and the second incremental pulse set verification currents are chosen from a group of a staircase pulse, a rectangular pulse, a triangular pulse, and a trapezium pulse.
14. The memory device according to claim 9, wherein
when the control circuit determines the memory array to be operated in the third operation state, after the pulse generation circuit applies the reset pulse and the first identical pulse set verification current to the memory array, checking whether the memory array is already programmed in the third operation state;
if not, the pulse generation circuit applies a second identical pulse set verification current to the memory device and the control circuit checks whether the memory array is already programmed in the third operation state;
an allowable maximum current of the second identical pulse set verification current is lower than the melt current; and
the allowable maximum current of the second identical pulse set verification current is higher than the allowable maximum current of the first identical pulse set verification current.
15. The memory device according to claim 14, wherein
the first and the second identical pulse set verification currents are chosen from a group of a staircase pulse, a rectangular pulse, a triangular pulse, and a trapezium pulse.
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