US9318813B2 - Signal processing block for a receiver in wireless communication - Google Patents
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- the present invention relates to an improved signal processing block and more particularly to a processor block for computing QR decomposition of a Channel Matrix for detection/estimation of incoming signals in, for example, a MIMO receiver for communication.
- MIMO multiple-input multiple-output
- QR decomposition is an essential signal processing task that is utilized in most MIMO detection schemes to decompose an estimated channel matrix into an upper triangular matrix, providing a suitable framework for sequential detection schemes.
- decomposition of complex MIMO channel matrices with large dimensions leads to high computational complexity and hence results in either large core area or low throughput.
- it is required to perform QRD with low processing latency.
- Givens rotations work on only two matrix rows at a time, they are more easily parallelized. Furthermore, the Coordinate Rotation Digital Computer (CORDIC) solution, in its vectoring and rotation modes, is usable to perform Givens rotations using low-complexity shift and add operations. These two factors make Givens rotations the method of choice for common QRD implementations with small dimensionality.
- CORDIC Coordinate Rotation Digital Computer
- using the conventional sequence of Givens rotations to decompose matrices with large dimensions leads to high computational complexity, due to the large number of required vectoring and rotation operations.
- a modified sequence of Givens rotations is presented by Y. T. Hwang and W. D.
- a device comprises a QR Decomposition (QRD) processing unit that includes an input port for receiving an input matrix having a plurality of real value elements and a processor operative to concurrently annihilate a portion of the plurality of real elements.
- the processor is configured to perform multi-dimensional Givens Rotations, multi-dimensional Householder Reflections, and two-dimensional (2D) Givens Rotations, multi-dimensional Householder Reflections to generate a QRD of the input matrix within a computational time.
- the processor further includes an output port for providing data relating to the QRD of the input matrix.
- the processor includes a circuitry to generate z vectors with a same time period as the QRD computational time.
- the input port is coupled with a multiple-input multiple-output receiver having multiple antennas.
- a method for computing QR decomposition includes receiving a data matrix relating to a received signal that is received at a plurality of antennas.
- the data matrix includes a plurality of real value elements.
- the method further includes concurrently annihilating a portion of the plurality of real value elements using a combination of multi-dimensional Givens Rotations, multi-dimensional Householder Reflections and conventional 2D Givens Rotations; computing the QR decomposition (QRD) of the matrix; and outputting data related to the QRD of the matrix.
- QRD QR decomposition
- the method includes approximating multiple two-dimensional Givens Rotations in parallel to either nullify multiple elements within a multi-dimensional vector or to rotate multi-dimensional vector by given angles, by use of multi-dimensional CORDIC algorithms and multi-dimensional Householder CORDIC algorithms. Furthermore, the method includes obtaining a strictly upper-triangular real R matrix by using a modified Real Value Decomposition (RVD) model. The method further includes performing multi-dimensional vector rotations by using only shift and add operations.
- the plurality of antennas include 2 or more antennas. In other embodiments, the plurality of antennas include at least 4 antennas.
- a method in another embodiment, includes operating with pipelined stages of an input controller for interfacing a QRD core with a preceding stage in the receiver and an output controller for interfacing the QRD core with a succeeding stage in the receiver, the input controller is configured to read in the input matrix and the output controller is configured to write out an output matrix.
- the method further includes operating with four pipelined central stages to compute the QRD of the input matrix and 4 z vectors, using un-rolled pipelined 2D, 3D and 4D CORDIC processors.
- the method includes operating with a multiplexer bank with datapath of each stage for selecting input operands for the CORDIC processor every cycle, and operating with a register bank for each central stage, for re-directing and holding the CORDIC outputs until the current central stage completes its desired computations.
- a method includes forming the 3D un-rolled CORDIC processors with 4 pipelined stages; implementing 2 sets of conventional 2D CORDIC elementary rotations in a single clock cycle for each stage, implementing one set of CORDIC equations in each half of the clock cycle by using a same set of 16-bit signed adders twice and using multiplexers to select input values to these adders, performing four 2D vectoring and twenty four 2D rotation operations within 40 clock cycles, in Stage1 of the 2D CORDIC processor; performing three 2D vectoring and twenty four 2D rotation operations within 40 clock cycles, in Stage4 of the 2D processor; implementing two sets of Householder 3D CORDIC elementary rotation processes within two clock cycles, for each stage of the 3D un-rolled CORDIC processor; performing one 3D vectoring and twelve 3D rotation operations within 40 clock cycles, in Stage3 of the un-rolled 3D CORDIC processor; configuring the 4D/2D configurable un-rolled CORDIC processor in Stage 2, such that the 4D/2D processor comprises 8 pipeline
- FIG. 1 illustrates a modified Real-valued H Matrix augmented with four Received Vectors and the element nullification sequence with conventional Givens rotations QRD, according to an embodiment of the invention.
- FIG. 2 illustrates a schematic view of the overall QRD algorithm core architecture, according to an embodiment of the invention.
- FIG. 3 illustrates a simplified schematic diagram of a single stage architecture for the Householder 3D CORDIC Processor, according to an embodiment of the invention.
- FIG. 4 illustrates a simplified schematic diagram of a single stage architecture for the 4D/2D configurable CORDIC Processor, according to an embodiment of the invention.
- FIG. 5 illustrates an Element Annihilation Sequence using Givens Rotations QRD scheme, as known in the prior art.
- FIG. 6 illustrates an Element Annihilation Sequence, in accordance with one embodiment of the present invention.
- FIG. 7 shows a QRD core, in accordance with one embodiment of the present invention.
- FIG. 8 shows a CORDIC processor, in accordance with one embodiment of the present invention.
- FIG. 9 shows an input coarse rotation stage for a 2D CORDIC processor, in accordance with one embodiment of the present invention.
- FIG. 10 shows an output coarse rotation and scaling stage for a 2D CORDIC processor, in accordance with one embodiment of the present invention.
- FIG. 11 is a block diagram of a 2D CORDIC processor, as known in the prior art.
- FIG. 12 is a block diagram of a 2D CORDIC processor, in accordance with one embodiment of the present invention.
- FIG. 13 is a block diagram of a 3D CORDIC processor, in accordance with one embodiment of the present invention.
- FIG. 14 is a block diagram of a 4D/2D configurable CORDIC processor, in accordance with one embodiment of the present invention.
- FIG. 15 shows the BER performance of a QRD core with different CORDIC processing gain scale factors, in accordance with one embodiment of the present invention.
- FIG. 16 shows the BER performance of a QRD core with different number of CORDIC algorithm iterations, in accordance with one embodiment of the present invention.
- FIG. 17 shows the BER performance of a different QRD cores for 4 ⁇ 4 matrix decomposition combined with 64-QAM K-best MIMO detector, in accordance with one embodiment of the present invention.
- FIG. 18 is a die micrograph of a QRD core, in accordance with one embodiment of the present invention.
- FIG. 19 is picture illustrating a test setup according to an embodiment of the present invention.
- FIG. 20 shows a measured maximum operating frequency and power consumption as a function of supply voltage, in accordance with one embodiment of the present invention.
- FIG. 21 is shows a comparison of QR processing efficiency between an embodiment of a QRD of the present invention and a conventional QRD.
- the N R -dimensional vector ⁇ v is an independent identically distributed (i.i.d) complex zero-mean Gaussian noise vector with variance ⁇ 2 .
- the matrix ⁇ H represents an N R ⁇ N T complex-valued channel matrix.
- the real-valued system model is derivable using the real valued decomposition (RVD) process as described in M. Shabany and P. G.
- the QRD core should be designed to generate a new 8 ⁇ 8 real R matrix and four 8 ⁇ 1 real z vectors every 40 clock cycles, while optionally minimizing power dissipation and gate count for an exemplary application of mobile communications.
- the QRD core may operate at a clock frequency of at least 270 MHz. Without loss of generality, this is an example.
- the QRD scheme is applicable and necessary to many other types of detection schemes, such as sphere decoding, etc.
- Givens rotations method is superior in terms of performance and hardware complexity for small dimensionality.
- QRD of a large H matrix using conventional sequence of Givens rotations relies on a large number of vectoring and rotations operations, e.g. for a 4 ⁇ 4 complex matrix, a total of 28 vectoring and 252 rotation operations are used.
- the modified sequence of Givens rotations presented by Y. T. Hwang and W. D. Chen reduces the number of vectoring and rotation operations to 16 and 136, respectively, which is still large.
- a hybrid QRD processing core uses a combination of multi-dimensional Givens rotations, Householder reflections and conventional two dimensional Givens rotations in order to reduce, over prior art implementations, the number of rotation operations performed and to enable a parallel implementation.
- the process increases throughput by annihilating multiple H * Re elements simultaneously, where Re is the real part of the complex element and * represents the indices in the matrix.
- the annihilating is achieved by using multi-dimensional Givens rotations and Householder reflections and reduces the overall circuit complexity by implementing these multi dimensional rotations using series of shift and add operations.
- Multi-dimensional Givens rotations operate on vectors of dimensions larger than 2, to align them with the first axis.
- An embodiment of the present invention uses a special sequence of Givens rotations that maintains symmetry between adjacent columns of H intact as explained in Y. T. Hwang and W. D. Chen, “A Low Complexity Complex QR Factorization Design for Signal Detection in MIMO OFDM Systems,” in Proc. IEEE ISCAS 2008, pp. 932-935, May 2008. Hence, the process only performs vectoring and rotation operations on odd numbered columns of H and the values for the elements in the even numbered columns can be derived automatically, without any computations.
- the process begins with annihilating the H * Im elements in the first column of the H matrix in a parallel manner using conventional 2D Givens rotations. It then uses 4D Givens rotations to annihilate the elements H 4,1 Re , H 3,1 Re and H 2,1 Re in parallel, as opposed to the sequential annihilation using the conventional 2D Givens rotations. As a result, a number of corresponding rotation operations is reduced by a factor of 3, from 42 to 14. Then, conventional 2D Givens rotations are used once again to perform parallel annihilation of the H * Im elements in the third column of the H matrix, shown in FIG. 1 . The proposed process then uses the 3D Householder CORDIC process to annihilate H 4,2 Re , H 3,2 Re simultaneously.
- the improved QRD process is used to develop a QRD architecture for 4 ⁇ 4 MIMO receivers.
- the QRD core outputs an 8 ⁇ 8 R matrix and four 8 ⁇ 1 z vectors every 40 clock cycles.
- 2D, 3D and 4D vector rotations are applied to the elements of the input H matrix to convert it to an upper-triangular R matrix.
- the updated symbol vectors, z are generated simultaneously while converting the input H matrix to the output R matrix. This obviates calculation of an inverse matrix in order to determine z.
- An implementation according to an embodiment comprises a novel pipelined architecture that uses un-rolled CORDIC processors, iteratively, to implement the proposed QRD process.
- the overall QRD architecture with the improved QRD process is illustrated in FIG. 2 wherein a simplified diagram of a QRD architecture for 4 ⁇ 4 MIMO receivers is shown.
- the QRD core performs a total of 16 vectoring and 136 rotation operations to output an 8 ⁇ 8 R matrix and four 8 ⁇ 1 z vectors every 40 clock cycles.
- FIG. 2 shows a pipelined architecture ( 290 ) using un-rolled CORDIC processors ( 245 a to 245 d ) iteratively to implement the proposed QRD process.
- the overall architecture comprises 6 pipelined stages.
- the Input Controller and Output Controller stages ( 200 a , 200 b ) provide interfaces for the QRD core to the preceding and succeeding stages in a MIMO receiver, to read in or write out the input and output matrices.
- input controller 200 a receives an input complex matrix and complex y vectors every 40 clock cycles from the preceding stage in the MIMO receiver.
- the input complex matrix includes a 4 ⁇ 4 complex H matrix and the complex y vectors comprises four 4 ⁇ 1 complex y vectors.
- Input controller 200 a then stores the received data and uses them to provide appropriate input operands to the CORDIC processors in a subsequent stage.
- input controller 200 a includes an input coarse rotation.
- Input controller 200 a based on the input operands, generates a control signal that is used by output controller 200 b to determine whether or not to perform an inverse rotation.
- Stage1-4 a QR decomposition of input H matrix, as well as 4 z vectors using un-rolled pipelined 2D, 3D and 4D CORDIC processors is computed.
- the datapath of each of these stages also contains a multiplexer bank ( 223 a to 223 d ), that is used to select the input operands for the CORDIC processor every cycle, and a register bank ( 280 a to 280 d ) that is used to re-direct and hold the CORDIC output ports until the current stage completes its computations.
- Each of these stages also comprises an independent Stage Controller ( 212 a to 212 d ) that provides control signals to direct appropriate data in and out of the CORDIC processor every cycle.
- the stage controller also controls the CORDIC mode of operation, the rotation direction transfers and re-use of the pipelined CORDIC stages in order to Maximize resource utilization.
- the CORDIC modules were designed to approximately minimize gate count by performing CORDIC process iterations in each half of the clock cycle, however the Stage Controllers are designed to use full clock cycles for reduced complexity.
- 2 sets of 2D CORDIC elementary rotation equations may be computed in the same single stage.
- the same set of 16-bit signed adders can be used twice having a input multiplexer to select inputs to the set of adders, with the clock signal acts as the multiplex select control signal.
- the inputs corresponding to the first set of elementary equations are passed to the adders.
- the adder outputs, from the first half of the clock cycle processing, are used as the adder inputs for the second half of the clock cycle.
- the present embodiment meets the QRD processing latency specification of 40 cycles, while improving resource utilization and gate count.
- the last stage of the 2D CORDIC processor, Householder 3D processor and 4D/2D configurable CORDIC processor may include a mechanism to compensate for implicit CORDIC processing gain.
- the compensation of the CORDIC processing gain is approximating using bit shift and addition, instead of signed multipliers. This approximation, in turn, introduces errors in gain compensation.
- the amount of percentage errors depends on whether a 2D, Householder 3D, or 4D CORDIC processor is used.
- the maximum gain compensation has been found to be not greater than 2.45%.
- Output controller 200 b is the last stage in the pipelined architecture. Output controller 200 b may perform both inverse coarse rotation to compensate for the input coarse rotation and output scaling to compensate for the CORDIC processing gain. Output controller 200 b is configured to output a complex R matrix and complex z vectors.
- both input and output controllers 220 a , 220 b reads in or write out 1 complex number (e.g., 2 16-bit real numbers) each clock cycle, by following the scheduling shown in Table C.1 in Appendix B.
- 1 complex number e.g., 2 16-bit real numbers
- the CORDIC modules perform a large number of vectoring and rotation operations within a limited number of cycles.
- the number of cycles is a design specified concern and so is the gate count. That said, when implemented in an optimized fashion, the present embodiment allows for a small gate count with good performance.
- the 2D, 3D and 4D CORDIC processors are designed with a primary aim of achieving high throughput to meet the specified design criteria and then, as the secondary aim, gate count is reduced by using various strategies.
- the 2D, 3D and 4D CORDIC processors comprise multiple pipelined core stages, where at least one core stage is configured to implement one or more of the CORDIC elementary rotation operations in either vectoring or rotation mode of operation.
- the CORDIC processors also comprise at least one module to perform input coarse rotation, output inverse coarse rotation and output scaling to compensate for CORDIC processing gain.
- the last stage of 2D CORDIC processor, Householder 3D CORDIC processor, and 4D/2D configurable CORDIC processors includes a mechanism to compensate for implicit CORDIC processing gain. In order to reduce area and power requirements, as well as length of critical path, this compensation is approximated using bit shift and add operations, instead of signed multiplication. This approximation, in turn, introduces errors in the gain compensation. The amount of percentage errors depends on whether a 2D CORDIC processor, a Householder CORDIC processor or a 4D CORDIC processor is used.
- the gain compensation factor is not greater than 2.45%. Based on extensive MATLAB simulations, architectural decisions were made to use 8 CORDIC iterations and the two's complement data format for input, output and internal data with a word-length of 16 bits and 11 bits for the fractional part. Of course, other design choices are compatible with the present invention.
- One of the strategies used to achieve lower gate count is to use implicit angle transfer using the elementary rotation directions, rather than explicitly computing and transferring actual rotation angles. This results in a hardware savings of approximately 30%, since the hardware resource's in the angle datapath are removable. Also, since each CORDIC core stage performs a fixed shift, it is performable using re wiring of the input operands and hence the area intensive barrel shifters are obviated. Another hardware saving strategy is to re-use the CORDIC stages to perform more than one elementary rotation per stage. This reduces a number of pipelined stages and increases the datapath hardware utilization significantly.
- a CORDIC processor may include a gain scaling circuit having only an adder and a fixed shift circuit.
- Stage 1 includes a 2D un-rolled CORDIC processor 245 a and Stage 4 includes a 2D un-rolled CORDIC processor 245 d .
- the 2D CORDIC processor can complete 2 sets of conventional 2D CORDIC elementary rotations in a single clock cycle.
- a same set of 16-bit signed adders is used twice and multiplexers are used to select the input values to these adders, to implement one set of CORDIC equations in each half of the clock cycle.
- 2D CORDIC processor 245 a performs four 2D vectoring and twenty four 2D rotation operations
- Stage 4 2D CORDIC processor 245 d performs three 2D vectoring and twenty four 2D rotation operations, within 40 cycles.
- Stage 3 includes a 3D un-rolled CORDIC processor 245 c that can perform two sets of Householder 3D CORDIC elementary rotation processes within two clock cycles.
- FIG. 3 shows an exemplary logic schematic of a single stage of the Householder 3D un-rolled CORDIC processor, wherein the top two adders compute X 1 i+1 and the bottom two adders compute X 2 i+1 and X 3 i+1 , within a single clock cycle, using the Householder 3D CORDIC processes.
- the output values X 1 i+1 , X 2 i+1 and X 3 i+1 are then fed back as input values to the same stage, and the same procedure is used to compute X 1 i+2 , X 2 i+2 and X 3 i+2 , which serve as the final output values of the stage.
- the un-rolled 3D CORDIC processor is used in Stage 3 of the QRD core to perform one 3D vectoring and twelve 3D rotation operations.
- the four signed adders are used a total of 4 times, within 2 clock cycles, to implement the 2 iterations of the Householder 3D CORDIC equations.
- the multiplexers are controlled by the clock signal to provide appropriate inputs to the adders.
- the Householder 3D CORDIC processor can perform 1 3D Vectoring and 12 3D Rotation operations within 34 clock cycles.
- Stage 2 of QRD comprises a 4D/2D configurable un-rolled CORDIC processor that includes 8 single stages connected in series. Each of the 8 single stages is programmable to operate in either 4D or 2D mode. In the 2D mode of operation, each stage of the 4D/2D configurable CORDIC processor can perform four 2D Vectoring or Rotation operations in parallel, in a single clock cycle. In the 4D mode of operation, each stage can perform a single Vectoring or Rotation operation within a single clock cycle.
- FIG. 4 shows an exemplary schematic block diagram of a single stage 4D/2D configurable un-rolled CORDIC processor.
- the multiplexers select the input data and rotation directions for the adders according to the mode of operation (2D or 4D). Since, in the 4D mode of operation, each of these adders are used twice, the multiplexers are cascaded to select the adder inputs. For the 4D mode of operation, the adders are used to compute X 1 i+1 and X 2 i+1 in the first half of the clock cycle, and X 3 i+1 and X 4 i+1 in the second half of the clock cycle.
- the CORDIC processor performs Vectoring and Rotation operations on two sets 2D vectors, [X1i X2i]T and [X3i X4i]T, in parallel, in each half of the clock cycle.
- the adders compute [X1i+1 X2i+1]T in the first half of the clock cycle, for the first set of two 2D input vectors.
- the same process is repeated in the second half of the clock cycle to compute updated vectors for the second set of two 2D input vectors.
- the 4D/2D configurable CORDIC processor performs a total of one 4D vectoring, fourteen 4D rotation, three 2D vectoring and eighteen 2D rotation operations within 36 clock cycles.
- QRD QR Decomposition
- SIC Successive Interference Cancellation
- V-BLAST V-BLAST
- K-Best K-Best
- Sphere Decoding Several types of channel pre-processing operations run in parallel with MIMO detection, one of which is the QR Decomposition (QRD) of the estimated channel characteristic matrix.
- QRD is required by many types of MIMO detection schemes, such as Successive Interference Cancellation (SIC), V-BLAST, K-Best, Sphere Decoding and many other schemes.
- SIC Successive Interference Cancellation
- V-BLAST V-BLAST
- K-Best K-Best
- Sphere Decoding Sphere Decoding
- QR Decomposition is preferred for MIMO receivers, compared other matrix triangularization schemes, is because of the fact that the matrix Q generated by QR Decomposition is a unitary matrix, which helps to avoid the noise enhancement problem and keeps noise spatially white.
- the IEEE 802.16m and LTE-Advanced standards include applications with mobile speeds up to 350 km/h, maximum antenna configuration of 8 ⁇ 8 and Downlink peak data rates of up to 1 Gbps.
- the high-mobility applications involve dynamic and fast-varying channel environments, which require channel estimation and QR Decomposition to be performed very frequently, for every few channel uses.
- QRD Processing Latency which is formally defined as the number of cycles after which a new set of QRD outputs is ready.
- QRD power dissipation and silicon area as much as possible.
- the applications in the emerging 4G wireless standards require QRD implementations for decomposing large complex channel matrices, while minimizing QRD processing latency, silicon area and power consumption requirements.
- QR Decompositions are listed and implementation challenges are described.
- CORDIC algorithms that provide a low complexity method to implement vector rotations that are executed during QR Decomposition are then described.
- the QRD in accordance with the present, is then described and its computational complexity is analyzed.
- the overall VLSI architecture of the QRD core and functionality for each of the individual sub-blocks are subsequently described.
- the 3 basic methods for computing matrix QR Decomposition include: the Modified Gram-Schmidt Orthonormalization (MGS) algorithm, Householder transformations and Givens rotations.
- MGS Modified Gram-Schmidt Orthonormalization
- the MGS algorithm computes Q and R matrices, column by column, by using vector projection, norm and other computations, see “Matrix Computation,” G. H. Golub and C. F. V. Loan, John Hopkins University Press, 1996.
- MGS Modified Gram-Schmidt Orthonormalization
- the MGS algorithm computes Q and R matrices, column by column, by using vector projection, norm and other computations, see “Matrix Computation,” G. H. Golub and C. F. V. Loan, John Hopkins University Press, 1996.
- it offers lesser accuracy and numerical stability due to round-off errors and loss of orthogonality introduced during the vector projections onto planes.
- a straight-forward implementation of this algorithm requires multiplication, division and square-root operations, which lead to high implementation complexity and high computation
- Householder transformations can be used to transform the input channel matrix H to the final upper-triangular R matrix, by eliminating all of the elements below the diagonal in a column simultaneously, see “Matrix Computation,” G. H. Golub and C. F. V. Loan, John Hopkins University Press, 1996.
- a major disadvantage of Householder transformations, when used for QR De-composition is that since a Householder reflection operates on all of the matrix rows simultaneously, it is not straightforward to carry out multiple reflections in parallel, which could have helped to speed up the QR Decomposition process, see “Load balanced Parallel QR decomposition on Shared Memory Multiprocessor,” J. Boleng and M. Misra, Parallel Computing, vol. 27, pp. 1321-1345, September 2001.
- a straightforward VLSI implementation of the Householder algorithm requires multiplication, division and square-root operations, and hence leads to very high hardware complexity.
- Givens rotations have the capability of selectively annihilating individual matrix elements by rotating two-dimensional real or complex column vectors to align them with the pivot axis. Since Givens Rotations work on two matrix rows at a time, they can be more easily parallelized, to reduce the QR Decomposition processing latency.
- Application of Givens rotations to two-dimensional column vectors within the input H matrix can be implemented using either multiply-and-add operations or more commonly using the Coordinate Rotation Digital Computer (CORDIC) algorithm, see “A survey of CORDIC algorithms for FPGA based computers,” R. Andraka, Proc. of the 1998 ACM/SIGDA sixth international symposium on filed programmable gate arrays, pp. 191-200, February 1998.
- CORDIC Coordinate Rotation Digital Computer
- the Vectoring and Rotation modes of the CORDIC algorithm can be used to approximate vector rotation and hence perform Givens rotations using low-complexity shift and add operations. Hence, the capability of performing multiple Givens rotations in parallel, which in turn leads to higher throughput, as well as the lower hardware complexity of the CORDIC modules makes Givens rotations the method of choice for implementing QR Decomposition.
- QRD for a 4 ⁇ 4 complex matrix H is implemented using the conventional sequence of Givens rotations, which attains the processing latency of 67 cycles at 125 MHz clock frequency, and requires 54 KG in 0.25 ⁇ m CMOS technology. Furthermore, as is described in detail in below, the sequential nature of annihilations for the H i,j Re matrix elements and the large number of Rotation operations required for each element annihilation causes a throughput bottleneck. These factors will lead to high computational complexity, larger hardware requirements and high power dissipation for throughput-constrained systems. Hence, a QR Decomposition architecture designed using these schemes will not be suitable for use in MIMO receivers embedded within mobile devices, that essentially require signal processing blocks with low power dissipation and low silicon area.
- the Coordinate Rotation Digital Computer (CORDIC) algorithms described by J. Volder in “The CORDIC Trigonometric Computing Technique,” in IRE Trans. Electronic Computers, vol. 8, no. 3, pp. 330-334, September 1959, and extended by Walther in “A unified algorithm for elementary functions,” in Proc. AFIPS Spring joint Computing Conf., vol. 38, pp. 379-385, November 1971, provide the mechanism to perform vector rotations in hardware using low-complexity adders and shifters.
- the CORDIC algorithms in their Vectoring and Rotation modes, can be used to approximate 2D Givens rotations.
- the CORDIC algorithm rotates the input vector by a necessary angle to align the resulting vector with the X axis.
- the Rotation mode the input vector is rotated by the specified angle to attain updated co-ordinates of the vector after rotation.
- the output is a rotation angle and the norm of the original vector.
- the CORDIC algorithm in effect attempts to minimize the Y component of the updated vector at each incremental rotation, and hence it uses the sign of the residual Y component to determine the direction for the next rotation. Since the angle accumulator is initialized with zero and is updated at each incremental rotation, it will contain the traversed angle, i.e. the angle between the vector and the x-axis, at the end of the Vectoring operation.
- [X 0 Y 0 ] T and [X n Y n ] T represent the input and output vectors to the Vectoring process, respectively.
- a n represents the processing gain of the CORDIC algorithm, where n represents the number of CORDIC algorithm iterations.
- the angle accumulator is first initialized with the desired rotation angle.
- the direction of elementary rotations is determined so that the magnitude of the residual angle, in the angle accumulator, is diminished.
- Multi-dimensional Givens rotations operate on column vectors of dimensions larger than 2, to align them with the first axis (Vectoring operation) and then to apply the same rotation to rotate other vectors (Rotation operation).
- Vectoring operation the first axis
- Rotation operation the same rotation to rotate other vectors
- This approach increases the parallelism in the vector rotation operation by processing all components of the vector simultaneously.
- a generic way to implement multi-dimensional Givens rotations, for column vector dimensions 3 or larger is to use high-complexity multiply-and-accumulate based algorithms. From the VLSI implementation perspective, this results in reduced latency, however, leads to much larger hardware requirements.
- the CORDIC elementary rotation equations for 4D Givens rotations are shown in Eq.
- Householder transformations also provide the capability of annihilating multiple elements simultaneously by reflecting a multi-dimensional input vector onto a plane.
- a straightforward VLSI implementation of the Householder algorithm requires multiplication, division and square-root operations, and hence it leads to very high hardware complexity, see “Matrix Computation,” G. H. Golub and C. F. V. Loan, John Hopkins University Press, 1996.
- the publication “Householder CORDIC Algorithms,” IEEE Trans. on Computers, vol. 44, no. 8, pp. 990-1001, August 1995 presents a novel Householder CORDIC algorithms that use sequences of simple Householder reflections, which can be easily implemented using shift, carry-save-addition (CSA) and simple addition operations.
- CSA carry-save-addition
- Equation 5.8 shows the rotation equations for a single (i th ) iteration of the 3D Householder CORDIC algorithm.
- X 1 i+1 X 1 i (1 ⁇ 3*2 ⁇ 2i )+ X 2 i (2 ⁇ i+1 D 1 i )+ X 3 i (2 ⁇ i+1 D 2 i )+ X 4 i (2 ⁇ i+1 D 3 i )
- X 2 i+1 X 1 i (2 ⁇ i+1 D 1 i )+ X 2 i (1+2 ⁇ 2i )+ X 3 i ( ⁇ 2 ⁇ 2i+1 D 1 i D 2 i )+ X 4 i ( ⁇ 2 ⁇ 2i+1 D 1 i D 3 i )
- X 3 i+1 X 1 i ( ⁇ 2 ⁇ i+1 D 2 i )+ X 2 i ( ⁇ 2 ⁇ 2i+1 D 1 i D 2 i )+ X 3 i (1+2 ⁇ 2i )+ X
- FIG. 5 illustrates the Element Annihilation Sequence for the Conventional Givens Rotations QRD Scheme.
- QR Decomposition As described above, the three popular methods for computing QR Decomposition include the Modified Gram-Schmidt Orthonormalization (MGS) algorithm, Householder transformations and Givens rotations. Among these, the Givens rotations method is superior in terms of BER performance and hardware complexity, compared to the other two methods.
- QR Decomposition of the channel characteristic matrix H using the conventional sequence of Givens rotations as described by El-Amawy and Dharmarajan in “Parallel VLSI algorithm for stable inversion of dense matrices,” Computers and Digital Techniques, IEEE Proc., vol. 136, no. 6, pp. 575-580, November 1989, leads to an excessive amount of computations, since it does not exploit the symmetry between the adjacent columns of the H matrix.
- the Vectoring and Rotation operations corresponding to the annihilation of the H i,j Im elements can be performed in a completely parallel manner, since they operate on independent set of rows of the H matrix.
- the H matrix shown in FIG. 5 Givens rotations to annihilate the H 3,1 Im and H 4,1 Im elements will operate on row pairs 5, 6 and 7, 8 of the H matrix, respectively, and hence they can be executed in parallel.
- annihilation of the H i,j Re elements and their corresponding Rotation operations have to be performed sequentially.
- the Givens rotations to annihilate the H 3,1 Re and H 4,1 Re elements will operate on row pairs 3,5 and 5,7 of the H matrix, respectively, and hence they can not be performed in parallel.
- Another issue with the annihilation of H i,j Re elements is that the number of Rotation operations required corresponding to the annihilation of each H i,j Re elements is very large.
- Such a hybrid QR Decomposition scheme relieves the throughput bottleneck and reduces the hardware complexity by first decreasing the number of Rotation operations required and then by enabling their parallel execution. To achieve this, multiple H i,j Re elements are annihilated in parallel, by using Multi-dimensional Givens rotations and Householder trans-formations.
- Circuit complexity is reduced by implementing these multi-dimensional vector rotations using CORDIC algorithms that only utilize low-complexity shift and addition operations. Also, for the H i,j Im elements, that do allow parallel Vectoring and Rotation operations, the 2D Givens rotations can be used to perform annihilation with maximum parallelism and minimal complexity.
- Embodiments of the present invention use the special sequence of element annihilations, see “A low complexity complex QR factorization design for signal detection in MIMO OFDM systems,” Hwang and Chen, Proc. IEEE ISCAS 2008, pp. 932-935, May 2008, that keeps the symmetry between the adjacent columns of H intact. Hence, embodiments of the present invention will only need to perform Vectoring and Rotation operations on odd numbered columns of H, and the values for the elements in the even numbered columns can be derived directly, without any computations. Also, embodiments of the present invention use the Multi-dimensional CORDIC and Householder CORDIC algorithms, described above, to implement Multi-dimensional Givens rotations and Householder transformations for 3D and 4D vectors.
- the QR Decomposition scheme for 4 ⁇ 4 complex matrix is shown in Table I.
- the algorithm begins with annihilating the H i,j Im elements in the first column of the H matrix.
- the Vectoring and Rotation operations corresponding to the annihilation of the H i,j Im elements can be performed in a completely parallel manner, and hence the conventional 2D Givens rotations are used for these element annihilations.
- the algorithm uses 4D Givens rotations to annihilate the elements H 4,1 Re , H 3,1 Re and H 2,1 Re simultaneously.
- the conventional 2D Givens rotations are used once again to perform parallel annihilation of the H i,2 Im elements in the third column of the H matrix.
- the scheme then uses the 3D Householder CORDIC algorithm described in “Householder CORDIC Algorithms,” IEEE Trans. on Computers, vol. 44, no. 8, pp. 990-1001, August 1995 to annihilate H 4,2 Re and H 3,2 Re simultaneously.
- the effect of element annihilation is propagated to non-zero elements in rows 2, 3, 4 and 6, 7, 8 in parallel, and this further reduces the number of corresponding rotation operations by a factor of 2.
- the algorithm annihilates the H 3,5 Im , H 4,3 Im , H 4,3 Re and H 4,4 Re elements, in the order given, using the conventional 2D Givens rotations.
- FIG. 6 demonstrates the annihilation order used, in accordance with the embodiments of the present invention, where the number on top of each arrow shows the sequential step number in the annihilation process.
- the number “1” on top of arrows for H 1,1 Im , H 2,1 Im , H 3,1 Im and H 4,1 Im demonstrate that all of these four elements are annihilated in step 1 , in a completely parallel manner. Also, from FIG. 5 and FIG.
- QRD scheme in accordance with the embodiments of the present invention, is described above for decomposition of a 4 ⁇ 4 complex channel characteristic matrix H.
- it can be generalized to perform QR Decomposition of matrices of any size, by appropriately using the 2D and 4D CORDIC algorithms and the Householder 3D CORDIC algorithm.
- This generalization for QR Decomposition of an n ⁇ n complex matrix can be performed using the following:
- an extended QRD scheme for 6 ⁇ 6 complex channel matrix is shown in Table II.
- this example requires a total of 11 sequential steps that use either of 2D, Householder 3D or 4D CORDIC algorithms to nullify the elements of the input 6 ⁇ 6 complex H matrix, to convert it to an upper-triangular R matrix. Note that, according to Delosme and Hsiao in “CORDIC algorithms in four dimensions,” Advanced Signal Processing Algorithms, Architectures, and Implementations, Proc. SPIE, vol. 1348, no. 1., pp.
- the element annihilation sequence shown in Table II for QRD of 6 ⁇ 6 complex matrix uses the low-complexity 2D CORDIC algorithm described in “A survey of CORDIC algorithms for FPGA based computers,” R. Andraka, Proc. of the 1998 ACM/SIGDA sixth international symposium on filed programmable gate arrays, pp. 191-200, February 1998, to annihilate the necessary H i,j Im elements in parallel.
- embodiments of the present invention use the optimal number of 4D, Householder 3D and 2D CORDIC vector rotations, such that the number of sequential steps required to annihilate the necessary H i,j Re elements in each column is minimized.
- embodiments of the present invention annihilate a total of 5 H i,1 Re elements.
- an embodiment of the present invention uses the 4D CORDIC algorithm to annihilate H 6,1 Re H 5,1 Re , and H 4,1 Re elements simultaneously, and then uses the Householder 3D CORDIC algorithm to nullify the remaining 2 elements, H 3,1 Re and H 2,1 Re .
- all 5 elements in column 1 are annihilated using only 2 sequential steps, as opposed to 5 sequential steps required using the 2D CORDIC algorithm.
- a QRD scheme in accordance with embodiments of the present invention, requires 3 4D Vectoring, 24 4D Rotation, 2 Householder 3D Vectoring, 14 Householder 3D Rotation, 23 2D Vectoring and 80 2D Rotation operations to perform QRD of a 6 ⁇ 6 complex matrix.
- QRD of 4 ⁇ 4 complex matrix requires 1 4D Vectoring, 6 4D Rotation, 1 Householder 3D Vectoring, 4 Householder 3D Rotation, 11 2D Vectoring and 21 2D Rotation operations.
- QRD of an 8 ⁇ 8 complex matrix requires 7 4D Vectoring, 76 4D Rotation, 2 Householder 3D Vectoring, 14 Householder 3D Rotation, 39 2D Vectoring and 191 2D Rotation operations.
- a QRD scheme in accordance with embodiments of the present invention, for processing n ⁇ n complex matrices can be performed by appropriately utilizing the 2D, Householder 3D and 4D CORDIC algorithms, according to the rules mentioned above, depending on the type and number of element annihilations to be performed.
- a QRD scheme in accordance with embodiments of the present invention, reduces the number of sequential annihilation steps required significantly, and hence reduces the QRD processing latency and removes the throughput bottleneck, compared to the existing Givens rotations based QRD schemes.
- a QRD scheme in accordance with embodiments of the present invention, also utilizes the low-complexity CORDIC algorithms for two-dimensional and multi-dimensional vector rotations, that results in a substantial reduction in the computational complexity required for QRD calculation.
- QR Decomposition implementations for processing large complex channel matrices, while minimizing QRD processing latency, silicon area and power consumption requirements.
- the existing QRD schemes lead to high computational complexity, sequential throughput bottleneck and lack of parallelism.
- the published QRD VLSI implementations using these existing schemes, either lead to large QRD processing latency or to large silicon area and power requirements.
- a hybrid QR Decomposition scheme that uses a unique combination of Multi-dimensional Givens rotations, Householder trans-formations and the conventional 2D Givens rotations to reduce the computational complexity and achieve higher execution parallelism, in accordance with the present invention, is described above.
- QRD architecture that decomposes large channel matrices with minimal QRD processing latency, and also minimizes gate count and power consumption requirements as much as possible.
- an architecture with linear or triangular systolic arrays will require an extremely large amount of hardware resources, see “Triangular systolic array with reduced latency for QR-decomposition of complex matrices,” Maltsev, Pestretsov, Maslennikov, and Khoryaev, Proc. IEEE ISCAS 2006, pp. 1421-1424, May 2006.
- an iterative architecture where one or more CORDIC processors are used repeatedly to perform the complete QR Decomposition will have much smaller silicon area and power requirements, however, they will lead to very large QRD processing latency, due to the large number of Vectoring and Rotation operations that need to be done iteratively, see “Parametric minimum hardware QR-factoriser architecture for V-BLAST detection,” Sobhanmanesh and Nooshabadi, IEEE Proc. on circuits, devices and systems, vol. 153, no. 5, pp. 433-441, October 2006.
- embodiments of the present invention provide an efficient semi-pipelined semi-iterative architecture that uses un-rolled CORDIC processors iteratively, along with complex controllers, to maximize throughput and resource utilization, while minimizing the area and power requirements.
- the QRD architecture of the present invention attains a processing latency of merely 40 clock cycles at 278 MHz, while occupying 0.3 mm 2 core area (36 KG) and dissipating 48.2 mW at 1.32V supply.
- FIG. 7 shows the overall architecture of a QR Decomposition core, in accordance with one embodiment of the present invention.
- the overall architecture consists of a total of 6 pipelined stages, each with latency less than or equal to 40 cycles.
- the first stage is an Input Controller stage, that provides the interface with the preceding stage in the MIMO Receiver. This stage serves the purpose of reading in one 4 ⁇ 4 complex H matrix and four 4 ⁇ 1 complex y vectors every 40 clock cycles from the preceding stage.
- the Input Controller stage then stores the read data and uses them to supply appropriate input operands to the CORDIC processors.
- Both the Input Controller and the Output Controller blocks read in or write out 1 complex number (2 16-bit Real numbers) each cycle, by following the scheduling shown in Table C.1 in Appendix C.
- each of these four central stages also contains a multiplexor (MUX) bank (MuxBank) and a register bank (RegBank) in the datapath, in addition to the un-rolled CORDIC processors.
- MUX multiplexor
- RegBank register bank
- the MuxBank serves the purpose of selecting the input operands for the CORDIC processor in that stage every clock cycle.
- the RegBank at the output of each stage is used to re-direct the CORDIC outputs to appropriate registers and to hold them until the current stage completes its desired computations and all outputs are ready to be passed to the next stage as inputs.
- each of these stages contains an independent Stage Controller that controls the operation of the datapath modules, to enable them to per-form the required operations within the given number of clock cycles.
- the Stage Controller provides the select and other control signals to direct appropriate data in and out of the CORDIC processor every cycle.
- the Stage Controller also provides the required control signals to the CORDIC processors to control their mode of operation (Vectoring or Rotation), rotation direction transfers and re-use of the pipelined CORDIC stages to maximize resource utilization.
- the QRD architecture also contains a Global Controller that controls the overall operation of the complete QRD core. As mentioned, all 6 pipelined stages perform a certain fixed set of tasks every 40 clock cycles, independently of each other.
- the Global Controller contains a counter that provides a global count (from 1 to 40), in order to synchronize the operation of each of the 6 stages.
- the Global Controller also provides the required control signals to ensure correct functionality of the Input Controller and Output Controller blocks, as well as Stage Controller blocks within each central stage.
- the data format for input, output and internal data for the QR Decomposition core is signed numbers in two's complement format with a word-length of 16 bits and 11 bits for the fractional part.
- the Householder 3D CORDIC processor uses an extra bit for the integer part, and hence requires a word-length of 17 bits.
- These word-length and number of bits for fractional part were derived using extensive bit-true simulations, such that the BER loss relative to the floating-point result is minimized.
- the total latency of the architecture from input H and y matrices to output R and z matrices is 160 clock cycles.
- the QRD architecture processes a new set of H and y matrices, and produces a new set of R and z output matrices every 40 clock cycles.
- the CORDIC algorithm uses a series of shift and addition operations to evaluate many basic arithmetic and mathematical functions, see “A unified view of CORDIC processor design,” Wang, Piuri, and E. S. Jr. in Proc. of IEEE 39 th Midwest symposium on circuits and systems, vol. 2, pp. 852-855, August 1996. It is also very suitable for implementing Givens rotations, using its Vectoring and Rotation modes, see “A survey of CORDIC algorithms for FPGA based computers,” R. Andraka, Proc. of the 1998 ACM/SIGDA sixth international symposium on filed programmable gate arrays, pp. 191-200, February 1998. There are a number of ways to design the CORDIC processors, that implement the CORDIC algorithms. Hence, the architecture of the CORDIC processor, for the given application, depends on the latency and hardware resource constraints.
- a QR Decomposition architecture uses an un-rolled, deeply pipelined architecture with iterative stages to design the 2D, Householder 3D and 4D/2D Configurable CORDIC processors, with major modifications to reduce the gate count and the number of cycles required for complete Vectoring and Rotation operations.
- FIG. 8 shows the architecture of a CORDIC processor used in a QRD core, in accordance with embodiment of the present invention.
- the 2D, Householder 3D and 4D/2D Configurable CORDIC processors include multiple pipelined core stages, where each stage implements one or more of the CORDIC elementary rotation equations.
- Each CORDIC Core stage is designed to work in either Vectoring or Rotation mode, which in turn is controlled by the Stage Controller block.
- the CORDIC processors also include an input coarse rotation stage and an output stage that performs both inverse coarse rotation and output scaling. The architectures for these stages are shown in FIG. 9 and FIG. 10 , respectively.
- the CORDIC Vectoring and Rotation algorithms are limited to rotation angles between ⁇ /2 and + ⁇ /2, and hence for composite rotation angles larger than ⁇ /2, the input and output coarse rotation stages rotate the input and output vectors by ⁇ and + ⁇ , respectively. From a hardware perspective, this is implemented in the input coarse rotation stage by simply monitoring the sign of the input operands and negating (using the two's complement scheme) them, if required. Based on the input operands, the input coarse rotation stage generates the control signal “CoarseRot_Req”, which is then used by the output inverse coarse rotation stage to decide whether to perform inverse rotation or not.
- the output scaling stage scales the CORDIC outputs by a constant factor, in order to compensate for the CORDIC processing gain, described in sections above.
- the QRD architecture of the present invention approximates the scaling operation to reduce the circuit complexity. For example, for the 2D CORDIC case, implementation of the exact scaling by factor 0.6097 requires signed multipliers. However, approximation of this scaling by 2 ⁇ 1 +2 ⁇ 3 (0.6250) will allow its implementation with considerably lower circuit complexity, by only using hardwired shifts and signed addition, as shown in FIG. 10 . Similarly, the Householder 3D and 4D CORDIC processors use approximate scale factors of 0.1875 (2 ⁇ 3 +2 ⁇ 4 ) and 0.3125 (2 ⁇ 2 +2 ⁇ 4 ), respectively. The impact of these approximations on the BER performance is very minor, as is described below. Also, note that based on MATLAB simulations, architectural decisions were made to use 8 CORDIC iterations.
- the 2D CORDIC algorithm provides a method to implement the Vectoring and Rotation operations for Givens rotations.
- the CORDIC elementary rotation equations shown in Eq. (5.1), are used to implement both Vectoring and Rotation operations, where the elementary rotation direction is calculated using the input vector co-ordinates for the Vectoring case, and using the residual angle for the Rotation case.
- a single stage architecture, for the 2D CORDIC processor can be designed to be programmable to execute appropriate CORDIC equations, depending on its mode of operation (Vectoring or Rotation).
- FIG. 11 shows the generic single stage architecture for 2D un-rolled CORDIC processor, derived using equation (5.1). As shown, the architecture uses a ROM module and a large amount of hardware resources for the angle datapath.
- FIG. 12 illustrates a single stage architecture for the 2D un-rolled CORDIC processor according to one embodiment of the present invention.
- the single stage architecture resolves these issues using two major improvement strategies, namely implicit angle transfer and re-use of hardware resources for execution of multiple CORDIC iterations in a single clock cycle using the same single stage.
- the implicit angle transfer computes the elementary rotation directions in the Vectoring mode, stores them in the Stage Controller registers, and utilizes them directly in the Rotation mode of operation.
- the CORDIC processor does not need to explicitly compute the rotation angle in the Vectoring mode and does not need to utilize and keep track of it to derive the elementary rotation directions. This results in hardware savings of around 30%, since the adders, registers, MUXs and the ROM that make up the angle datapath for each CORDIC stage can be removed.
- Some embodiments of the present invention implement 2 sets of 2D CORDIC elementary rotation equations using the same single stage.
- the same set of 16-bit signed adders twice and MUXs are used to select inputs to these adders, with the clock signal acting as the MUX select signal.
- the inputs corresponding to the first set of elementary equations are passed to the adders.
- the adder outputs, from the first half of the clock cycle processing, are used as the adder inputs for the second half of the clock cycle.
- the elementary rotation directions are computed from the input operands, and are used to operate the signed adders in either addition or subtraction mode.
- each CORDIC single stage needs to perform fixed shift, it can be performed using re-wiring of the input operands and hence the area intensive Barrel Shifters can be removed.
- identical architectures of the 2D CORDIC processors are used in Stage 1 and Stage4 of the QR Decomposition core of the present invention. In Stage 1, it performs 4 2D Vectoring and 24 2D Rotation operations, and in Stage 3, it performs 3 2D Vectoring and 24 2D Rotation operations within 40 clock cycles.
- the 3D un-rolled CORDIC processor performs Vectoring and Rotation operations on three-dimensional column vectors (3 ⁇ 1 real-valued vectors) using the Householder 3D CORDIC elementary rotation equations, shown in equation (5.8).
- the 3D un-rolled CORDIC processor consists of 4 pipelined single stages, each of which implements 2 sets of Householder 3D elementary rotation equations, within 2 clock cycles.
- FIG. 13 shows the architecture of a single stage of the Householder 3D un-rolled CORDIC processor, with critical path highlighted according to an embodiment of the present invention. Note that this architecture also uses the same area saving strategies that were used for the 2D CORDIC processor, described above.
- the four signed adders are used a total of 4 times, within 2 clock cycles, to implement the 2 iterations of the Householder 3D CORDIC equations.
- the MUXs controlled by the clock signal, are used to provide appropriate inputs to the adders.
- the top two adders compute X 1 i+1 by adding the 4 terms in the first equation, shown in (5.8).
- the bottom two adders compute X 2 i+1 and X 3 i+1 , in each half of a single clock cycle.
- the outputs X 1 i+1 , X 2 i+1 and X 3 i+1 are then fed back as inputs to the same single stage, and the same procedure is used to compute X 1 i+2 , X 2 i+2 and X 3 i+1 , which serve as the final outputs of the single stage.
- the Householder 3D CORDIC processor is used in the QR Decomposition Stage 3, and it performs 1 3D Vectoring and 12 3D Rotation operations within 34 clock cycles.
- Stage 2 of the QR Decomposition core contains a 4D/2D configurable un-rolled CORDIC processor.
- This CORDIC processor consists of 8 pipelined single stages, each of which is programmable to operate in either 4D or 2D mode.
- each single stage of the 4D/2D configurable CORDIC processor can perform 4 2D Vectoring or Rotation operations in parallel, in a single clock cycle.
- In the 4D mode of operation it can perform a single Vectoring or Rotation operation, by implementing the 4 elementary rotation equations shown in 5.6, within a single clock cycle.
- FIG. 14 shows the architecture of a single stage of the 4D/2D configurable un-rolled CORDIC processor, with critical path highlighted.
- the MUXs select the input data and rotation directions for the adders according to the mode of operation (2D or 4D). Since, in the 4D mode of operation, each of these adders are used twice, the clock signal driven MUXs have also been cascaded to select the adder inputs. For the 4D mode of operation, the adders are used to compute X 1 i+1 and X 2 i+1 in the first half of the clock cycle, and to compute X 3 i+1 and X 4 i+1 in the second half of the clock cycle.
- the CORDIC processor performs Vectoring and Rotation operations on two sets 2D vectors, [X 1 i X 2 i ] T and [X 3 i X 4 i ] T , in parallel, in each half of the clock cycle.
- the adders compute [X 1 i+1 X 3 i+1 ] T and [X 3 i+1 X 4 i+1 ] T in the first half of the clock cycle, for the first set of two 2D input vectors.
- the same process is repeated in the second half of the clock cycle to compute updated vectors for the second set of two 2D input vectors.
- the 4D/2D configurable un-rolled CORDIC processor performs a total of 1 4D Vectoring, 14 4D Rotation, 3 2D Vectoring and 18 2D Rotation operations within 36 clock cycles. This makes Stage 2 the most computation and hardware intensive stage within the complete QR Decomposition core. Also, due to the hardware intensive nature, the critical path of the single stage of the 4D/2D configurable CORDIC processor accounts for the critical path of the overall QR Decomposition core.
- QR Decomposition operation does not directly estimate the transmitted vector, and hence it does not have a direct impact on the BER performance.
- accuracy of the channel matrix QR Decomposition does have an effect on the MIMO detection process.
- the matrix R and symbol vectors z are then used by the MIMO detector to estimate the transmitted vectors ⁇ .
- These estimated transmitted vectors, ⁇ are then compared to the actual transmitted vectors, s, to quantize the BER performance of the MIMO Receiver (QRD+MIMO Detector).
- QR Decomposition will produce R matrix and z vectors that may not be exactly the same as the actual R and z attained mathematically (using ideal QRD) in floating-point format.
- Use of these perturbed R and z matrices for MIMO detection would lead to errors in estimating the transmitted vector ⁇ , which then results in BER performance degradation compared to ideal QRD.
- the QRD architecture uses approximations for the actual scale factors for compensating CORDIC processing gain, in order to simplify the VLSI implementation of the scaling operation.
- the scale factors 0.6097, 0.1896 and 0.3364 for 2D, Householder 3D and 4D CORDIC processors have been approximated with 0.6250 (2 ⁇ 1 +2 ⁇ 3 ), 0.1875 (2 ⁇ 3 +2 ⁇ 4 ) and 0.3125 (2 ⁇ 2 +2 ⁇ 4 ), respectively.
- these approximations might lead to increased inaccuracy in the resulting R matrix and z vectors, and hence might cause BER performance degradation.
- the CORDIC algorithms are utilized to perform vector rotation.
- the accuracy of the vector rotations depends on the number of iterations used for the CORDIC algorithm. In other words, a larger number of CORDIC iterations will lead to better accuracy, however, will also lead to larger hardware complexity.
- the MATLAB models for the QRD of the present invention were simulated with different number of CORDIC iterations.
- FIG. 16 shows the BER curves attained using these MATLAB simulations.
- QRD using 6 CORDIC iterations leads to a significant BER performance degradation, compared to QRD with 8 CORDIC iterations.
- use of 10 CORDIC iterations leads to a much higher computational complexity, which results in either large QRD processing latency or large hardware and power requirements. This justifies using 8 iterations for 2D, Householder 3D and 4D/2D configurable CORDIC processors.
- FIG. 17 shows the BER curves obtained by simulating the combination of QR Decomposition and K-Best MIMO Detector for different QRD schemes.
- the QR Decomposition MATLAB models use 8 CORDIC iterations and the scale factors of 0.6250, 0.1875 and 0.3125 for 2D, Householder 3D and 4D CORDIC processors, respectively. From FIG. 17 , it can be noticed that the BER performance for the QR Decomposition scheme is identical to that of the QRD scheme using the conventional sequence of Givens rotations, for both floating-point and fixed-point models.
- FIG. 17 also shows the BER curve for QR Decomposition using ideal Givens rotations, implemented in floating-point arithmetic (as opposed to implementing them using the CORDIC algorithm). It can be noticed that the BER performance for QRD using ideal Givens rotations is marginally better compared to that when Givens rotations are implemented using the CORDIC algorithm. This can be explained by the fact that the CORDIC algorithm just approximates actual vector rotations, with the accuracy dependent on the number of CORDIC algorithm iterations used and the compensation scale factors used.
- a QR Decomposition core in accordance with the present invention, was fabricated in a 0.13 ⁇ m IBM 1P8M CMOS process and was tested using an Agilent(Verigy) 93000 SoC high-speed digital tester and a Temptronic TP04300 thermal forcing unit.
- the die micrograph for the QRD chip is shown in FIG. 18 .
- the test setup consisting of the 93K SoC tester, Temptronic TP04300 thermal forcing unit, load board and the DUT is shown in FIG. 19 .
- the nominal core supply voltage is 1.2 V, whereas the I/O voltage is 2.5 V.
- the functionality of the QRD core was verified by generating and passing channel matrices and received symbol vectors at different SNR values to the chip through the tester and comparing the QRD outputs with the expected values from the bit-true simulations both from MATLAB and Verilog HDL simulations.
- the BER performance of the QRD core was measured as follows:
- FIG. 20 shows a Shmoo plot depicting the maximum operating frequency and the total power dissipation of the design versus the supply voltage at 25° C.
- a total of five chips were tested, where the average and the max/min values of the achieved frequency have been shown in FIG. 20 .
- the detailed measurement results are presented in Appendix D in Table D.1 to Table D.15.
- the QRD design operates at a clock rate up to 278 MHz and consumes 48.2 mW of power.
- the temperature was forced to be at 25° C. using the Temptronic TP04300 thermal forcing unit.
- test results at 0° C. and 85° C. yield clock rates of 292 MHz and 254 MHz, while dissipating 51.5 mW and 43.7 mW, respectively, at 1.32V supply.
- the complete measurement results at these temperatures have been presented in Appendix D.
- Table IV shows the measured results for the QRD chip of the present invention and compares it to other published state-of-the-art QR Decomposition implementations for decomposing 4 ⁇ 4 matrices.
- MMSE QR Decomposition design presented in “VLSI Implementation of a high-speed iterative sorted MMSE QR decomposition.” P. Luethi, A. Burg, S. Haene, D. Perels, N. Felber, and W. Fichtner, Proc. IEEE ISCAS 2007, pp. 1421-1424, May 2007, new Q and R matrices are produced every 67 cycles, running at 125 MHz, and the total core area required is 54 KG.
- QR Processing Efficiency As can be noticed from Table IV, some of the reference QRD chips have been designed for processing matrices with dimensions other than 4 ⁇ 4 complex. Hence, to allow fair comparison, we introduce a new figure of merit, QR Processing Efficiency, as follows:
- FIG. 21 shows the QR Processing Efficiency comparison between the reference QRD chips and the QRD in accordance with the present invention.
- Each hyperbola in FIG. 21 represents a constant value of QR Processing Efficiency (computed by taking the reciprocal of the product of the two axes) for each QRD design. Note that since QR Processing Efficiency is the reciprocal of the product of the two axes, the distance of the hyper-bola to the origin is inversely proportional to the QR Processing Efficiency metric.
- the QRD core of the present invention provides a 3.6 ⁇ reduction in processing latency (for 4 ⁇ 4 complex case) and a 2.5 ⁇ increase in QR Processing Efficiency, compared to the best reported design referenced in “Complex-valued QR decomposition implementation for MIMO receivers,” by P. Salmela, A. Burian, H. Sorokin, and J. Takala in Proc. IEEE ICASSP 2008, pp. 1433-1436, April 2008.
- QR Decomposition implementations are required that decompose large complex channel matrices with minimum possible processing latency, silicon area and power consumption requirements.
- the state-of-the-art QRD implementations cause high computational complexity and throughput bottlenecks, which leads to either large QRD Processing Latency or to large area and power requirements.
- Embodiments of the present invention provide a hybrid QR Decomposition scheme that reduces the number of computations required and increases their execution parallelism by using a unique combination of Multi-dimensional Givens rotations, Householder transformations and Conventional 2D Givens rotations. The computational complexity is further reduced by using the CORDIC algorithm to implement these multi-dimensional vector rotations.
- a semi-pipelined semi-iterative architecture is presented for the QRD core, that uses innovative design ideas to develop 2D, Householder 3D and 4D/2D Configurable CORDIC Processors, such that they can perform the maximum possible number of Vectoring and Rotation operations within the given number of cycles, while minimizing gate count and maximizing resource utilization.
- the test results for the QRD chip demonstrate that the QRD chip attains the lowest reported processing latency of 40 clock cycles (144 ns) at 278 MHz for 4 ⁇ 4 complex matrices at room temperature. It also outperforms all of the previously published QRD designs by offering the highest QR Processing Efficiency, while consuming only 0.3 mm silicon area and 48.2 mW.
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Abstract
Description
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- “Complex-valued QR decomposition implementation for MIMO receivers,” in Proc. IEEEICASSP 2008, pp. 1433-1436, April 2008, P. Salmela, A. Burian, H. Sorokin, and J. Takala;
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However, since this QRD scheme uses an approximation to an actual function, for fixed-precision arithmetic, it might lead to a degradation in the bit error rate (BER) performance of the MIMO detector. Furthermore, since the QRD core presented in [34] uses an iterative architecture, it incurs a very large processing latency. In 0.13 μm CMOS, this QRD design requires a QRD processing latency of 139 clock cycles at 269 MHz and requires only 23.3 KG silicon area.
X i+1 =X i−2−1 D i Y i
Y i+1 =Y i−2−i D i X i
θi+1=θi −D i tan−1(2−i) (5.1)
where, Di=−sign(Yi), see “A survey of CORDIC algorithms for FPGA based computers,” R. Andraka, Proc. of the 1998 ACM/SIGDA sixth international symposium on filed programmable gate arrays, pp. 191-200, February 1998. Thus, if the Vectoring operation is completed so that the residual Y component is zero, we have:
X n =A n√{square root over ((X 0)2+(Y 0)2)}{square root over ((X 0)2+(Y 0)2)}
Y n=0
θn=tan−1(Y 0 /X 0)
A n=Π√{square root over (1+2−2i)} (5.2)
See, “A survey of CORDIC algorithms for FPGA based computers,” R. Andraka, Proc. of the 1998 ACM/SIGDA sixth international symposium on filed programmable gate arrays, pp. 191-200, February 1998. Note, that here [X0Y0]T and [XnYn]T represent the input and output vectors to the Vectoring process, respectively. Also, An represents the processing gain of the CORDIC algorithm, where n represents the number of CORDIC algorithm iterations.
X n =A n [X 0 cos θ0 −Y 0 sin θ0]
Y n =A n [Y 0 cos θ0 −X 0 sin θ0]
θn=0
A n=Π√{square root over (1+2−2i)} (5.3)
Note, that the CORDIC algorithms approximate the actual vector rotations by using a series of successively smaller elementary rotations by angles tan−12−i. Hence, there is a direct trade-off between n, the number of CORDIC algorithm iterations, the accuracy of the vector rotations and computational complexity of the rotation operation. In other words, an increase in the value of n improves the vector rotation accuracy, however, it leads to larger computational complexity, and hence larger resource requirements.
Multi-Dimensional CORDIC Algorithm
X 1 i+1 =X 1 i(1−2−2i)+X 2 i(
X 2 i+1 =X 1 i(−
X 3 i+1 =X 1 i(−
where, the rotation directions are calculated as: D1 i=sign(X1 i·X2 i) and D2 i=sign(X1 i·X3 i). Also, the CORDIC processing gain for the 3D CORDIC algorithm can be calculated using the following equation, for n iterations of this 3D CORDIC algorithm:
A n=Π1+3*2−2i (5.5)
The CORDIC elementary rotation equations for 4D Givens rotations are shown in Eq. 5.6 below:
X 1 i+1 =X 1 i−2i D 1 i X 2 i−2−i D 2 i X 3 i2−i D 3 i X 4 i
X 2 i+1=2−i D 1 i X 1 i +
X 3 i+1=2−i D 1 i X 1 i−2−i D 3 i X 2 i +
X 4 i+1=2−i D 3 i X 1 i+2−i D 2 i X 2 i−2−i D 1 i X 3 i +X 4 i (5.6)
where, the rotation directions are calculated as: D1 i=−sign(X1 i·X2 i), D2 i=−sign(X1 i·X3 i) and D3 i=−sign(X1 i·X4 i). Also, the CORDIC processing gain can be given as:
A n=Π√{square root over (1+3*2−2i)} (5.7)
Since these 3D and 4D CORDIC algorithms can annihilate multiple elements simultaneously (2 elements for the 3D case and 3 elements for the 4D case) using only shift and addition operations, they offer a significant reduction in hardware complexity, as well as reduction in the overall processing latency. The details about hardware implementation of these equations to develop 3D and 4D CORDIC processors are described below.
Householder CORDIC Algorithm
X 1 i+1 =X 1 i−2−2i+1 X 1 i+2−2i+1 D 1 i X 2 i+2−i+1 D 2 i X 3 i
X 2 i+1=−2−i+1 D 1 i X 1 i +X 2 i−2−2i+1 D 1 i D 2 i X 3 i
X 3 i+1=−2−i+1 D 2 i X 1 i−2−2i+1 D 1 i D 2 i X 2 i +X 3 i (5.8)
where, the rotation directions can be obtained from the input operands as: D1 i=sign(X1 i·X2 i) and D2 i=sign(X1 i·X3 i). Also, the CORDIC processing gain for the 3D Householder CORDIC algorithm can be calculated using the following equation:
A n=Π1+2−2i+1 (5.9)
X 1 i+1 =X 1 i(1−3*2−2i)+X 2 i(2−i+1 D 1 i)+X 3 i(2−i+1 D 2 i)+X 4 i(2−i+1 D 3 i)
X 2 i+1 =X 1 i(2−i+1 D 1 i)+X 2 i(1+2−2i)+X 3 i(−2−2i+1 D 1 i D 2 i)+X 4 i(−2−2i+1 D 1 i D 3 i)
X 3 i+1 =X 1 i(−2−i+1 D 2 i)+X 2 i(−2−2i+1 D 1 i D 2 i)+X 3 i(1+2−2i)+X 4 i(−2−2i+1 D 2 i D 3 i)
X 4 i+1 =X 1 i(−2−i+1 D 3 i)+X 2 i(−2−2i+1 D 1 i D 3 i)+X 3 i(−2−2i+1 D 2 i D 3 i)+X 4 i(1+2−2i) (5.10)
where, the rotation directions can be obtained from the input operands as: D1 i=sign(X1 i·X2 i), D2 i=sign (X1 i·X3 i) and D3 i=sign (X1 i·X4 i). Also, the CORDIC processing gain for the 4D Householder CORDIC algorithm can be calculated using the following equation, for n iterations of this 4D Householder CORDIC algorithm:
A n=Π1+3−2i+1 (5.11)
TABLE I | |
1) | Annihilate H1,1 Im, H2,1 Im, H3,1 Im and H4,1 Im using 2D CORDIC |
algorithm. | |
2) | Annihilate (H2,1 Re, H3,1 Re, H4,1 Re) using 4D CORDIC algorithm. |
3) | Annihilate H2,2 Im, H3,2 Im and H4,2 Im in parallel using 2D CORDIC |
algorithm. | |
4) | Annihilate (H3,2 Re, H4,2 Re) using |
algorithm. | |
5) | Annihilate H3,3 Im and H4,3 Im using 2D CORDIC algorithm. |
6) | Annihilate H4,3 Re using 2D CORDIC algorithm. |
7) | Annihilate H4,4 Im using 2D CORDIC algorithm. |
-
- 1. For element annihilations that operate on independent sets of rows of H and can be parallelized, use the conventional 2D CORDIC algorithm to attain maximum parallelization and minimal computational complexity;
- 2. For sequential element annihilations that use common pivot rows, use
Householder 3D CORDIC and 4D CORDIC algorithms to nullify these elements simultaneously, and hence reduce latency by a factor of 2 and 3, respectively, and also remove the throughput bottleneck.
TABLE II | |
1) | Annihilate H1,1 Im, H2,1 Im, H3,1 Im, H4,1 Im, H5,1 Im and H6,1 Im in parallel using 2D |
CORDIC algorithm. | |
2) | Annihilate (H6,1 Re, H5,1 Re, H4,1 Re) using 4D CORDIC algorithm. |
3) | Annihilate (H3,1 Re, H2,1 Re) using |
4) | Annihilate H2,2 Im, H3,2 Im, H4,2 Im, H5,2 Im and H6,2 Im in parallel using 2D CORDIC |
algorithm. | |
5) | Annihilate (H6,2 Re, H5,2 Re, H4,2 Re) using 4D CORDIC algorithm. |
6) | Annihilate H3,2 Re using 2D CORDIC algorithm. |
7) | Annihilate H3,3 Im, H4,3 Im, H5,3 Im and H6,3 Im in parallel using 2D CORDIC |
algorithm. | |
8) | Annihilate (H6,3 Re, H5,3 Re, H4,3 Re) using 4D CORDIC algorithm. |
9) | Annihilate H4,4 Im, H5,4 Im and H6,4 Im in parallel using 2D CORDIC algorithm. |
10) | Annihilate (H6,4 Re, H5,4 Re) using |
11) | Annihilate H5,5 Im and H6,5 Im in parallel using 2D CORDIC algorithm. |
12) | Annihilate H6,5 Re using 2D CORDIC algorithm. |
13) | Annihilate H6,6 Im using 2D CORDIC algorithm. |
TABLE III | |
Number of Operations Required | |
Operation | for n × n Complex Matrix |
4D Vectoring | |
4D Rotation | |
Householder 3D Vectoring | |
Householder 3D Rotation | |
2D Vectoring | |
2D Rotation | |
QR Decomposition—Overall Architecture Description
- 1. Complex-valued random Gaussian channel characteristic matrix, updated every four channel uses, was generated and was used to transmit the symbol vectors.
- 2. For a given SNR value, additive white Gaussian noise with the desired variance was generated and was used along with the channel matrix to derive the received symbol vectors.
- 3. A test vector, including the input channel matrix and received symbols, as well as all the required control and enable signals, was generated using MATLAB.
- 4. This generated test vector was then converted to a VCD file using ModelSim, a Verilog HDL simulator.
- 5. The V93K TestGenerator tool, see “How to migrate HDL Design to ATE Test Plan Quickly and Efficiently—The V93K_TestGenerator Tool”, by Dimpesh Patel, Glenn Gulak, and Jeetendar Narsinghani, Jun. 27, 2008, was then used to convert the test vector VCD file to timing files (“.tim”), configuration files (“.pin”), and binary test vector files (“.binl”) required for testing.
- 6. The core supply voltage along with the I/O supply voltage are set appropriately.
- 7. These files were loaded onto the V93K SoC tester and were used to supply input test vectors to the QRD chip.
- 8. An at-speed test was run on the QRD chip and the outputs are compared against the desired bit stream generated by the MATLAB simulation.
TABLE IV | |||||
Reference | [34]-2008 | [33]-2007 | [47]-2009 | [36]-2007 | This work |
Process | 0.13 μm | 0.18 μm | 0.18 μm | 0.25 μm | 0.13 μm |
QRD | MGS | MGS | MGS | Givens | Hybrid |
Algorithm | Rot | ||||
Used | |||||
|
4 × 4 | 4 × 4 | 4 × 4 | 4 × 4 | 4 × 4 |
Size | Complex | Real | Real | Complex | Complex |
QRD | Real | Real | Real | Complex | Real |
Processing | |||||
Mode | |||||
QRD | 139 cycles | 67 cycles | 44 cycles | 67 |
40 cycles |
Processing | |||||
Latency | |||||
Max Clock | 269 MHz | 277 MHz | 270 MHz | 125 MHz | 278 MHz |
Frequency | |||||
QRD | 516 ns | 241 ns | 162 ns | 536 ns | 144 ns |
Processing | |||||
Latency [ns] | |||||
Core Area | 23.2 KG | 72 KG | 51 KG | 54 |
36 KG |
QRD | 5.346 | 0.923 | 1.936 | 2.212 | 12.352 |
Processing | |||||
Efficiency | |||||
(1/ns · KG) | |||||
(×103) | |||||
Tested Chip | No | No | No | No | Yes |
Power | N/A | N/A | N/A | N/A | 48.2 mW |
Consumption | @ | ||||
1.32V | |||||
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