US9311099B2 - Systems and methods for locking branch target buffer entries - Google Patents
Systems and methods for locking branch target buffer entries Download PDFInfo
- Publication number
- US9311099B2 US9311099B2 US13/955,106 US201313955106A US9311099B2 US 9311099 B2 US9311099 B2 US 9311099B2 US 201313955106 A US201313955106 A US 201313955106A US 9311099 B2 US9311099 B2 US 9311099B2
- Authority
- US
- United States
- Prior art keywords
- branch target
- target buffer
- entries
- lock
- indicator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active, expires
Links
- 239000000872 buffer Substances 0.000 title claims abstract description 105
- 238000000034 method Methods 0.000 title claims description 21
- 238000012545 processing Methods 0.000 claims abstract description 39
- 230000004044 response Effects 0.000 claims abstract description 18
- 239000004020 conductor Substances 0.000 description 29
- 230000015654 memory Effects 0.000 description 15
- 230000002457 bidirectional effect Effects 0.000 description 12
- 230000008569 process Effects 0.000 description 11
- 230000002093 peripheral effect Effects 0.000 description 9
- 230000008901 benefit Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 230000010365 information processing Effects 0.000 description 3
- 230000000875 corresponding effect Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000004590 computer program Methods 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000005294 ferromagnetic effect Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000005291 magnetic effect Effects 0.000 description 1
- 238000007726 management method Methods 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000012913 prioritisation Methods 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000026676 system process Effects 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
- G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
Definitions
- This disclosure relates generally to data processors, and more specifically, to the execution of branch instructions by data processors.
- branch target buffer With embedded processing systems, area required by a circuit is a key metric to optimize. In doing so, generally a smaller branch target buffer is preferred to a larger one. In many cases, a small branch target buffer works fine in accelerating a majority of the branches. However, there are also instances of code where the number of branches is large and the branches are executed only once (referred to as “one and done”). In these cases, the usefulness of the branch target buffer is effectively zero when the size of the branch target buffer is less than the number of taken branches due to the constant thrashing of the branch target buffer contents.
- FIG. 1 illustrates in block diagram form a data processing system having a branch target buffer in accordance with one form of the present invention
- FIG. 2 illustrates in block diagram form a portion of a central processing unit (CPU) of the data processing system of FIG. 1 in accordance with one form of the present invention
- FIG. 3 illustrates in block diagram form a portion of the branch target buffer of FIG. 1 in accordance with one form of the present invention
- FIG. 4 illustrates in diagrammatic form a first embodiment of an entry in the branch target buffer of FIG. 1 corresponding to a group of fetched data processing instructions in accordance with the present invention
- Embodiments of systems and methods disclosed herein provide capability to lock the contents of some or all of the entries in a branch target buffer when a specified number (or percentage) of the entries are occupied.
- the ability to lock the contents can apply to all styles of branch target buffers including direct mapped, fully associative, and set associative. For set associative, the lock can occur once all ways of a set are valid, such that no replacements can occur.
- a portion of the branch target buffer can be allowed to lock, while the remaining portion could be replaceable. Instead of not gaining any performance advantage with the branch target buffer, some performance advantage can still occur due to having locked in a subset of the total number of unique taken branches, as further described herein.
- FIG. 1 illustrates, in block diagram form, a data processing system 10 that can be used to implement various embodiments of the present disclosure.
- Data processing system 10 includes a processor 12 , a system bus 14 , a memory 16 and a plurality of peripherals such as a peripheral 18 , a peripheral 20 and, in some embodiments, additional peripherals as indicated by the dots in FIG. 1 separating peripheral 18 from peripheral 20 .
- the memory 16 is a system memory that is coupled to the system bus 14 by a bidirectional conductor that, in one form, has multiple conductors. In the illustrated form each of peripherals 18 and 20 is coupled to the system bus 14 by bidirectional multiple conductors as is the processor 12 .
- the processor 12 includes a bus interface unit 22 that is coupled to the system bus 14 via a bidirectional bus having multiple conductors.
- the bus interface unit 22 is coupled to an internal bus 24 via bidirectional conductors.
- the internal bus 24 is a multiple-conductor communication bus. Coupled to the internal bus 24 via respective bidirectional conductors is a cache 26 , a branch target buffer (BTB) 28 , a central processing unit (CPU) 30 and a memory management unit (MMU) 32 .
- the CPU 30 is a processor for implementing data processing operations. Within the CPU 30 is a control register 31 which stores values for branch to buffer lock control and lock amount signals, among others.
- Each of cache 26 , BTB 28 , CPU 30 and MMU 32 are coupled to the internal bus via a respective input/output (I/O) port or terminal.
- the processor 12 functions to implement a variety of data processing functions by executing a plurality of data processing instructions.
- Cache 26 is a temporary data store for frequently-used information that is needed by the CPU 30 .
- Information needed by the CPU 30 that is not within cache 26 is stored in memory 16 .
- the MMU 32 controls interaction of information between the CPU 30 and the cache 26 and the memory 16 .
- the bus interface unit 22 is only one of several interface units between the processor 12 and the system bus 14 .
- the bus interface unit 22 functions to coordinate the flow of information related to instruction execution including branch instruction execution by the CPU 30 . Control information and data resulting from the execution of a branch instruction are exchanged between the CPU 30 and the system bus 14 via the bus interface unit 22 .
- the BTB 28 is a buffer for storing a plurality of entries. Each of the entries corresponds to a fetch group of branch target addresses associated with branch instructions that are executed by the CPU 30 . Therefore, CPU 30 selectively generates branch instruction addresses which are sent via the internal bus 24 to the BTB 28 .
- the BTB 28 contains a subset of all of the possible branch instruction addresses that may be generated by CPU 30 .
- the BTB 28 In response to receiving a branch instruction address from CPU 30 , the BTB 28 provides a branch target address to the CPU 30 that corresponds to a branch instruction within a plurality of instructions.
- the branch target address which the BTB 28 provides is both a valid address and may be predicted to be taken.
- FIG. 2 Illustrated in FIG. 2 is a detailed portion of the CPU 30 of FIG. 1 that relates to the execution of instructions and the use of the BTB 28 .
- An instruction fetch unit 40 is illustrated as including both an instruction buffer 44 and an instruction register 42 .
- the instruction buffer 44 has an output that is connected to an input of the instruction register 42 .
- a multiple conductor bidirectional bus couples a first output of the instruction fetch unit 40 to an input of an instruction decode unit 46 for decoding fetched instructions.
- An output of the instruction decode unit 46 is coupled via a multiple conductor bidirectional bus to one or more execution unit(s) 48 .
- the one or more execution unit(s) 48 is coupled to a register file 50 via a multiple conductor bidirectional bus.
- each of the instruction fetch units 40 , the instruction decode unit 46 , the one or more execution unit(s) 48 and the register file 50 is coupled via separate bidirectional buses to respective input/output terminals of a control and interface unit 52 that interfaces to and from the internal bus 24 .
- the control and interface unit 52 has address generation circuitry 54 having a first input for receiving a BTB Hit Indicator signal via a multiple conductor bus from the branch target buffer 28 via the internal bus 24 .
- the address generation circuitry 54 also has a second input for receiving a BTB Target Address via a multiple conductor bus from the MMU 32 via the internal bus 24 .
- the address generation circuitry 54 has a multiple conductor output for providing a branch instruction address signal to the branch target buffer 28 via the internal bus 24 , and single conductor outputs for providing lock control and lock amount signals to branch target buffer 28 .
- Other data and control signals can be communicated via single or multiple conductors between the control and interface unit 52 and the internal bus 24 for implementing data processing instruction execution, as required.
- the control and interface unit 52 controls the instruction fetch unit 40 to selectively identify and implement the fetching of instructions including the fetching of groups of instructions.
- the instruction decode unit 46 performs instruction decoding for the one or more execution unit(s) 48 .
- the register file 50 is used to support the one or more execution unit(s) 48 .
- address generation circuitry 54 Within the control and interface unit 52 is address generation circuitry 54 .
- the address generation circuitry 54 sends out a branch instruction address to the BTB 28 to obtain multiple instructions.
- a BTB target address is provided to the CPU 30 to identify an address of a group of instructions.
- the BTB target address is used by CPU 30 to obtain an operand at the target address from either cache 26 or from memory 16 if the address is not present and valid within cache 26 .
- a register 60 stores (N+1) BTB entries 64 where N is an integer.
- the register 60 has an input/output terminal coupled to an input/output terminal of a BTB control circuit 62 via a bidirectional multiple conductor bus.
- the BTB control circuit 62 also has inputs for receiving the branch instruction address, lock control, and lock amount signals from the CPU 30 .
- BTB control circuit 62 includes lock control logic 66 , which sets lock indicators for the entries in BTB register 60 based on the lock control indicator and lock amount signal from the CPU 30 and a fullness level of the BTB register 60 .
- BTB control circuit 62 provides the BTB Hit Indicator and the BTB Target Address signals.
- a branch instruction address is received from the CPU 30 .
- the BTB control circuit 62 determines whether the requested branch instruction address exists in the register 60 . If so, the BTB Hit Indicator signal is asserted. If not, the BTB Hit Indicator is not asserted and the CPU 30 determines that the MMU 32 needs to provide the BTB Target Address associated with the Branch instruction address. The missing entry is typically provided from the memory 16 . In addition to asserting the BTB Hit Indicator signal, the BTB control circuit 62 retrieves the requested BTB Target Address from the correct entry and outputs the BTB Target Address to the CPU 30 .
- the BTB control circuit 62 may fill the unlocked BTB entry 64 with the branch instruction address, corresponding branch target address once available from the CPU 30 , as well as other information including a lock indicator for the entry 64 .
- lock control logic 66 reads the lock control signal to determine whether to lock any of the entries in BTB register 60 . If the lock control signal indicates that locking is enabled, lock control logic 66 determines the percentage or number of entries 64 to lock using the lock amount signal. For example, the lock amount signal may be set to a percentage such as 25%, 50%, 75%, 100%, or other suitable percentage.
- the lock amount may be set to a particular number that is less than or equal to the total number of entries 64 in BTB register 60 .
- Lock control logic 66 keeps track of the number or percentage of entries 64 that occupy BTB register 60 . Once the number or percentage of entries equals the lock amount signal, then the current entries 64 are locked and cannot be used to store information for a new entry. Information in remaining unlocked entries 64 , if any, may still be overwritten with new information. Once locked, entries 64 remain locked as long as the current set of instructions or routine continues executing. If CPU 30 starts executing a new set of program instructions or routine, entries 64 in BTB register 60 are flushed and invalidated, which also causes any locked entries 64 to be unlocked.
- FIG. 4 Illustrated in FIG. 4 is a first embodiment of a BTB entry 64 in the register 60 of FIG. 3 .
- the entry 64 can have any suitable number of bits that are allocated in fields for a Branch Instruction Address, a Branch Target Address, a LOCK indicator, a predicted (PRED) indicator, and a VALID indicator.
- the Branch Instruction Address field contains a predetermined number of bits related to the branch instruction address the entry is correlated.
- the BTB control circuit 62 compares the Branch Instruction Address with a current branch instruction address provided by the CPU 30 to determine whether the entry contains the instruction that is being addressed. If there is a match, the BTB control circuit 62 then checks the VALID indicator in the entry 64 to determine if the branch target address is valid.
- the BTB control circuit 62 also determines whether the valid branch target address is predicted to be taken using the PRED indicator in the entry 64 . If the PRED indicator indicates the valid branch target address is predicted to be taken, then the BTB control circuit 62 asserts the BTB Hit Indicator signal. If not, the BTB Hit Indicator signal is not asserted. Once lock control logic 66 determines that the number of entries equals the lock amount, then the LOCK indicators in the current entries 64 are set to indicate the entries 64 are locked.
- a data processing system can include a processor configured to execute processor instructions.
- a branch target buffer can have a plurality of entries, each entry configured to store a branch target address and a lock indicator.
- the lock indicator indicates whether the entry is a candidate for replacement.
- the processor is configured to access the branch target buffer during execution of the processor instructions.
- Control circuitry can be configured to determine a fullness level of the branch target buffer. In response to the fullness level reaching a fullness threshold, the control circuitry can be configured to assert the lock indicator of one or more of the plurality of entries to indicate that the one or more of the plurality of entries is not a candidate for replacement.
- the branch target buffer can be configured to, in response to a hit of a processor instruction in the branch target buffer, provide a branch target address to the processor.
- the fullness level of the branch target buffer can indicate a percentage of valid entries of the plurality of entries branch target buffer.
- each entry of the branch target buffer can be configured to store a valid indicator.
- the one or more of the plurality of entries can comprise all of the plurality of entries of the branch target buffer.
- the branch target buffer is further characterized as set associative, wherein the control circuitry is configured to determine a fullness level of a set of the branch target buffer. In response to the fullness level reaching the fullness threshold, the lock indicator can be asserted for one or more entries in the set.
- control circuitry can be configured to store a lock amount indicator, wherein the lock amount indicator indicates the fullness threshold.
- the lock amount indicator can indicate the one or more of the plurality of entries whose lock indicator is asserted.
- the branch target buffer can be configured to, in response to a miss of a processor access of the branch target buffer, select an entry for replacement from entries of the branch target buffer whose lock indicator is not asserted.
- a method in a data processing system having a branch target buffer, can comprise determining a fullness level of the branch target buffer based on a number of valid entries in the branch target buffer. Whether the fullness level of the branch target buffer has reached a fullness threshold can be determined. When the fullness level of the branch target buffer reaches the fullness threshold, one or more entries of the branch target buffer can be locked to cause the one or more entries to not be candidates for replacement.
- the method can further comprise receiving a lock amount indicator, wherein the lock amount indicator indicates the fullness threshold.
- the lock amount indicator can indicate the one or more entries.
- the locking the one or more entries can comprise locking all entries of the branch target buffer.
- the method can further comprise determining that a processor instruction results in a miss in the branch target buffer.
- An entry of the branch target buffer which is not locked can be selected for replacement.
- the selected entry can be updated with the processor instruction.
- the fullness level of the branch target buffer can indicate a percentage of valid entries of the plurality of entries branch target buffer.
- a data processing system can comprise a processor configured to execute processor instructions, and a branch target buffer having a plurality of entries. Each entry can be configured to store a branch target address, a valid indictor, and a lock indicator. The lock indicator can indicate whether the entry is a candidate for replacement.
- the processor can be configured to access the branch target buffer during execution of the processor instructions.
- Storage circuitry can be configured to store a lock amount indicator. The lock amount indicator can indicate a percentage of entries of the branch target buffer.
- Control circuitry can be configured to determine a fullness level of the branch target buffer based on valid entries of the branch target buffer.
- control circuitry can be configured to assert the lock indicator of one or more entries of branch target buffer which achieves the percentage of entries of the branch target buffer indicated by the lock amount indicator to indicate that the one or more of the plurality of entries is not a candidate for replacement.
- the lock amount indicator can indicate the fullness threshold.
- the fullness level of the branch target buffer can indicate a percentage of valid entries of the plurality of entries branch target buffer.
- the branch target buffer can be further characterized as set associative.
- the control circuitry can be configured to determine a fullness level of a set of the branch target buffer. In response to the fullness level reaching the fullness threshold, the lock indicator of one or more entries in the set which achieves the percentage of entries indicated by the lock amount indicator can be asserted.
- the branch target buffer can be configured to, in response to a miss of a processor instruction in the branch target buffer, select an entry for replacement from entries of the branch target buffer whose lock indicator is not asserted.
- bus is used to refer to a plurality of signals or conductors which may be used to transfer one or more various types of information, such as data, addresses, control, or status.
- the conductors as discussed herein may be illustrated or described in reference to being a single conductor, a plurality of conductors, unidirectional conductors, or bidirectional conductors. However, different embodiments may vary the implementation of the conductors. For example, separate unidirectional conductors may be used rather than bidirectional conductors and vice versa. Also, a plurality of conductors may be replaced with a single conductor that transfers multiple signals serially or in a time multiplexed manner. Likewise, single conductors carrying multiple signals may be separated out into various different conductors carrying subsets of these signals. Therefore, many options exist for transferring signals.
- assert or “set” and “negate” (or “deassert” or “clear”) are used herein when referring to the rendering of a signal, status bit, or similar apparatus into its logically true or logically false state, respectively. If the logically true state is a logic level one, the logically false state is a logic level zero. And if the logically true state is a logic level zero, the logically false state is a logic level one.
- FIG. 1 and the discussion thereof describe an exemplary information processing architecture
- this exemplary architecture is presented merely to provide a useful reference in discussing various aspects of the invention.
- the description of the architecture has been simplified for purposes of discussion, and it is just one of many different types of appropriate architectures that may be used in accordance with the invention.
- Those skilled in the art will recognize that the boundaries between logic blocks are merely illustrative and that alternative embodiments may merge logic blocks or circuit elements or impose an alternate decomposition of functionality upon various logic blocks or circuit elements.
- any two components herein combined to achieve a particular functionality can be seen as “associated with” each other such that the desired functionality is achieved, irrespective of architectures or intermedial components.
- any two components so associated can also be viewed as being “operably connected,” or “operably coupled,” to each other to achieve the desired functionality.
- data processing system 10 are circuitry located on a single integrated circuit or within a same device.
- data processing system 10 may include any number of separate integrated circuits or separate devices interconnected with each other.
- memory 16 may be located on a same integrated circuit as processor 12 or on a separate integrated circuit or located within another peripheral or slave discretely separate from other elements of data processing system 10 .
- Peripherals 18 and 20 may also be located on separate integrated circuits or devices.
- data processing system 10 or portions thereof may be soft or code representations of physical circuitry or of logical representations convertible into physical circuitry. As such, data processing system 10 may be embodied in a hardware description language of any appropriate type.
- All or some of the software described herein may be received elements of data processing system 10 , for example, from computer readable media such as memory 16 or other media on other computer systems.
- computer readable media may be permanently, removably or remotely coupled to an information processing system such as data processing system 10 .
- the computer readable media may include, for example and without limitation, any number of the following: magnetic storage media including disk and tape storage media; optical storage media such as compact disk media (e.g., CD-ROM, CD-R, etc.) and digital video disk storage media; nonvolatile memory storage media including semiconductor-based memory units such as FLASH memory, EEPROM, EPROM, ROM; ferromagnetic digital memories; MRAM; volatile storage media including registers, buffers or caches, main memory, RAM, etc.; and data transmission media including computer networks, point-to-point telecommunication equipment, and carrier wave transmission media, just to name a few.
- magnetic storage media including disk and tape storage media
- optical storage media such as compact disk media (e.g., CD-ROM, CD-R, etc.) and digital video disk storage media
- nonvolatile memory storage media including semiconductor-based memory units such as FLASH memory, EEPROM, EPROM, ROM
- ferromagnetic digital memories such as FLASH memory, EEPROM, EPROM, ROM
- data processing system 10 is a computer system such as a personal computer system.
- Computer systems are information handling systems which can be designed to give independent computing power to one or more users.
- Computer systems may be found in many forms including but not limited to mainframes, minicomputers, servers, workstations, personal computers, notepads, personal digital assistants, electronic games, automotive and other embedded systems, cell phones and various other wireless devices.
- a typical computer system includes at least one processing unit, associated memory and a number of input/output (I/O) devices.
- a computer system processes information according to a program and produces resultant output information via I/O devices.
- a program is a list of instructions such as a particular application program and/or an operating system.
- a computer program is typically stored internally on computer readable storage medium or transmitted to the computer system via a computer readable transmission medium.
- a computer process typically includes an executing (running) program or portion of a program, current program values and state information, and the resources used by the operating system to manage the execution of the process.
- a parent process may spawn other, child processes to help perform the overall functionality of the parent process. Because the parent process specifically spawns the child processes to perform a portion of the overall functionality of the parent process, the functions performed by child processes (and grandchild processes, etc.) may sometimes be described as being performed by the parent process.
- Coupled is not intended to be limited to a direct coupling or a mechanical coupling.
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
Description
Claims (17)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/955,106 US9311099B2 (en) | 2013-07-31 | 2013-07-31 | Systems and methods for locking branch target buffer entries |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/955,106 US9311099B2 (en) | 2013-07-31 | 2013-07-31 | Systems and methods for locking branch target buffer entries |
Publications (2)
Publication Number | Publication Date |
---|---|
US20150039870A1 US20150039870A1 (en) | 2015-02-05 |
US9311099B2 true US9311099B2 (en) | 2016-04-12 |
Family
ID=52428775
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/955,106 Active 2034-10-09 US9311099B2 (en) | 2013-07-31 | 2013-07-31 | Systems and methods for locking branch target buffer entries |
Country Status (1)
Country | Link |
---|---|
US (1) | US9311099B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10423418B2 (en) | 2015-11-30 | 2019-09-24 | International Business Machines Corporation | Method for maintaining a branch prediction history table |
US10489296B2 (en) | 2016-09-22 | 2019-11-26 | International Business Machines Corporation | Quality of cache management in a computer |
Citations (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5530825A (en) | 1994-04-15 | 1996-06-25 | Motorola, Inc. | Data processor with branch target address cache and method of operation |
US6253288B1 (en) * | 1998-04-30 | 2001-06-26 | Hewlett-Packard Company | Hybrid cache/SIRO buffer system |
US6895498B2 (en) * | 2001-05-04 | 2005-05-17 | Ip-First, Llc | Apparatus and method for target address replacement in speculative branch target address cache |
US20060031839A1 (en) * | 2002-10-15 | 2006-02-09 | Koninkljke Philips Eletronics N.V. | Data processing apparatus and method of synchronizing at least two processing means in a data processing apparatus |
US20090217017A1 (en) | 2008-02-26 | 2009-08-27 | International Business Machines Corporation | Method, system and computer program product for minimizing branch prediction latency |
US7620750B2 (en) * | 2004-07-20 | 2009-11-17 | Koninklijke Philips Electronics N.V. | Time budgeting by determining status of a streaming buffer during an autonomous non-data transfer operations in drive units |
US7676633B1 (en) * | 2007-01-31 | 2010-03-09 | Network Appliance, Inc. | Efficient non-blocking storage of data in a storage server victim cache |
US7707396B2 (en) * | 2006-11-17 | 2010-04-27 | International Business Machines Corporation | Data processing system, processor and method of data processing having improved branch target address cache |
US7895422B2 (en) * | 2008-02-29 | 2011-02-22 | Freescale Semiconductor, Inc. | Selective postponement of branch target buffer (BTB) allocation |
US8024517B2 (en) * | 2009-01-30 | 2011-09-20 | International Business Machines Corporation | Proactive technique for reducing occurrence of long write service time for a storage device with a write cache |
US20110296096A1 (en) * | 2010-05-28 | 2011-12-01 | Xiang Zou | Method And Apparatus For Virtualized Microcode Sequencing |
US8090934B2 (en) * | 2006-07-11 | 2012-01-03 | Cetin Kaya Koc | Systems and methods for providing security for computer systems |
US8171269B2 (en) * | 2009-03-06 | 2012-05-01 | Agere Systems Inc. | Branch target buffer with entry source field for use in determining replacement priority |
US8244988B2 (en) * | 2009-04-30 | 2012-08-14 | International Business Machines Corporation | Predictive ownership control of shared memory computing system data |
US8832418B2 (en) * | 2009-08-28 | 2014-09-09 | Via Technologies, Inc. | Efficient branch target address cache entry replacement |
US8874884B2 (en) * | 2011-11-04 | 2014-10-28 | Qualcomm Incorporated | Selective writing of branch target buffer when number of instructions in cache line containing branch instruction is less than threshold |
US20150006863A1 (en) * | 2013-07-01 | 2015-01-01 | Freescale Semiconductor, Inc. | Debug method and device for providing indexed trace messages |
US9052910B2 (en) * | 2007-10-25 | 2015-06-09 | International Business Machines Corporation | Efficiency of short loop instruction fetch |
-
2013
- 2013-07-31 US US13/955,106 patent/US9311099B2/en active Active
Patent Citations (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5530825A (en) | 1994-04-15 | 1996-06-25 | Motorola, Inc. | Data processor with branch target address cache and method of operation |
US6253288B1 (en) * | 1998-04-30 | 2001-06-26 | Hewlett-Packard Company | Hybrid cache/SIRO buffer system |
US6895498B2 (en) * | 2001-05-04 | 2005-05-17 | Ip-First, Llc | Apparatus and method for target address replacement in speculative branch target address cache |
US20060031839A1 (en) * | 2002-10-15 | 2006-02-09 | Koninkljke Philips Eletronics N.V. | Data processing apparatus and method of synchronizing at least two processing means in a data processing apparatus |
US7620750B2 (en) * | 2004-07-20 | 2009-11-17 | Koninklijke Philips Electronics N.V. | Time budgeting by determining status of a streaming buffer during an autonomous non-data transfer operations in drive units |
US8090934B2 (en) * | 2006-07-11 | 2012-01-03 | Cetin Kaya Koc | Systems and methods for providing security for computer systems |
US7707396B2 (en) * | 2006-11-17 | 2010-04-27 | International Business Machines Corporation | Data processing system, processor and method of data processing having improved branch target address cache |
US7676633B1 (en) * | 2007-01-31 | 2010-03-09 | Network Appliance, Inc. | Efficient non-blocking storage of data in a storage server victim cache |
US9052910B2 (en) * | 2007-10-25 | 2015-06-09 | International Business Machines Corporation | Efficiency of short loop instruction fetch |
US20090217017A1 (en) | 2008-02-26 | 2009-08-27 | International Business Machines Corporation | Method, system and computer program product for minimizing branch prediction latency |
US7895422B2 (en) * | 2008-02-29 | 2011-02-22 | Freescale Semiconductor, Inc. | Selective postponement of branch target buffer (BTB) allocation |
US8024517B2 (en) * | 2009-01-30 | 2011-09-20 | International Business Machines Corporation | Proactive technique for reducing occurrence of long write service time for a storage device with a write cache |
US8171269B2 (en) * | 2009-03-06 | 2012-05-01 | Agere Systems Inc. | Branch target buffer with entry source field for use in determining replacement priority |
US8244988B2 (en) * | 2009-04-30 | 2012-08-14 | International Business Machines Corporation | Predictive ownership control of shared memory computing system data |
US8832418B2 (en) * | 2009-08-28 | 2014-09-09 | Via Technologies, Inc. | Efficient branch target address cache entry replacement |
US20110296096A1 (en) * | 2010-05-28 | 2011-12-01 | Xiang Zou | Method And Apparatus For Virtualized Microcode Sequencing |
US8874884B2 (en) * | 2011-11-04 | 2014-10-28 | Qualcomm Incorporated | Selective writing of branch target buffer when number of instructions in cache line containing branch instruction is less than threshold |
US20150006863A1 (en) * | 2013-07-01 | 2015-01-01 | Freescale Semiconductor, Inc. | Debug method and device for providing indexed trace messages |
Also Published As
Publication number | Publication date |
---|---|
US20150039870A1 (en) | 2015-02-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7987322B2 (en) | Snoop request management in a data processing system | |
US8145985B2 (en) | Error detection schemes for a unified cache in a data processing system | |
US9165023B2 (en) | Integrated circuit device and method for determining an index of an extreme value within an array of values | |
US8458447B2 (en) | Branch target buffer addressing in a data processor | |
US8131951B2 (en) | Utilization of a store buffer for error recovery on a store allocation cache miss | |
CN107810481B (en) | Age-based management of instruction blocks in a processor instruction window | |
US7873819B2 (en) | Branch target buffer addressing in a data processor | |
US8766827B1 (en) | Parallel apparatus for high-speed, highly compressed LZ77 tokenization and Huffman encoding for deflate compression | |
US9519588B2 (en) | Bounded cache searches | |
US9092225B2 (en) | Systems and methods for reducing branch misprediction penalty | |
US9213665B2 (en) | Data processor for processing a decorated storage notify | |
US5774710A (en) | Cache line branch prediction scheme that shares among sets of a set associative cache | |
US8180969B2 (en) | Cache using pseudo least recently used (PLRU) cache replacement with locking | |
US20150331799A1 (en) | Pre-decoding analysis based configuration information cache management method and system | |
US8504777B2 (en) | Data processor for processing decorated instructions with cache bypass | |
US20150301829A1 (en) | Systems and methods for managing branch target buffers in a multi-threaded data processing system | |
US9311099B2 (en) | Systems and methods for locking branch target buffer entries | |
US10740237B2 (en) | Data processing unit having a memory protection unit | |
US9483272B2 (en) | Systems and methods for managing return stacks in a multi-threaded data processing system | |
CN112379929A (en) | Instruction replacement method, device, processor, electronic equipment and storage medium | |
US8589738B2 (en) | Program trace message generation for page crossing events for debug | |
US20090249048A1 (en) | Branch target buffer addressing in a data processor | |
US10007522B2 (en) | System and method for selectively allocating entries at a branch target buffer |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SCOTT, JEFFREY W.;MOYER, WILLIAM C.;SIGNING DATES FROM 20130729 TO 20130730;REEL/FRAME:030916/0056 |
|
AS | Assignment |
Owner name: CITIBANK, N.A., AS NOTES COLLATERAL AGENT, NEW YOR Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:031591/0266 Effective date: 20131101 |
|
AS | Assignment |
Owner name: CITIBANK, N.A., AS NOTES COLLATERAL AGENT, NEW YOR Free format text: SUPPLEMENT TO IP SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:031627/0201 Effective date: 20131101 Owner name: CITIBANK, N.A., AS COLLATERAL AGENT, NEW YORK Free format text: SUPPLEMENT TO IP SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:031627/0158 Effective date: 20131101 |
|
AS | Assignment |
Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: PATENT RELEASE;ASSIGNOR:CITIBANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:037357/0874 Effective date: 20151207 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS;ASSIGNOR:CITIBANK, N.A.;REEL/FRAME:037444/0787 Effective date: 20151207 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS;ASSIGNOR:CITIBANK, N.A.;REEL/FRAME:037518/0292 Effective date: 20151207 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: SUPPLEMENT TO THE SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:039138/0001 Effective date: 20160525 |
|
AS | Assignment |
Owner name: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC., NETHERLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:040925/0001 Effective date: 20160912 Owner name: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC., NE Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:040925/0001 Effective date: 20160912 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PCT NUMBERS IB2013000664, US2013051970, US201305935 PREVIOUSLY RECORDED AT REEL: 037444 FRAME: 0787. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS;ASSIGNOR:CITIBANK, N.A.;REEL/FRAME:040450/0715 Effective date: 20151207 |
|
AS | Assignment |
Owner name: NXP B.V., NETHERLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:040928/0001 Effective date: 20160622 |
|
AS | Assignment |
Owner name: NXP USA, INC., TEXAS Free format text: MERGER;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:041144/0363 Effective date: 20161107 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS;ASSIGNOR:CITIBANK, N.A.;REEL/FRAME:041703/0536 Effective date: 20151207 |
|
AS | Assignment |
Owner name: SHENZHEN XINGUODU TECHNOLOGY CO., LTD., CHINA Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITYINTEREST IN PATENTS.;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:048734/0001 Effective date: 20190217 |
|
AS | Assignment |
Owner name: NXP B.V., NETHERLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:050744/0097 Effective date: 20190903 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |
|
AS | Assignment |
Owner name: NXP B.V., NETHERLANDS Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVEAPPLICATION 11759915 AND REPLACE IT WITH APPLICATION11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITYINTEREST;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:052915/0001 Effective date: 20160622 |
|
AS | Assignment |
Owner name: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC., NETHERLANDS Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVEAPPLICATION 11759915 AND REPLACE IT WITH APPLICATION11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITYINTEREST;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:052917/0001 Effective date: 20160912 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |