US9301391B2 - Substrate structure, semiconductor package device, and manufacturing method of substrate structure - Google Patents

Substrate structure, semiconductor package device, and manufacturing method of substrate structure Download PDF

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US9301391B2
US9301391B2 US13/689,207 US201213689207A US9301391B2 US 9301391 B2 US9301391 B2 US 9301391B2 US 201213689207 A US201213689207 A US 201213689207A US 9301391 B2 US9301391 B2 US 9301391B2
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metal layer
layer
dielectric layer
substrate structure
structure according
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US20130161809A1 (en
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Hwee-Seng Jimmy Chew
Shoa-Siong Raymond Lim
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Advanpack Solutions Pte Ltd
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Advanpack Solutions Pte Ltd
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Assigned to ADVANPACK SOLUTIONS PTE LTD. reassignment ADVANPACK SOLUTIONS PTE LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEW, HWEE-SENG JIMMY, LIM, SHOA-SIONG RAYMOND
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    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
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    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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    • H01L21/4857—Multilayer substrates
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H05K1/0313—Organic insulating material
    • H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/0373—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement containing additives, e.g. fillers
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    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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Definitions

  • the invention relates in general to a substrate structure, the semiconductor package device and manufacturing method of substrate structure.
  • the invention is directed to a substrate structure, a semiconductor package device and a manufacturing method of substrate structure.
  • the first metal layer of the conductive structure is electrically connected to the third metal layer through the second metal layer, and the size of the third metal layer is larger than that of the second metal layer, so that the trace density is increased, and the trace design is more flexible.
  • a substrate structure comprising a conductive structure comprising a first metal layer, a second metal layer and a third metal layer.
  • the second metal layer is disposed on the first metal layer.
  • the third metal layer is disposed on the second metal layer.
  • Each of the second metal layer and the third metal layer has a first surface and a second surface opposite to the first surface.
  • the first surface of the third metal layer is connected to the second surface of the second metal layer.
  • the surface area of the first surface of the third metal layer is larger than that of the second surface of the second metal layer.
  • a semiconductor package device comprises a conductive structure and a semiconductor chip.
  • the conductive structure comprises a first metal layer, a second metal layer and a third metal layer.
  • the second metal layer is disposed on the first metal layer.
  • the third metal layer is disposed on the second metal layer.
  • Each of the second metal layer and the third metal layer has a first surface and a second surface opposite to the first surface.
  • the first surface of the third metal layer is connected to the second surface of the second metal layer.
  • the surface area of the first surface of the third metal layer is larger than that of the second surface of the second metal layer.
  • the semiconductor chip is disposed on the conductive structure and is electrically connected to the first metal layer.
  • a manufacturing method of substrate structure comprises the following steps.
  • a first metal layer is formed.
  • a second metal layer is formed on the first metal layer.
  • a third metal layer is formed on the second metal layer.
  • Each of the second metal layer and the third metal layer has a first surface and a second surface opposite to the first surface.
  • the first surface of the third metal layer is connected to the second surface of the second metal layer.
  • the surface area of the first surface of the third metal layer is larger than that of the second surface of the second metal layer.
  • the first metal layer, the second metal layer and the third metal layer form a conductive structure.
  • FIG. 1A shows a cross-sectional view of a substrate structure according to an embodiment of the invention
  • FIG. 1B shows a partial top view of a region A of FIG. 1A ;
  • FIG. 2A shows a cross-sectional view of a substrate structure according to another embodiment of the invention.
  • FIG. 2B shows a partial cross-sectional view of the first metal layer FIG. 2A being bonded to a contact pad
  • FIG. 3A shows a top view of a substrate structure according to an alternate embodiment of the invention
  • FIG. 3B shows a cross-sectional view of the substrate structure of FIG. 3A along a cross-sectional line 3 B- 3 B′.
  • FIG. 4A shows e a top view of a substrate structure according to another alternate embodiment of the invention.
  • FIG. 4B shows a cross-sectional view of the substrate structure of FIG. 4A along a cross-sectional line 4 B- 4 B′;
  • FIG. 5 shows a cross-sectional view of a semiconductor package device according to an embodiment of the invention
  • FIG. 6 shows a cross-sectional view of a semiconductor package device according to another embodiment of the invention.
  • FIGS. 7A ⁇ 7 T are processes of a flowchart of a manufacturing method of substrate structure according to an embodiment of the invention.
  • the substrate structure 100 comprises a conductive structure 100 A and a conductive carrier 110 disposed on the conductive structure 100 A.
  • the conductive structure 100 A comprises a first metal layer 120 , a second metal layer 130 and a third metal layer 140 .
  • the second metal layer 130 is disposed on the first metal layer 120 .
  • the third metal layer 140 is disposed on the second metal layer 130 .
  • the second metal layer 130 has a first surface 130 a and a second surface 130 b opposite to the first surface 130 a .
  • the third metal layer 140 has a first surface 140 a and a second surface 140 b opposite to the first surface 140 a .
  • the first surface 140 a of the third metal layer 140 is connected to the second surface 130 b of the second metal layer 130 .
  • the surface area of the first surface 140 a of the third metal layer 140 is larger than that of the second surface 130 b of the second metal layer 130 .
  • the thickness 120 T of the first metal layer 120 is about 20 ⁇ m.
  • the thickness 140 T of the third metal layer 140 is larger than or equal to the thickness 130 T of the second metal layer 130 .
  • the thickness 130 T of the second metal layer 130 ranges between 20 ⁇ 50 ⁇ m, and preferably ranges between 20 ⁇ 30 ⁇ m.
  • the thickness 140 T of the third metal layer 140 ranges between 50 ⁇ 100 ⁇ m.
  • each of the first metal layer 120 and the third metal layer 140 comprises at least one of copper, nickel, palladium or gold, and the second metal layer 130 comprises at least one of copper or nickel.
  • FIG. 1B a partial top view of a region A of FIG. 1A is shown.
  • the second surface 130 b of the second metal layer 130 and the first surface 140 a of the third metal layer 140 are substantially circular
  • the diameter 130 D of the second surface 130 b of the second metal layer 130 ranges between 20 ⁇ 100 ⁇ m
  • the diameter 140 D of the first surface 140 a of the third metal layer 140 ranges between 200 ⁇ 300 ⁇ m.
  • the part of the first metal layer 120 coupled to the second metal layer 130 is substantially circular, and has a diameter 120 D, which ranges between 80 ⁇ 100 ⁇ m.
  • the diameter 140 D is larger than the diameter 130 D
  • the diameter 140 D is larger than the diameter 120 D.
  • the conductive structure 100 A further comprises a dielectric layer 150 .
  • the first metal layer 120 , the second metal layer 130 and the third metal layer 140 are embedded in the dielectric layer 150 , such that the metal layers 120 , 130 and 140 will not be damaged by an etching solution in subsequent etching process.
  • the dielectric layer 150 comprises a thermosetting material and a silica filler.
  • the second surface 140 b of the third metal layer 140 is exposed outside the dielectric layer 150 for electrically connecting to an external element.
  • the part outside the second surface 140 b of the third metal layer 140 is encapsulated by the dielectric layer 150 . That is, the dielectric layer 150 defines the surface area of the second surface 140 b , and avoids the metal layers 120 , 130 and 140 being damaged in subsequent etching process. Meanwhile, in the subsequent process, when the metal layers 120 , 130 and/or 140 are connected to the solder, the dielectric layer 150 can protect the metal layers 120 , 130 and 140 without using a solder mask. That is, the dielectric layer 150 can have the function of a solder mask.
  • the substrate structure 100 has an active surface and a rear surface opposite to the active surface.
  • the first metal layer 120 is formed by a plurality of traces.
  • the traces form a trace pattern on the active surface of the substrate structure 100 .
  • the second metal layer 130 has a plurality of micro-via holes completely embedded in the dielectric layer 150 .
  • the third metal layer 140 has a plurality of studs. At least one trace has a micro-via hole and a stud corresponding to the trace.
  • the micro-via holes of the second metal layer 130 are for electrically connecting the traces of the first metal layer 120 to the studs of the third metal layer 140 .
  • the studs further electrically connect the traces to the rear surface of the substrate structure 100 .
  • a surface of the stud is exposed outside the dielectric layer 150 for electrically connecting to an external element.
  • the surface area of the electrical connection terminal S is equal to that of the first surface 140 a of the third metal layer 140 .
  • the large surface area of the terminal S incapacitates the formation of the metal traces 120 - 1 and 120 - 5 of FIG. 1B .
  • the first metal layer 120 is electrically connected to the third metal layer 140 through the second metal layer 130 , the first metal layer 120 is not directly formed on the third metal layer 140 , and the size of the third metal layer 140 is larger than that of the second metal layer 130 .
  • the surface area of the first surface 140 a of the third metal layer 140 is larger than that of the second surface 130 b of the second metal layer 130 ; or, the diameter 140 D is larger than the diameter 130 D.
  • the surface area of the part of the first metal layer 120 coupled to the second metal layer 130 (the electrical connection terminal) can be reduced to be equal to or slightly larger than that of the second surface 130 b of the second metal layer 130 . Therefore, there is sufficient space for forming the metal traces 120 - 1 and 120 - 5 of FIG. 1B , and more traces can be formed at the part between the electrical connection terminals (the part electrically connected to the second metal layer 130 ) of the first metal layer 120 (traces). Consequently, the trace density is increased, and trace design becomes more flexible.
  • the conductive carrier 110 is such as a copper layer or a composite metal layer having a Cu exterior clad layer.
  • the composite metal layer comprises an inner layer and a Cu exterior clad layer, wherein the thickness of the inner layer is larger than that of the Cu exterior clad layer.
  • the inner layer such as comprises steel, or at least two of iron, carbon, magnesium, phosphorus, sulfur, chromium and nickel.
  • the material of the Cu exterior clad layer is different from that of the inner layer, hence providing better isolation for etching.
  • the use of the Cu exterior clad layer makes the conductive carrier 110 be used and operated as a complete copper layer, and reduces overall manufacturing cost.
  • the coefficient of thermal expansion (CTE) of the inner layer is close to that of the package material used for encapsulating the semiconductor chip. Therefore, the semiconductor package device formed by using the conductive carrier 110 has fewer warpage, such that the surface area of the conductive carrier 110 is increased and more semiconductor package devices can be formed on the conductive carrier 110 .
  • the surface area of the conductive carrier 110 is larger than that of the conductive structure 100 A.
  • the conductive carrier 110 has an opening 110 c exposing the top surface 120 a of the first metal layer 120
  • the conductive carrier 110 has a carrier ring surrounding the opening 110 c .
  • the carrier ring of the conductive carrier 110 is protruded from the peripheral of the conductive structure 100 A.
  • the carrier ring of the conductive carrier 110 surrounds the top surface 150 a of the dielectric layer 150 for enhancing the strength of the substrate structure 100 to avoid the package unit being warped or deformed.
  • the semiconductor package device having the substrate structure 100 can be delivered through the carrier ring of the conductive carrier 110 without contacting the first metal layer 120 or the dielectric layer 150 to avoid the semiconductor package device being mechanically damaged.
  • the conductive carrier 110 has at least one through hole 110 t formed in the ring structure (carrier ring).
  • the through hole 110 t is a positioning hole for the semiconductor package device having the substrate structure 100 , and can be used as a reference point for positioning the semiconductor package device.
  • FIG. 2A shows a cross-sectional view of a substrate structure according to another embodiment of the invention.
  • FIG. 2B shows a partial cross-sectional view of the first metal layer FIG. 2A being bonded to a contact pad.
  • the present embodiment of the invention is different from the embodiment of FIG. 1A in that: in the semiconductor structure 200 , the top surface 220 a of the first metal layer 220 of the conductive structure 200 A is exposed outside the dielectric layer 150 and recessed corresponding to the top surface 150 a of the dielectric layer 150 . As indicated in FIG.
  • the solder 280 when the surface 220 a is recessed corresponding to the top surface 150 a of the dielectric layer 150 , the solder 280 is partly or completely embedded in the recess of the dielectric layer 150 , such that two opposite sides of the solder 280 are individually restricted in the recess by the sidewalls of the dielectric layer 150 and cannot move around. Consequently, the solder 280 (such as solder tin) reflowed at a high temperature will not be bridged and short-circuited.
  • the second surface 140 b of the third metal layer 140 can also be recessed corresponding to the bottom surface 150 b of the dielectric layer 150 (the bottom surface 150 b is not illustrated in the diagram) for fixing the solder ball 575 (Referring to FIG. 5 ) on the third metal layer 140 , such that the implantation quality is more stable.
  • FIG. 3A shows a top view of a substrate structure according to an alternate embodiment of the invention.
  • FIG. 3B shows a cross-sectional view of the substrate structure of FIG. 3A along a cross-sectional line 3 B- 3 B′.
  • the substrate structure 300 comprises a conductive carrier ring 110 and four packaging units 301 .
  • the conductive carrier ring 110 has four openings 110 c separated by ribs 110 R. Each opening 110 c correspondingly exposes a packaging unit 301 .
  • Each packaging unit 301 is such as divided into four element blocks 303 .
  • each of the element blocks 303 has the same pattern and is formed by a plurality of traces.
  • the four element blocks 303 are encapsulated by the dielectric layer 150 , and the peripheral of each packaging unit 301 is interconnected by the ribs 110 R to avoid the package unit being warped or deformed.
  • the conductive carrier ring 110 also has a plurality of through holes 110 t in the ring structure (carrier ring). As indicated in FIG. 3A , the circular through holes 110 t at the four corners of the conductive carrier ring 110 can be used as reference points for positioning the semiconductor package device, and the groove type through holes 110 t located on two sides of the conductive carrier ring 110 can be used for relieving the stress of the substrate structure 300 .
  • FIG. 4A shows a top view of a substrate structure according to another alternate embodiment of the invention.
  • FIG. 4B shows a cross-sectional view of the substrate structure of FIG. 4A along a cross-sectional line 4 B- 4 B′.
  • the embodiment of FIGS. 4A ⁇ 4 B is different from the embodiment of FIGS.
  • the conductive carrier ring 310 has a larger opening 310 c correspondingly exposing a packaging units 301 , each packaging unit 301 is such as divided into 16 element blocks 303 encapsulated by the dielectric layer 150 a , and the outmost peripherals of the four packaging units 301 are connected to the conductive carrier ring 310 to avoid the package unit being warped or deformed.
  • FIG. 5 shows a cross-sectional view of a semiconductor package device according to an embodiment of the invention.
  • FIG. 6 shows a cross-sectional view of a semiconductor package device according to another embodiment of the invention.
  • the semiconductor package device 500 / 600 comprises a conductive structure 100 A, a conductive carrier 110 and a semiconductor chip 560 .
  • the conductive carrier 110 is disposed on the conductive structure 110 A.
  • the conductive carrier 110 has an opening 110 c exposing the top surface 120 a of the first metal layer 120 .
  • the semiconductor chip 560 is disposed in the opening 110 c and electrically connected to the first metal layer 120 .
  • the semiconductor package device 500 / 600 may further comprise a connection element for electrically connecting the semiconductor chip 560 to the first metal layer 120 .
  • the semiconductor package device 500 / 600 further comprises an encapsulating layer 570 encapsulating the semiconductor chip 560 and the connection element. Details of the description of the conductive structure 110 A are as disclosed in the above embodiments, and the similarities are not repeated here.
  • the connection element is such as a solder 580 and a column stud 590 (pillar bump).
  • the semiconductor chip 560 is electrically connected to the first metal layer 120 through the solder 580 and the column stud 590 .
  • the encapsulating layer 570 encapsulates the semiconductor chip 560 , the solder 580 and the column stud 590 .
  • the semiconductor package device 500 further comprises a solder ball 575 or a solder paste (not illustrated), and the second surface 140 b of the third metal layer 140 is electrically connected to an external element through the solder ball 575 or the solder paste.
  • the semiconductor package device 500 further comprises the underfill 585 encapsulating the connection element.
  • connection element is such as a bonding wire 690 through which the semiconductor chip 560 is electrically connected to the first metal layer 120 .
  • the encapsulating layer 570 encapsulates the semiconductor chip 560 and the bonding wire 690 .
  • the semiconductor package device 600 further comprises a solder pad 675 through which the second surface 140 b of the third metal layer 140 is electrically connected to an external element.
  • the package structure having two semiconductor elements is cut along a cutting line to form single semiconductor elements.
  • the conductive carrier ring 110 is removed (not illustrated).
  • FIGS. 7A ⁇ 7 T processes of a flowchart of a manufacturing method of substrate structure according to an embodiment of the invention are shown.
  • a conductive carrier 110 is provided.
  • the material of the conductive carrier 110 is the same as the disclosure in the above embodiments, and the similarities are not repeated here.
  • a first metal layer 120 is formed.
  • the formation of the first metal layer 120 comprises the following steps: A conductive carrier 110 is provided. A first photoresist layer PR 1 is formed on the conductive carrier 110 as indicated in FIG. 7B . A first photoresist layer PR 1 is patterned to form a plurality of first opening 710 exposing a part of the conductive carrier 110 as indicated in FIG. 7C . A first metal layer 120 is formed in the first opening 710 as indicated in FIG. 7D . Thus, the line width and the line spacing of the first metal layer 120 can achieve 10 ⁇ m level.
  • the formation of the first metal layer is as follows.
  • a copper layer is formed on the conductive carrier 110 .
  • a photoresist layer is formed on the copper layer.
  • the photoresist layer is patterned to form a predetermined pattern of the first metal layer.
  • a part of the copper layer exposed outside the photoresist layer is etched.
  • the photoresist layer is removed to form the first metal layer.
  • the manufacturing process for forming the first metal layer is selected according to actual needs and is not limited to the above exemplification.
  • the first opening 710 is formed by such as etching
  • the first metal layer 120 is formed by such as electroplating
  • the first metal layer 120 comprises at least one of copper, nickel, palladium or gold and directly contacts the conductive carrier 110 .
  • a second metal layer 130 is formed.
  • the formation of the second metal layer 130 comprises the following steps: A second photoresist layer PR 2 is formed on the first photoresist layer PR 1 and the first metal layer 120 as indicated in FIG. 7E . A second photoresist layer PR 2 is patterned to form a plurality of second openings 720 exposing a part of the first metal layer 120 as indicated in FIG. 7F . A second metal layer 130 is formed in the second opening 720 as indicated in FIG. 7G . In an embodiment, each part of the first metal layer 120 at least corresponds to a second opening 720 as indicated in FIG. 7F .
  • each part of the first metal layer 120 is at least corresponding and connected to a part of the second metal layer 130 .
  • the surface of each part of the second metal layer 130 (the first surface 130 a and the second surface 130 b ) is such as circular, the diameter ranges between 20 ⁇ 100 ⁇ m, and each part of the second metal layer 130 is such as cylindrical.
  • the second metal layer 130 directly contacts the first metal layer 120 .
  • the second metal layer 130 is formed on the first metal layer 120 by such as electroplating.
  • the second metal layer 130 comprises at least one of copper or nickel, and the thickness of the second metal layer 130 ranges between 20 ⁇ 50 ⁇ m.
  • a third metal layer 140 is formed.
  • the formation of the third metal layer 140 comprises the following steps: A third photoresist layer PR 3 is formed on the second photoresist layer PR 2 and the second metal layer 130 as indicated in FIG. 7H . A third photoresist layer PR 3 is patterned to form a plurality of third openings 730 exposing the second metal layer 130 as indicated in FIG. 7I . A third metal layer 140 is formed in the third opening 730 as indicated in FIG. 7J .
  • each part of the second metal layer 130 at least corresponds to a third opening 730 .
  • the size of the third opening 730 is larger than that of the second metal layer 130 .
  • the third opening 730 exposes the entire surface 130 b of the second metal layer 130 and a part of the second photoresist layer PR 2 .
  • each part of the second metal layer 130 is at least corresponding and connected to a part of the third metal layer 140 .
  • the size of the third metal layer 140 is larger than that of the second metal layer 130 .
  • the third metal layer 140 covers the entire surface 130 b of the second metal layer 130 and a part of the second photoresist layer PR 2 .
  • the first surface 140 a of the third metal layer 140 directly contacts the second surface 130 b of the second metal layer 130 , and the surface area of the first surface 140 a of the third metal layer 140 is larger than that of the second surface 130 b of the second metal layer 130 .
  • the third metal layer 140 is formed by such as an electroplating process and comprises at least one of copper, nickel, palladium or gold.
  • the thickness of the third metal layer 140 is larger than or equal to that of the second metal layer 130 .
  • the first metal layer 120 , the second metal layer 130 and the third metal layer 140 form a conductive structure 100 A.
  • the first photoresist layer PR 1 , the second photoresist layer PR 2 and the third photoresist layer PR 3 are removed.
  • the photoresist layers PR 1 , PR 2 and PR 3 are removed at the same time by such as etching. After the photoresist layers PR 1 , PR 2 and PR 3 are removed, the conductive carrier 110 , the first metal layer 120 , the second metal layer 130 and the third metal layer 140 are exposed.
  • the formation of the second metal layer and the third metal layer (not illustrated) as follows: A second photoresist layer is formed on the first photoresist layer and the first metal layer. A second photoresist layer is patterned to form a plurality of second openings exposing the first metal layer. A third photoresist layer is formed on the second photoresist layer and patterned to form a plurality of third openings exposing a part of the second photoresist layer and the first metal layer. A second metal layer and a third metal layer are formed at the same time in the second opening and the third opening respectively.
  • the manufacturing method of the present embodiment of the invention is different from the manufacturing method of FIGS.
  • the dielectric layer 150 , the first metal layer 120 , the second metal layer 130 and the third metal layer 140 are formed and embedded in the dielectric layer 150 .
  • the formation of the dielectric layer 150 comprises the following steps: A conductive structure 100 A (the first metal layer 120 , the second metal layer 130 and the third metal layer 140 ) is formed in the cavity 750 s of the mold 750 as indicated in FIG. 7L .
  • a liquid thermosetting material 150 ′ is introduced into the cavity 750 s for encapsulating the conductive structure 100 A (the first metal layer 120 , the second metal layer 130 and the third metal layer 140 ) as indicated in FIG. 7M .
  • the liquid thermosetting material 150 ′ is cured to form the dielectric layer 150 as indicated in FIG. 7N .
  • the mold 750 is removed.
  • the liquid thermosetting material 150 ′ is introduced into the mold 750 under the conditions of high temperature and high pressure.
  • surface treatment is applied to the surface of the conductive structure 100 A (the first metal layer 120 , the second metal layer 130 and the third metal layer 140 ) by such as chemical treatment or plasma treatment for increasing the adhesion between the surface and the dielectric layer 150 .
  • the operating pressure may easily cause damage to delicate metal structure.
  • the thermosetting material 150 ′ is heated and becomes liquid through the transfer molding process. Then, the liquid thermosetting material 150 ′ is introduced into the cavity 750 s of the mold 750 under the conditions of high temperature and high pressure without causing damage to the structure of the first metal layer 120 , the second metal layer 130 and the third metal layer 140 . Since the thermosetting material 150 ′ introduced into the cavity 750 s of the mold 750 is in a liquid state, the liquid thermosetting material 150 ′ can completely encapsulate the first metal layer 120 , the second metal layer 130 and the third metal layer 140 .
  • thermosetting material 150 ′ in a liquid state does not damage the structure even when the operating pressure is high, the high pressure state can be used to suppress the generation of gas, and excellent adhesion between the dielectric layer 150 and the first metal layer 120 , the second metal layer 130 and the third metal layer 140 can thus be achieved.
  • the transfer molding process under high temperature provides excellent tightness between the dielectric layer 150 and the metal layers 120 , 130 and 140 , such that the metal layers 120 , 130 and 140 will not be damaged in subsequent etching process.
  • the dielectric layer 150 comprises a thermosetting material and a silica filler.
  • a part of the dielectric layer 150 is removed to expose the second surface 140 b of the third metal layer 140 .
  • a part of the dielectric layer 150 is removed by such as mechanical grinding or polishing for completely exposing the second surface 140 b of the third metal layer 140 .
  • a part of the third metal layer 140 is removed by mechanical grinding or polishing, such that the expose second surface 140 b is even smoother.
  • the second surface 140 b of the third metal layer 140 can be etched, such that the second surface 140 b of the third metal layer 140 is recessed corresponding to the bottom surface 150 b (not illustrated) of the dielectric layer 150 .
  • the conductive carrier 110 is etched to form an opening 110 c exposing the top surface 120 a of the first metal layer 120 .
  • the conductive carrier 110 has a carrier ring surrounding the opening 110 c.
  • the step of forming the opening 110 c by etching the conductive carrier 110 is as follows: A fourth photoresist layer PR 4 is formed on the conductive carrier 110 and the dielectric layer 150 as indicated in FIG. 7P .
  • the fourth photoresist layer PR 4 is patterned to form opening 740 c exposing a part of the conductive carrier 110 as indicated in FIG. 7Q .
  • the conductive carrier 110 is etched according to the patterned fourth photoresist layer PR 4 to form the opening 110 c as indicated in FIG. 7R .
  • the fourth photoresist layer PR 4 is removed.
  • the opening 110 c exposes the top surface 120 a of the first metal layer 120 and the top surface 150 a of the dielectric layer 150 .
  • the conductive carrier 110 is etched at the same time to form at least one through hole 110 t in the ring structure (carrier ring) of the conductive carrier 110 .
  • the step of forming the through hole 110 t by etching the conductive carrier 110 is as follows: A fourth photoresist layer PR 4 is formed on the conductive carrier 110 and the dielectric layer 150 as indicated in FIG. 7P .
  • the fourth photoresist layer PR 4 is patterned to form opening 740 t exposing a part of the conductive carrier 110 as indicated in FIG. 7Q .
  • the conductive carrier 110 is etched according to the patterned fourth photoresist layer PR 4 to form opening 110 t as indicated in FIG. 7R .
  • the fourth photoresist layer PR 4 is removed.
  • the top surface 120 a of the first metal layer 120 can be etched, such that the top surface 120 a of the first metal layer 120 is recessed corresponding to the top surface 150 a of the dielectric layer 150 ( FIG. 2A ).
  • a surface finishing layer 760 can be formed on the exposed surface 120 a of the first metal layer 120 and the second surface 140 b of the third metal layer 140 .
  • the surface finishing layer 760 is formed by such as electroplating, electroless plating or immersion.
  • the surface finishing layer 760 comprises at least one of copper, nickel, palladium, gold, silver and tin.

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Abstract

A substrate structure includes first, second and third metal layers embedded in a dielectric layer between its opposite upper first and lower second surfaces. The entire upper surface of the first metal layer is exposed on the first surface of the dielectric layer, the entire lower surface of the third metal layer is exposed on the second surface of the dielectric layer, and the second metal layer is disposed between the first metal layer and the third metal layer, wherein the area of the third metal layer is larger than the area of the second metal layer.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a substrate structure, the semiconductor package device and manufacturing method of substrate structure.
2. Description of the Related Art
As the electronic products are widely used in people's everydayness, the demand for semiconductor elements is increasing. The design of semiconductor elements is directed towards slimness. As the size of semiconductor elements is reduced, the number of I/O pins is increased, not decreased, such that the circuit pitch and the circuit width need to be reduced, and the design of fine pitches as small as 50 μm or even smaller than 35 μm has thus come to the fore.
However, in the design of fine pitches, solder bridging may easily occur between neighboring traces, and the solder may even be overspread along traces. Therefore, how to resolve the above problems encountered in element miniaturization and simplify the packaging process has become a prominent task for the industries of semiconductor package device.
SUMMARY OF THE INVENTION
The invention is directed to a substrate structure, a semiconductor package device and a manufacturing method of substrate structure. In the substrate structure, the first metal layer of the conductive structure is electrically connected to the third metal layer through the second metal layer, and the size of the third metal layer is larger than that of the second metal layer, so that the trace density is increased, and the trace design is more flexible.
According to an embodiment of the present invention, a substrate structure is provided. The substrate structure comprises a conductive structure comprising a first metal layer, a second metal layer and a third metal layer. The second metal layer is disposed on the first metal layer. The third metal layer is disposed on the second metal layer. Each of the second metal layer and the third metal layer has a first surface and a second surface opposite to the first surface. The first surface of the third metal layer is connected to the second surface of the second metal layer. The surface area of the first surface of the third metal layer is larger than that of the second surface of the second metal layer.
According to another embodiment of the present invention, a semiconductor package device is provided. The semiconductor package device comprises a conductive structure and a semiconductor chip. The conductive structure comprises a first metal layer, a second metal layer and a third metal layer. The second metal layer is disposed on the first metal layer. The third metal layer is disposed on the second metal layer. Each of the second metal layer and the third metal layer has a first surface and a second surface opposite to the first surface. The first surface of the third metal layer is connected to the second surface of the second metal layer. The surface area of the first surface of the third metal layer is larger than that of the second surface of the second metal layer. The semiconductor chip is disposed on the conductive structure and is electrically connected to the first metal layer.
According to an alternate embodiment of the present invention, a manufacturing method of substrate structure is provided. The manufacturing method of substrate structure comprises the following steps. A first metal layer is formed. A second metal layer is formed on the first metal layer. A third metal layer is formed on the second metal layer. Each of the second metal layer and the third metal layer has a first surface and a second surface opposite to the first surface. The first surface of the third metal layer is connected to the second surface of the second metal layer. The surface area of the first surface of the third metal layer is larger than that of the second surface of the second metal layer. The first metal layer, the second metal layer and the third metal layer form a conductive structure.
The above and other aspects of the invention will become better understood with regard to the following detailed description of the preferred but non-limiting embodiment(s). The following description is made with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A shows a cross-sectional view of a substrate structure according to an embodiment of the invention;
FIG. 1B shows a partial top view of a region A of FIG. 1A;
FIG. 2A shows a cross-sectional view of a substrate structure according to another embodiment of the invention;
FIG. 2B shows a partial cross-sectional view of the first metal layer FIG. 2A being bonded to a contact pad;
FIG. 3A shows a top view of a substrate structure according to an alternate embodiment of the invention;
FIG. 3B shows a cross-sectional view of the substrate structure of FIG. 3A along a cross-sectional line 3B-3B′.
FIG. 4A shows e a top view of a substrate structure according to another alternate embodiment of the invention;
FIG. 4B shows a cross-sectional view of the substrate structure of FIG. 4A along a cross-sectional line 4B-4B′;
FIG. 5 shows a cross-sectional view of a semiconductor package device according to an embodiment of the invention;
FIG. 6 shows a cross-sectional view of a semiconductor package device according to another embodiment of the invention;
FIGS. 7A˜7T are processes of a flowchart of a manufacturing method of substrate structure according to an embodiment of the invention.
 DETAILED DESCRIPTION OF THE INVENTION
Referring to FIG. 1A, a cross-sectional view of a substrate structure according to an embodiment of the invention is shown. The substrate structure 100 comprises a conductive structure 100A and a conductive carrier 110 disposed on the conductive structure 100A.
The conductive structure 100A comprises a first metal layer 120, a second metal layer 130 and a third metal layer 140. The second metal layer 130 is disposed on the first metal layer 120. The third metal layer 140 is disposed on the second metal layer 130. The second metal layer 130 has a first surface 130 a and a second surface 130 b opposite to the first surface 130 a. The third metal layer 140 has a first surface 140 a and a second surface 140 b opposite to the first surface 140 a. The first surface 140 a of the third metal layer 140 is connected to the second surface 130 b of the second metal layer 130. The surface area of the first surface 140 a of the third metal layer 140 is larger than that of the second surface 130 b of the second metal layer 130.
In an embodiment, the thickness 120T of the first metal layer 120 is about 20 μm. In an embodiment, the thickness 140T of the third metal layer 140 is larger than or equal to the thickness 130T of the second metal layer 130. The thickness 130T of the second metal layer 130 ranges between 20˜50 μm, and preferably ranges between 20˜30 μm. The thickness 140T of the third metal layer 140 ranges between 50˜100 μm.
In an embodiment, each of the first metal layer 120 and the third metal layer 140 comprises at least one of copper, nickel, palladium or gold, and the second metal layer 130 comprises at least one of copper or nickel.
Referring to FIG. 1B, a partial top view of a region A of FIG. 1A is shown. In an embodiment, as indicated in FIG. 1B, the second surface 130 b of the second metal layer 130 and the first surface 140 a of the third metal layer 140 are substantially circular, the diameter 130D of the second surface 130 b of the second metal layer 130 ranges between 20˜100 μm, and the diameter 140D of the first surface 140 a of the third metal layer 140 ranges between 200˜300 μm. As indicated in FIG. 1B, the part of the first metal layer 120 coupled to the second metal layer 130 is substantially circular, and has a diameter 120D, which ranges between 80˜100 μm. In an embodiment, the diameter 140D is larger than the diameter 130D, and the diameter 140D is larger than the diameter 120D.
As indicated in FIG. 1A, the conductive structure 100A further comprises a dielectric layer 150. The first metal layer 120, the second metal layer 130 and the third metal layer 140 are embedded in the dielectric layer 150, such that the metal layers 120, 130 and 140 will not be damaged by an etching solution in subsequent etching process. In an embodiment, the dielectric layer 150 comprises a thermosetting material and a silica filler.
In an embodiment, as indicated in FIG. 1A, the second surface 140 b of the third metal layer 140 is exposed outside the dielectric layer 150 for electrically connecting to an external element. The part outside the second surface 140 b of the third metal layer 140 is encapsulated by the dielectric layer 150. That is, the dielectric layer 150 defines the surface area of the second surface 140 b, and avoids the metal layers 120, 130 and 140 being damaged in subsequent etching process. Meanwhile, in the subsequent process, when the metal layers 120, 130 and/or 140 are connected to the solder, the dielectric layer 150 can protect the metal layers 120, 130 and 140 without using a solder mask. That is, the dielectric layer 150 can have the function of a solder mask.
The substrate structure 100 has an active surface and a rear surface opposite to the active surface. The first metal layer 120 is formed by a plurality of traces. The traces form a trace pattern on the active surface of the substrate structure 100. Preferably, the second metal layer 130 has a plurality of micro-via holes completely embedded in the dielectric layer 150. The third metal layer 140 has a plurality of studs. At least one trace has a micro-via hole and a stud corresponding to the trace. The micro-via holes of the second metal layer 130 are for electrically connecting the traces of the first metal layer 120 to the studs of the third metal layer 140. The studs further electrically connect the traces to the rear surface of the substrate structure 100. A surface of the stud is exposed outside the dielectric layer 150 for electrically connecting to an external element.
As indicated in FIG. 1B, if the first metal layer 120 is directly formed on the third metal layer 140, then the surface area of the electrical connection terminal S is equal to that of the first surface 140 a of the third metal layer 140. The large surface area of the terminal S incapacitates the formation of the metal traces 120-1 and 120-5 of FIG. 1B. Conversely, in an embodiment of the disclosure, the first metal layer 120 is electrically connected to the third metal layer 140 through the second metal layer 130, the first metal layer 120 is not directly formed on the third metal layer 140, and the size of the third metal layer 140 is larger than that of the second metal layer 130. For example, the surface area of the first surface 140 a of the third metal layer 140 is larger than that of the second surface 130 b of the second metal layer 130; or, the diameter 140D is larger than the diameter 130D. Meanwhile, the surface area of the part of the first metal layer 120 coupled to the second metal layer 130 (the electrical connection terminal) can be reduced to be equal to or slightly larger than that of the second surface 130 b of the second metal layer 130. Therefore, there is sufficient space for forming the metal traces 120-1 and 120-5 of FIG. 1B, and more traces can be formed at the part between the electrical connection terminals (the part electrically connected to the second metal layer 130) of the first metal layer 120 (traces). Consequently, the trace density is increased, and trace design becomes more flexible.
In an embodiment, the conductive carrier 110 is such as a copper layer or a composite metal layer having a Cu exterior clad layer. The composite metal layer comprises an inner layer and a Cu exterior clad layer, wherein the thickness of the inner layer is larger than that of the Cu exterior clad layer. The inner layer such as comprises steel, or at least two of iron, carbon, magnesium, phosphorus, sulfur, chromium and nickel. The material of the Cu exterior clad layer is different from that of the inner layer, hence providing better isolation for etching. Furthermore, the use of the Cu exterior clad layer makes the conductive carrier 110 be used and operated as a complete copper layer, and reduces overall manufacturing cost. In addition, the coefficient of thermal expansion (CTE) of the inner layer is close to that of the package material used for encapsulating the semiconductor chip. Therefore, the semiconductor package device formed by using the conductive carrier 110 has fewer warpage, such that the surface area of the conductive carrier 110 is increased and more semiconductor package devices can be formed on the conductive carrier 110.
As indicated in FIG. 1A, in an embodiment, the surface area of the conductive carrier 110 is larger than that of the conductive structure 100A. In an embodiment, the conductive carrier 110 has an opening 110 c exposing the top surface 120 a of the first metal layer 120, and the conductive carrier 110 has a carrier ring surrounding the opening 110 c. The carrier ring of the conductive carrier 110 is protruded from the peripheral of the conductive structure 100A. The carrier ring of the conductive carrier 110 surrounds the top surface 150 a of the dielectric layer 150 for enhancing the strength of the substrate structure 100 to avoid the package unit being warped or deformed. Moreover, the semiconductor package device having the substrate structure 100 can be delivered through the carrier ring of the conductive carrier 110 without contacting the first metal layer 120 or the dielectric layer 150 to avoid the semiconductor package device being mechanically damaged.
In an embodiment, as indicated in FIG. 1A, the conductive carrier 110 has at least one through hole 110 t formed in the ring structure (carrier ring). In an embodiment, the through hole 110 t is a positioning hole for the semiconductor package device having the substrate structure 100, and can be used as a reference point for positioning the semiconductor package device.
Referring to FIGS. 2A˜2B. FIG. 2A shows a cross-sectional view of a substrate structure according to another embodiment of the invention. FIG. 2B shows a partial cross-sectional view of the first metal layer FIG. 2A being bonded to a contact pad. The present embodiment of the invention is different from the embodiment of FIG. 1A in that: in the semiconductor structure 200, the top surface 220 a of the first metal layer 220 of the conductive structure 200A is exposed outside the dielectric layer 150 and recessed corresponding to the top surface 150 a of the dielectric layer 150. As indicated in FIG. 2B, when the surface 220 a is recessed corresponding to the top surface 150 a of the dielectric layer 150, the solder 280 is partly or completely embedded in the recess of the dielectric layer 150, such that two opposite sides of the solder 280 are individually restricted in the recess by the sidewalls of the dielectric layer 150 and cannot move around. Consequently, the solder 280 (such as solder tin) reflowed at a high temperature will not be bridged and short-circuited. In an embodiment, the second surface 140 b of the third metal layer 140 can also be recessed corresponding to the bottom surface 150 b of the dielectric layer 150 (the bottom surface 150 b is not illustrated in the diagram) for fixing the solder ball 575 (Referring to FIG. 5) on the third metal layer 140, such that the implantation quality is more stable.
Referring to FIGS. 3A˜3B. FIG. 3A shows a top view of a substrate structure according to an alternate embodiment of the invention. FIG. 3B shows a cross-sectional view of the substrate structure of FIG. 3A along a cross-sectional line 3B-3B′.
The substrate structure 300 comprises a conductive carrier ring 110 and four packaging units 301. The conductive carrier ring 110 has four openings 110 c separated by ribs 110R. Each opening 110 c correspondingly exposes a packaging unit 301. Each packaging unit 301 is such as divided into four element blocks 303. Preferably, each of the element blocks 303 has the same pattern and is formed by a plurality of traces. The four element blocks 303 are encapsulated by the dielectric layer 150, and the peripheral of each packaging unit 301 is interconnected by the ribs 110R to avoid the package unit being warped or deformed.
In an embodiment, the conductive carrier ring 110 also has a plurality of through holes 110 t in the ring structure (carrier ring). As indicated in FIG. 3A, the circular through holes 110 t at the four corners of the conductive carrier ring 110 can be used as reference points for positioning the semiconductor package device, and the groove type through holes 110 t located on two sides of the conductive carrier ring 110 can be used for relieving the stress of the substrate structure 300.
Referring to FIGS. 4A ˜ 4B. FIG. 4A shows a top view of a substrate structure according to another alternate embodiment of the invention. FIG. 4B shows a cross-sectional view of the substrate structure of FIG. 4A along a cross-sectional line 4B-4B′. The embodiment of FIGS. 4A ˜ 4B is different from the embodiment of FIGS. 3A˜3B in that: in the substrate structure 400, the conductive carrier ring 310 has a larger opening 310 c correspondingly exposing a packaging units 301, each packaging unit 301 is such as divided into 16 element blocks 303 encapsulated by the dielectric layer 150 a, and the outmost peripherals of the four packaging units 301 are connected to the conductive carrier ring 310 to avoid the package unit being warped or deformed.
Referring to FIGS. 5˜6. FIG. 5 shows a cross-sectional view of a semiconductor package device according to an embodiment of the invention. FIG. 6 shows a cross-sectional view of a semiconductor package device according to another embodiment of the invention.
As indicated in FIGS. 5˜6, the semiconductor package device 500/600 comprises a conductive structure 100A, a conductive carrier 110 and a semiconductor chip 560. The conductive carrier 110 is disposed on the conductive structure 110A. The conductive carrier 110 has an opening 110 c exposing the top surface 120 a of the first metal layer 120. The semiconductor chip 560 is disposed in the opening 110 c and electrically connected to the first metal layer 120. In an embodiment, the semiconductor package device 500/600 may further comprise a connection element for electrically connecting the semiconductor chip 560 to the first metal layer 120. In addition, the semiconductor package device 500/600 further comprises an encapsulating layer 570 encapsulating the semiconductor chip 560 and the connection element. Details of the description of the conductive structure 110A are as disclosed in the above embodiments, and the similarities are not repeated here.
As indicated in FIG. 5, the connection element is such as a solder 580 and a column stud 590 (pillar bump). The semiconductor chip 560 is electrically connected to the first metal layer 120 through the solder 580 and the column stud 590. The encapsulating layer 570 encapsulates the semiconductor chip 560, the solder 580 and the column stud 590. Besides, the semiconductor package device 500 further comprises a solder ball 575 or a solder paste (not illustrated), and the second surface 140 b of the third metal layer 140 is electrically connected to an external element through the solder ball 575 or the solder paste. Moreover, the semiconductor package device 500 further comprises the underfill 585 encapsulating the connection element.
As indicated in FIG. 6, the connection element is such as a bonding wire 690 through which the semiconductor chip 560 is electrically connected to the first metal layer 120. The encapsulating layer 570 encapsulates the semiconductor chip 560 and the bonding wire 690. Besides, the semiconductor package device 600 further comprises a solder pad 675 through which the second surface 140 b of the third metal layer 140 is electrically connected to an external element.
Furthermore, the package structure having two semiconductor elements is cut along a cutting line to form single semiconductor elements. In the cutting process, the conductive carrier ring 110 is removed (not illustrated).
Referring to FIGS. 7A˜7T, processes of a flowchart of a manufacturing method of substrate structure according to an embodiment of the invention are shown.
Referring to FIG. 7A, a conductive carrier 110 is provided. The material of the conductive carrier 110 is the same as the disclosure in the above embodiments, and the similarities are not repeated here.
Referring to FIG. 7B˜7D, a first metal layer 120 is formed.
In an embodiment, the formation of the first metal layer 120 comprises the following steps: A conductive carrier 110 is provided. A first photoresist layer PR1 is formed on the conductive carrier 110 as indicated in FIG. 7B. A first photoresist layer PR1 is patterned to form a plurality of first opening 710 exposing a part of the conductive carrier 110 as indicated in FIG. 7C. A first metal layer 120 is formed in the first opening 710 as indicated in FIG. 7D. Thus, the line width and the line spacing of the first metal layer 120 can achieve 10 μm level.
In another embodiment, the formation of the first metal layer (not illustrated) is as follows. A copper layer is formed on the conductive carrier 110. A photoresist layer is formed on the copper layer. The photoresist layer is patterned to form a predetermined pattern of the first metal layer. A part of the copper layer exposed outside the photoresist layer is etched. The photoresist layer is removed to form the first metal layer.
In practical application, the manufacturing process for forming the first metal layer is selected according to actual needs and is not limited to the above exemplification.
In an embodiment, the first opening 710 is formed by such as etching, the first metal layer 120 is formed by such as electroplating, and the first metal layer 120 comprises at least one of copper, nickel, palladium or gold and directly contacts the conductive carrier 110.
Then, referring to FIGS. 7E˜7G, a second metal layer 130 is formed.
In an embodiment, the formation of the second metal layer 130 comprises the following steps: A second photoresist layer PR2 is formed on the first photoresist layer PR1 and the first metal layer 120 as indicated in FIG. 7E. A second photoresist layer PR2 is patterned to form a plurality of second openings 720 exposing a part of the first metal layer 120 as indicated in FIG. 7F. A second metal layer 130 is formed in the second opening 720 as indicated in FIG. 7G. In an embodiment, each part of the first metal layer 120 at least corresponds to a second opening 720 as indicated in FIG. 7F.
In an embodiment, as indicated in FIG. 7G, each part of the first metal layer 120 is at least corresponding and connected to a part of the second metal layer 130. The surface of each part of the second metal layer 130 (the first surface 130 a and the second surface 130 b) is such as circular, the diameter ranges between 20˜100 μm, and each part of the second metal layer 130 is such as cylindrical. The second metal layer 130 directly contacts the first metal layer 120. In an embodiment, the second metal layer 130 is formed on the first metal layer 120 by such as electroplating. The second metal layer 130 comprises at least one of copper or nickel, and the thickness of the second metal layer 130 ranges between 20˜50 μm.
Then, referring to FIGS. 7H˜7J, a third metal layer 140 is formed.
In an embodiment, the formation of the third metal layer 140 comprises the following steps: A third photoresist layer PR3 is formed on the second photoresist layer PR2 and the second metal layer 130 as indicated in FIG. 7H. A third photoresist layer PR3 is patterned to form a plurality of third openings 730 exposing the second metal layer 130 as indicated in FIG. 7I. A third metal layer 140 is formed in the third opening 730 as indicated in FIG. 7J.
In an embodiment, as indicated in FIG. 7I, each part of the second metal layer 130 at least corresponds to a third opening 730. The size of the third opening 730 is larger than that of the second metal layer 130. The third opening 730 exposes the entire surface 130 b of the second metal layer 130 and a part of the second photoresist layer PR2.
In an embodiment, as indicated in FIG. 7J, each part of the second metal layer 130 is at least corresponding and connected to a part of the third metal layer 140. The size of the third metal layer 140 is larger than that of the second metal layer 130. The third metal layer 140 covers the entire surface 130 b of the second metal layer 130 and a part of the second photoresist layer PR2. The first surface 140 a of the third metal layer 140 directly contacts the second surface 130 b of the second metal layer 130, and the surface area of the first surface 140 a of the third metal layer 140 is larger than that of the second surface 130 b of the second metal layer 130.
In an embodiment, the third metal layer 140 is formed by such as an electroplating process and comprises at least one of copper, nickel, palladium or gold. The thickness of the third metal layer 140 is larger than or equal to that of the second metal layer 130. Up to here, the first metal layer 120, the second metal layer 130 and the third metal layer 140 form a conductive structure 100A.
Then, referring to FIG. 7K, the first photoresist layer PR1, the second photoresist layer PR2 and the third photoresist layer PR3 are removed. In an embodiment, the photoresist layers PR1, PR2 and PR3 are removed at the same time by such as etching. After the photoresist layers PR1, PR2 and PR3 are removed, the conductive carrier 110, the first metal layer 120, the second metal layer 130 and the third metal layer 140 are exposed.
In another embodiment, the formation of the second metal layer and the third metal layer (not illustrated) as follows: A second photoresist layer is formed on the first photoresist layer and the first metal layer. A second photoresist layer is patterned to form a plurality of second openings exposing the first metal layer. A third photoresist layer is formed on the second photoresist layer and patterned to form a plurality of third openings exposing a part of the second photoresist layer and the first metal layer. A second metal layer and a third metal layer are formed at the same time in the second opening and the third opening respectively. The manufacturing method of the present embodiment of the invention is different from the manufacturing method of FIGS. 7E˜7J in that: after the second photoresist layer PR2 is formed, the second metal layer is not formed and the second photoresist layer PR3 is directly formed instead. Meanwhile, each second opening 720 and each third opening 730 are connected, and then the second metal layer 130 and the third metal layer 140 together are respectively formed in the second opening 720 and the third opening 730 connected to each other.
Then, referring to FIG. 7L˜7N, the dielectric layer 150, the first metal layer 120, the second metal layer 130 and the third metal layer 140 are formed and embedded in the dielectric layer 150.
In an embodiment, the formation of the dielectric layer 150 comprises the following steps: A conductive structure 100A (the first metal layer 120, the second metal layer 130 and the third metal layer 140) is formed in the cavity 750 s of the mold 750 as indicated in FIG. 7L. A liquid thermosetting material 150′ is introduced into the cavity 750 s for encapsulating the conductive structure 100A (the first metal layer 120, the second metal layer 130 and the third metal layer 140) as indicated in FIG. 7M. The liquid thermosetting material 150′ is cured to form the dielectric layer 150 as indicated in FIG. 7N. Lastly, the mold 750 is removed.
In an embodiment, the liquid thermosetting material 150′ is introduced into the mold 750 under the conditions of high temperature and high pressure. In an embodiment, before the thermosetting material 150′ is introduced into the mold 750, surface treatment is applied to the surface of the conductive structure 100A (the first metal layer 120, the second metal layer 130 and the third metal layer 140) by such as chemical treatment or plasma treatment for increasing the adhesion between the surface and the dielectric layer 150.
When the dielectric layer is formed by lamination, the operating pressure may easily cause damage to delicate metal structure. In the present embodiment, the thermosetting material 150′ is heated and becomes liquid through the transfer molding process. Then, the liquid thermosetting material 150′ is introduced into the cavity 750 s of the mold 750 under the conditions of high temperature and high pressure without causing damage to the structure of the first metal layer 120, the second metal layer 130 and the third metal layer 140. Since the thermosetting material 150′ introduced into the cavity 750 s of the mold 750 is in a liquid state, the liquid thermosetting material 150′ can completely encapsulate the first metal layer 120, the second metal layer 130 and the third metal layer 140. Since the thermosetting material 150′ in a liquid state does not damage the structure even when the operating pressure is high, the high pressure state can be used to suppress the generation of gas, and excellent adhesion between the dielectric layer 150 and the first metal layer 120, the second metal layer 130 and the third metal layer 140 can thus be achieved. Besides, the transfer molding process under high temperature provides excellent tightness between the dielectric layer 150 and the metal layers 120, 130 and 140, such that the metal layers 120, 130 and 140 will not be damaged in subsequent etching process.
In an embodiment, the dielectric layer 150 comprises a thermosetting material and a silica filler.
Then, referring to FIG. 7O, a part of the dielectric layer 150 is removed to expose the second surface 140 b of the third metal layer 140. In an embodiment, a part of the dielectric layer 150 is removed by such as mechanical grinding or polishing for completely exposing the second surface 140 b of the third metal layer 140.
In an embodiment, a part of the third metal layer 140 is removed by mechanical grinding or polishing, such that the expose second surface 140 b is even smoother.
In an embodiment, the second surface 140 b of the third metal layer 140 can be etched, such that the second surface 140 b of the third metal layer 140 is recessed corresponding to the bottom surface 150 b (not illustrated) of the dielectric layer 150.
Then, referring to FIGS. 7P˜7S, the conductive carrier 110 is etched to form an opening 110 c exposing the top surface 120 a of the first metal layer 120. The conductive carrier 110 has a carrier ring surrounding the opening 110 c.
In an embodiment, the step of forming the opening 110 c by etching the conductive carrier 110 is as follows: A fourth photoresist layer PR4 is formed on the conductive carrier 110 and the dielectric layer 150 as indicated in FIG. 7P. The fourth photoresist layer PR4 is patterned to form opening 740 c exposing a part of the conductive carrier 110 as indicated in FIG. 7Q. The conductive carrier 110 is etched according to the patterned fourth photoresist layer PR4 to form the opening 110 c as indicated in FIG. 7R. The fourth photoresist layer PR4 is removed.
In an embodiment, the opening 110 c exposes the top surface 120 a of the first metal layer 120 and the top surface 150 a of the dielectric layer 150.
Referring to FIG. 7P˜7S. The conductive carrier 110 is etched at the same time to form at least one through hole 110 t in the ring structure (carrier ring) of the conductive carrier 110.
In an embodiment, the step of forming the through hole 110 t by etching the conductive carrier 110 is as follows: A fourth photoresist layer PR4 is formed on the conductive carrier 110 and the dielectric layer 150 as indicated in FIG. 7P. The fourth photoresist layer PR4 is patterned to form opening 740 t exposing a part of the conductive carrier 110 as indicated in FIG. 7Q. The conductive carrier 110 is etched according to the patterned fourth photoresist layer PR4 to form opening 110 t as indicated in FIG. 7R. The fourth photoresist layer PR4 is removed.
In an embodiment, the top surface 120 a of the first metal layer 120 can be etched, such that the top surface 120 a of the first metal layer 120 is recessed corresponding to the top surface 150 a of the dielectric layer 150 (FIG. 2A).
Then, referring to FIG. 7T, a surface finishing layer 760 can be formed on the exposed surface 120 a of the first metal layer 120 and the second surface 140 b of the third metal layer 140.
In an embodiment, the surface finishing layer 760 is formed by such as electroplating, electroless plating or immersion. The surface finishing layer 760 comprises at least one of copper, nickel, palladium, gold, silver and tin.
While the invention has been described by way of example and in terms of the preferred embodiment(s), it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.

Claims (15)

What is claimed is:
1. A substrate structure, comprising:
a dielectric layer having a first surface and a second surface opposite the first surface; and
a plurality of conductive structures embedded in the dielectric layer between the first surface and the second surface of the dielectric layer and connecting the first surface of the dielectric layer to the second surface of the dielectric layer;
wherein each conductive structure comprises a first metal layer, a second metal layer and a third metal layer, the first metal layer being entirely exposed on the first surface of the dielectric layer, the third metal layer being entirely exposed on the second surface of the dielectric layer, and the second metal layer being disposed between the first metal layer and the third metal layer;
wherein the area of the second metal layer is smaller than the area of the first metal layer and the area of the third metal layer, and the area of the first metal layer is smaller than the area of the third metal layer.
2. The substrate structure according to claim 1, wherein the first metal layer comprises a plurality of terminals on the first surface of the dielectric layer.
3. The substrate structure according to claim 2, wherein the third metal layer comprises a plurality of studs on the second surface of the dielectric layer.
4. The substrate structure according to claim 3, wherein the second metal layer comprises a plurality of micro-vias disposed between the terminals and the studs.
5. The substrate structure according to claim 1, wherein the thickness of the third metal layer is larger than or equal to the thickness of the second metal layer.
6. The substrate structure according to claim 4, wherein the micro-vias and the studs are cylindrical, and the diameters of the studs are larger than the diameters of the corresponding micro-vias.
7. The substrate structure according to claim 1, wherein the dielectric layer comprises a thermosetting material and silica fillers.
8. The substrate structure according to claim 1, wherein the exposed surface of the first metal layer is recessed corresponding to the first surface of the dielectric layer.
9. The substrate structure according to claim 1, wherein the exposed surface of the third metal layer is recessed corresponding to the second surface of the dielectric layer.
10. The substrate structure according to claim 1, further comprising a conductive carrier disposed on the first surface of the dielectric layer.
11. The substrate structure according to claim 10, wherein the conductive carrier comprises an inner layer and a clad layer.
12. The substrate structure according to claim 10, wherein the conductive carrier comprises at least an opening to expose the first metal layer and the dielectric layer.
13. A substrate structure, comprising:
a dielectric layer having a first surface and a second surface opposite the first surface; and
a plurality of terminals, micro-vias and studs embedded in the dielectric layer between the first surface and the second surface of the dielectric layer;
wherein the terminals are entirely exposed on the first surface of the dielectric layer, the studs are entirely exposed on the second surface of the dielectric layer, and the micro-vias are disposed between the terminals and the studs such that the plurality of terminals, micro-vias and studs connect the first surface of the dielectric layer to the second surface of the dielectric layer; and
wherein the area of at least one micro-via is smaller than the area of the corresponding terminal and the area of the corresponding stud, and the area of at least one terminal is smaller than the area of the corresponding stud.
14. The substrate structure according to claim 13, further comprising a plurality of traces connected to the plurality of terminals and exposed on the first surface of the dielectric layer.
15. The substrate structure according to claim 1, further comprising a plurality of traces connected to the plurality of conductive structures and exposed on the first surface of the dielectric layer.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10184189B2 (en) 2016-07-18 2019-01-22 ECSI Fibrotools, Inc. Apparatus and method of contact electroplating of isolated structures

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102605359A (en) * 2011-01-25 2012-07-25 台湾上村股份有限公司 Chemical palladium-gold plated film structure and manufacturing method thereof, copper wire or palladium-gold plated film packaging structure jointed by palladium-copper wire and packaging process thereof
TWI562295B (en) 2012-07-31 2016-12-11 Mediatek Inc Semiconductor package and method for fabricating base for semiconductor package
US10991669B2 (en) 2012-07-31 2021-04-27 Mediatek Inc. Semiconductor package using flip-chip technology
US9177899B2 (en) 2012-07-31 2015-11-03 Mediatek Inc. Semiconductor package and method for fabricating base for semiconductor package
US10128175B2 (en) * 2013-01-29 2018-11-13 Taiwan Semiconductor Manufacturing Company Packaging methods and packaged semiconductor devices
TWI525769B (en) * 2013-11-27 2016-03-11 矽品精密工業股份有限公司 Package substrate and manufacturing method thereof
TWI541963B (en) * 2014-05-30 2016-07-11 恆勁科技股份有限公司 Package substrate and its fabrication method
JP6524533B2 (en) * 2016-02-25 2019-06-05 大口マテリアル株式会社 Substrate for mounting semiconductor element, semiconductor device, optical semiconductor device, and manufacturing method thereof
MY181637A (en) * 2016-03-31 2020-12-30 Qdos Flexcircuits Sdn Bhd Single layer integrated circuit package
MY172923A (en) * 2016-03-31 2019-12-13 Twisden Ltd Integrated circuit package having pin up interconnect
DE102016124270A1 (en) * 2016-12-13 2018-06-14 Infineon Technologies Ag SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR PACKAGE
US11705414B2 (en) * 2017-10-05 2023-07-18 Texas Instruments Incorporated Structure and method for semiconductor packaging
US10629558B2 (en) * 2018-05-08 2020-04-21 Advanced Semiconductor Engineering, Inc. Electronic device
US20210074621A1 (en) * 2019-09-10 2021-03-11 Amazing Microelectronic Corp. Semiconductor package
CN110752201B (en) * 2019-10-31 2022-04-15 京东方科技集团股份有限公司 Display back plate, preparation method thereof and display device
US11063011B1 (en) * 2020-02-20 2021-07-13 Nanya Technology Corporation Chip and wafer having multi-layered pad

Citations (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5248854A (en) 1989-04-05 1993-09-28 Nec Corporation Multilevel metallization for vlsi and method for forming the same
US5481798A (en) 1994-01-19 1996-01-09 Sony Corporation Etching method for forming a lead frame
US20010010945A1 (en) 2000-02-01 2001-08-02 Nec Corporation Semiconductor device and method of manufacturing the same
US6294840B1 (en) 1999-11-18 2001-09-25 Lsi Logic Corporation Dual-thickness solder mask in integrated circuit package
US20020025607A1 (en) 2000-08-30 2002-02-28 Tadatoshi Danno Semiconductor device and a method of manufacturing the same
US20020037647A1 (en) 1998-01-13 2002-03-28 Hwang Jeng H. Method of etching an anisotropic profile in platinum
US20020168542A1 (en) 2001-03-16 2002-11-14 Izbicki Anthony John Composite metals and method of making
US20030045024A1 (en) 2001-09-03 2003-03-06 Tadanori Shimoto Interconnecting substrate for carrying semiconductor device, method of producing thereof and package of semiconductor device
US20030057568A1 (en) * 2000-05-26 2003-03-27 Takashi Miyazaki Flip chip type semiconductor device and method of manufacturing the same
US20030064671A1 (en) 2001-04-30 2003-04-03 Arch Specialty Chemicals, Inc. Chemical mechanical polishing slurry composition for polishing conductive and non-conductive layers on semiconductor wafers
US6563202B1 (en) 1997-07-01 2003-05-13 Sony Corporation Lead frame, manufacturing method of a lead frame, semiconductor device, assembling method of a semiconductor device, and electronic apparatus
US20030232205A1 (en) 2002-06-14 2003-12-18 Nobuyoshi Tsukaguchi Metal/ceramic bonding article and method for producing same
US20050088833A1 (en) * 2002-05-27 2005-04-28 Katsumi Kikuchi Semiconductor device mounting board, method of manufacturing the same, method of inspecting the same, and semiconductor package
US20060189141A1 (en) 2003-03-25 2006-08-24 Hartmut Mahlkow Solution for etching copper surfaces and method of depositing metal on copper surfaces
US20070120229A1 (en) 2001-02-16 2007-05-31 Dai Nippon Printing Co., Ltd. Wet etched insulator and electronic circuit component
US20070281471A1 (en) 2006-06-01 2007-12-06 Dror Hurwitz Advanced Multilayered Coreless Support Structures and their Fabrication
US7365441B2 (en) 2003-02-21 2008-04-29 Dai Nippon Printing Co., Ltd. Semiconductor device fabricating apparatus and semiconductor device fabricating method
JP2008153622A (en) * 2006-12-14 2008-07-03 Advanpack Solutions Pte Ltd Semiconductor package and its manufacturing method
CN100437987C (en) 2002-05-27 2008-11-26 日本电气株式会社 Semiconductor device mounting board, method of manufacturing the same, method of inspecting the same, and semiconductor package
US20090046441A1 (en) * 2006-01-06 2009-02-19 Nec Corporation Wiring board for mounting semiconductor device, manufacturing method of the same, and wiring board assembly
CN102132404A (en) 2008-11-07 2011-07-20 先进封装技术私人有限公司 Semiconductor package and trace substrate with enhanced routing design flexibility and method of manufacturing thereof
US20120153463A1 (en) * 2010-12-16 2012-06-21 Ngk Spark Plug Co., Ltd. Multilayer wiring substrate and method of manufacturing the same
US20120153466A1 (en) * 2009-09-02 2012-06-21 Hwee-Seng Jimmy Chew Package structure
US8310060B1 (en) 2006-04-28 2012-11-13 Utac Thai Limited Lead frame land grid array
US20130020710A1 (en) * 2011-07-22 2013-01-24 Advanpack Solutions Pte Ltd. Semiconductor substrate, package and device and manufacturing methods thereof
US20130175707A1 (en) * 2011-12-19 2013-07-11 Advanpack Solutions Pte Ltd. Substrate structure, semiconductor package device, and manufacturing method of semiconductor package
US8865525B2 (en) * 2010-11-22 2014-10-21 Bridge Semiconductor Corporation Method of making cavity substrate with built-in stiffener and cavity substrate manufactured thereby
US8866301B2 (en) * 2010-05-18 2014-10-21 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers with interconnection structures

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7582556B2 (en) * 2005-06-24 2009-09-01 Megica Corporation Circuitry component and method for forming the same
US20100270668A1 (en) * 2009-04-28 2010-10-28 Wafer-Level Packaging Portfolio Llc Dual Interconnection in Stacked Memory and Controller Module

Patent Citations (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5248854A (en) 1989-04-05 1993-09-28 Nec Corporation Multilevel metallization for vlsi and method for forming the same
US5481798A (en) 1994-01-19 1996-01-09 Sony Corporation Etching method for forming a lead frame
US6563202B1 (en) 1997-07-01 2003-05-13 Sony Corporation Lead frame, manufacturing method of a lead frame, semiconductor device, assembling method of a semiconductor device, and electronic apparatus
US20020037647A1 (en) 1998-01-13 2002-03-28 Hwang Jeng H. Method of etching an anisotropic profile in platinum
US6294840B1 (en) 1999-11-18 2001-09-25 Lsi Logic Corporation Dual-thickness solder mask in integrated circuit package
US20010010945A1 (en) 2000-02-01 2001-08-02 Nec Corporation Semiconductor device and method of manufacturing the same
US20030057568A1 (en) * 2000-05-26 2003-03-27 Takashi Miyazaki Flip chip type semiconductor device and method of manufacturing the same
US20020025607A1 (en) 2000-08-30 2002-02-28 Tadatoshi Danno Semiconductor device and a method of manufacturing the same
US20070120229A1 (en) 2001-02-16 2007-05-31 Dai Nippon Printing Co., Ltd. Wet etched insulator and electronic circuit component
US20020168542A1 (en) 2001-03-16 2002-11-14 Izbicki Anthony John Composite metals and method of making
US20030064671A1 (en) 2001-04-30 2003-04-03 Arch Specialty Chemicals, Inc. Chemical mechanical polishing slurry composition for polishing conductive and non-conductive layers on semiconductor wafers
US20030045024A1 (en) 2001-09-03 2003-03-06 Tadanori Shimoto Interconnecting substrate for carrying semiconductor device, method of producing thereof and package of semiconductor device
US20050088833A1 (en) * 2002-05-27 2005-04-28 Katsumi Kikuchi Semiconductor device mounting board, method of manufacturing the same, method of inspecting the same, and semiconductor package
US7474538B2 (en) * 2002-05-27 2009-01-06 Nec Corporation Semiconductor device mounting board, method of manufacturing the same, method of inspecting the same, and semiconductor package
CN100437987C (en) 2002-05-27 2008-11-26 日本电气株式会社 Semiconductor device mounting board, method of manufacturing the same, method of inspecting the same, and semiconductor package
US20030232205A1 (en) 2002-06-14 2003-12-18 Nobuyoshi Tsukaguchi Metal/ceramic bonding article and method for producing same
US7365441B2 (en) 2003-02-21 2008-04-29 Dai Nippon Printing Co., Ltd. Semiconductor device fabricating apparatus and semiconductor device fabricating method
US20060189141A1 (en) 2003-03-25 2006-08-24 Hartmut Mahlkow Solution for etching copper surfaces and method of depositing metal on copper surfaces
US20090046441A1 (en) * 2006-01-06 2009-02-19 Nec Corporation Wiring board for mounting semiconductor device, manufacturing method of the same, and wiring board assembly
US8310060B1 (en) 2006-04-28 2012-11-13 Utac Thai Limited Lead frame land grid array
US20070281471A1 (en) 2006-06-01 2007-12-06 Dror Hurwitz Advanced Multilayered Coreless Support Structures and their Fabrication
US20090102043A1 (en) 2006-12-14 2009-04-23 Advanpack Solutions Pte Ltd. Semiconductor package and manufacturing method thereof
US20090291530A1 (en) * 2006-12-14 2009-11-26 Advanpack Solutions Pte Ltd. Semiconductor package and manufacturing method thereof
JP2008153622A (en) * 2006-12-14 2008-07-03 Advanpack Solutions Pte Ltd Semiconductor package and its manufacturing method
CN102132404A (en) 2008-11-07 2011-07-20 先进封装技术私人有限公司 Semiconductor package and trace substrate with enhanced routing design flexibility and method of manufacturing thereof
US20110210442A1 (en) * 2008-11-07 2011-09-01 Shoa Siong Lim Semiconductor Package and Trace Substrate with Enhanced Routing Design Flexibility and Method of Manufacturing Thereof
US20120153466A1 (en) * 2009-09-02 2012-06-21 Hwee-Seng Jimmy Chew Package structure
US8866301B2 (en) * 2010-05-18 2014-10-21 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers with interconnection structures
US8865525B2 (en) * 2010-11-22 2014-10-21 Bridge Semiconductor Corporation Method of making cavity substrate with built-in stiffener and cavity substrate manufactured thereby
US20120153463A1 (en) * 2010-12-16 2012-06-21 Ngk Spark Plug Co., Ltd. Multilayer wiring substrate and method of manufacturing the same
US20130020710A1 (en) * 2011-07-22 2013-01-24 Advanpack Solutions Pte Ltd. Semiconductor substrate, package and device and manufacturing methods thereof
US20130175707A1 (en) * 2011-12-19 2013-07-11 Advanpack Solutions Pte Ltd. Substrate structure, semiconductor package device, and manufacturing method of semiconductor package

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
Chinese Office Action dated Aug. 10, 2015.
Chinese Office Action dated Jan. 21, 2015 English translation. *
Chinese Office Action dated Jan. 21, 2015.
Taiwanese Office Action dated on Sep. 24, 2014.

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10184189B2 (en) 2016-07-18 2019-01-22 ECSI Fibrotools, Inc. Apparatus and method of contact electroplating of isolated structures
US10480092B2 (en) 2016-07-18 2019-11-19 ECSI Fibrotools Inc. Apparatus and method of contact electroplating of isolated structures

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