US9158678B2 - Memory address management system and method - Google Patents
Memory address management system and method Download PDFInfo
- Publication number
- US9158678B2 US9158678B2 US13/893,615 US201313893615A US9158678B2 US 9158678 B2 US9158678 B2 US 9158678B2 US 201313893615 A US201313893615 A US 201313893615A US 9158678 B2 US9158678 B2 US 9158678B2
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- address
- blocks
- data
- bits
- logical
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7201—Logical to physical mapping or translation of blocks or pages
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
Description
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- A physical page is a unit for which read or write can be performed at once inside the NAND flash memory. A logical page is a read/write unit set in the memory system. One logical page corresponds to one or more physical pages.
- A physical block is a minimum unit for which data can independently be erased inside the NAND flash memory. The physical block includes a plurality of physical pages. A logical block is a data erase unit set in the memory system. One logical block corresponds to one or more physical pages.
- A sector is a minimum unit of access from the host.
- A cluster is a management unit for managing data in the memory system. A cluster size is set to be equal to or larger than a sector size, and equal to the data management unit of a file system adopted by the OS of the host or to a logical page size. An integral multiple of 2 or more of the cluster size may also correspond to the logical page size. One cluster corresponds to, for example, eight sectors.
- A logical block number LBN is a number given to each logical block in order to identify the logical block, and is used as, for example, the ID (index) of the logical block.
- A logical cluster number LCN is a number given to each logical cluster in order to identify the logical cluster, and is used as, for example, the ID (index) of the logical cluster.
- A logical cluster address LCA is a logical cluster address on the memory system. The logical cluster address LCA corresponds to the logical block number LBN and logical cluster number LCN.
[2. Address Conversion Table]
Claims (7)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US13/893,615 US9158678B2 (en) | 2013-03-13 | 2013-05-14 | Memory address management system and method |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US201361778968P | 2013-03-13 | 2013-03-13 | |
US13/893,615 US9158678B2 (en) | 2013-03-13 | 2013-05-14 | Memory address management system and method |
Publications (2)
Publication Number | Publication Date |
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US20140281144A1 US20140281144A1 (en) | 2014-09-18 |
US9158678B2 true US9158678B2 (en) | 2015-10-13 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US13/893,615 Active 2033-10-22 US9158678B2 (en) | 2013-03-13 | 2013-05-14 | Memory address management system and method |
Country Status (1)
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US (1) | US9158678B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6723863B2 (en) * | 2016-08-01 | 2020-07-15 | オリンパス株式会社 | Embedded system, photography equipment and refresh method |
KR20180021950A (en) * | 2016-08-22 | 2018-03-06 | 에스케이하이닉스 주식회사 | Memory system |
Citations (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010012222A1 (en) * | 1999-12-20 | 2001-08-09 | Yukio Terasaki | Memory controller for flash memory system and method for accessing flash memory device |
US20020062433A1 (en) * | 1998-11-06 | 2002-05-23 | Kazumasa Suzuki | Memory with address conversion table |
US20020069314A1 (en) * | 1996-01-08 | 2002-06-06 | Shigenori Miyauchi | Semiconductor storage device |
US20050144418A1 (en) * | 2003-12-26 | 2005-06-30 | Kenzo Kita | Memory controller, flash memory system, and method of controlling operation for data exchange between host system and flash memory |
US6965963B1 (en) * | 1999-07-28 | 2005-11-15 | Sony Corporation | Continuous arrangement of data clusters across multiple storages |
US20080016267A1 (en) * | 2006-06-30 | 2008-01-17 | Tdk Corporation | Memory controller, flash memory system having memory controller, and method for controlling flash memory |
US20090055618A1 (en) * | 2005-07-29 | 2009-02-26 | Matsushita Electric Industrial Co., Ltd. | Memory controller, nonvolatile storage device, nonvolatile storage system, and nonvolatile memory address management method |
US20090083478A1 (en) * | 2007-03-28 | 2009-03-26 | Kabushiki Kaisha Toshiba | Integrated memory management and memory management method |
US20090248964A1 (en) * | 2008-03-01 | 2009-10-01 | Kabushiki Kaisha Toshiba | Memory system and method for controlling a nonvolatile semiconductor memory |
US7610435B2 (en) * | 2004-02-27 | 2009-10-27 | Panasonic Corporation | Nonvolatile memory device employing a write completion flag table |
US20100064111A1 (en) * | 2008-09-09 | 2010-03-11 | Kabushiki Kaisha Toshiba | Information processing device including memory management device managing access from processor to memory and memory management method |
US20100070735A1 (en) * | 2008-09-16 | 2010-03-18 | Micron Technology, Inc. | Embedded mapping information for memory devices |
US20100095049A1 (en) * | 2008-10-15 | 2010-04-15 | Troy Manning | Hot memory block table in a solid state storage device |
US20110004725A1 (en) * | 2009-07-02 | 2011-01-06 | Toshiba Storage Device Corporation | Data storage device and method |
US20110022780A1 (en) * | 2009-07-24 | 2011-01-27 | Nir Jacob Wakrat | Restore index page |
US20120066568A1 (en) * | 2010-09-14 | 2012-03-15 | Kabushiki Kaisha Toshiba | Storage device, electronic device, and data error correction method |
US20120072680A1 (en) * | 2010-09-22 | 2012-03-22 | Kabushiki Kaisha Toshiba | Semiconductor memory controlling device |
US20120079167A1 (en) * | 2010-09-24 | 2012-03-29 | Kabushiki Kaisha Toshiba | Memory system |
US20120226957A1 (en) * | 2011-03-01 | 2012-09-06 | Kabushiki Kaisha Toshiba | Controller, data storage device and program product |
US20120246383A1 (en) * | 2011-03-24 | 2012-09-27 | Kabushiki Kaisha Toshiba | Memory system and computer program product |
US8316208B2 (en) * | 2010-05-14 | 2012-11-20 | Tdk Corporation | Memory controller, flash memory system with memory controller, and method of controlling flash memory |
US20130198439A1 (en) * | 2012-01-26 | 2013-08-01 | Hitachi, Ltd. | Non-volatile storage |
US20140025865A1 (en) * | 2012-07-19 | 2014-01-23 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
US8745310B2 (en) * | 2007-01-23 | 2014-06-03 | Sony Corporation | Storage apparatus, computer system, and method for managing storage apparatus |
US20140325129A1 (en) * | 2008-12-31 | 2014-10-30 | Micron Technology, Inc. | Method and apparatus for active range mapping for a nonvolatile memory device |
-
2013
- 2013-05-14 US US13/893,615 patent/US9158678B2/en active Active
Patent Citations (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020069314A1 (en) * | 1996-01-08 | 2002-06-06 | Shigenori Miyauchi | Semiconductor storage device |
US20020062433A1 (en) * | 1998-11-06 | 2002-05-23 | Kazumasa Suzuki | Memory with address conversion table |
US6965963B1 (en) * | 1999-07-28 | 2005-11-15 | Sony Corporation | Continuous arrangement of data clusters across multiple storages |
JP2001243110A (en) | 1999-12-20 | 2001-09-07 | Tdk Corp | Memory controller, flash memory system and access method to flash memory |
US20010012222A1 (en) * | 1999-12-20 | 2001-08-09 | Yukio Terasaki | Memory controller for flash memory system and method for accessing flash memory device |
US20050144418A1 (en) * | 2003-12-26 | 2005-06-30 | Kenzo Kita | Memory controller, flash memory system, and method of controlling operation for data exchange between host system and flash memory |
US7610435B2 (en) * | 2004-02-27 | 2009-10-27 | Panasonic Corporation | Nonvolatile memory device employing a write completion flag table |
JP4679581B2 (en) | 2005-07-29 | 2011-04-27 | パナソニック株式会社 | MEMORY CONTROLLER, NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY SYSTEM, AND NONVOLATILE MEMORY ADDRESS MANAGEMENT METHOD |
US20090055618A1 (en) * | 2005-07-29 | 2009-02-26 | Matsushita Electric Industrial Co., Ltd. | Memory controller, nonvolatile storage device, nonvolatile storage system, and nonvolatile memory address management method |
US20080016267A1 (en) * | 2006-06-30 | 2008-01-17 | Tdk Corporation | Memory controller, flash memory system having memory controller, and method for controlling flash memory |
US8745310B2 (en) * | 2007-01-23 | 2014-06-03 | Sony Corporation | Storage apparatus, computer system, and method for managing storage apparatus |
US20090083478A1 (en) * | 2007-03-28 | 2009-03-26 | Kabushiki Kaisha Toshiba | Integrated memory management and memory management method |
US20090248964A1 (en) * | 2008-03-01 | 2009-10-01 | Kabushiki Kaisha Toshiba | Memory system and method for controlling a nonvolatile semiconductor memory |
US20100064111A1 (en) * | 2008-09-09 | 2010-03-11 | Kabushiki Kaisha Toshiba | Information processing device including memory management device managing access from processor to memory and memory management method |
US20100070735A1 (en) * | 2008-09-16 | 2010-03-18 | Micron Technology, Inc. | Embedded mapping information for memory devices |
US20100095049A1 (en) * | 2008-10-15 | 2010-04-15 | Troy Manning | Hot memory block table in a solid state storage device |
US20140325129A1 (en) * | 2008-12-31 | 2014-10-30 | Micron Technology, Inc. | Method and apparatus for active range mapping for a nonvolatile memory device |
US20110004725A1 (en) * | 2009-07-02 | 2011-01-06 | Toshiba Storage Device Corporation | Data storage device and method |
US20110022780A1 (en) * | 2009-07-24 | 2011-01-27 | Nir Jacob Wakrat | Restore index page |
US8316208B2 (en) * | 2010-05-14 | 2012-11-20 | Tdk Corporation | Memory controller, flash memory system with memory controller, and method of controlling flash memory |
US20120066568A1 (en) * | 2010-09-14 | 2012-03-15 | Kabushiki Kaisha Toshiba | Storage device, electronic device, and data error correction method |
US20120072680A1 (en) * | 2010-09-22 | 2012-03-22 | Kabushiki Kaisha Toshiba | Semiconductor memory controlling device |
US20120079167A1 (en) * | 2010-09-24 | 2012-03-29 | Kabushiki Kaisha Toshiba | Memory system |
US20120226957A1 (en) * | 2011-03-01 | 2012-09-06 | Kabushiki Kaisha Toshiba | Controller, data storage device and program product |
US20120246383A1 (en) * | 2011-03-24 | 2012-09-27 | Kabushiki Kaisha Toshiba | Memory system and computer program product |
US20130198439A1 (en) * | 2012-01-26 | 2013-08-01 | Hitachi, Ltd. | Non-volatile storage |
US20140025865A1 (en) * | 2012-07-19 | 2014-01-23 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
Also Published As
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US20140281144A1 (en) | 2014-09-18 |
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