US9023225B2 - Pattern forming method - Google Patents

Pattern forming method Download PDF

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US9023225B2
US9023225B2 US14/038,345 US201314038345A US9023225B2 US 9023225 B2 US9023225 B2 US 9023225B2 US 201314038345 A US201314038345 A US 201314038345A US 9023225 B2 US9023225 B2 US 9023225B2
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exposing section
exposing
pattern forming
pattern
material film
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US20140094034A1 (en
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Kenichi Oyama
Hidetami Yaegashi
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
    • B81C1/00031—Regular or irregular arrays of nanoscale structures, e.g. etch mask layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
    • B81C2201/0147—Film patterning
    • B81C2201/0149—Forming nanoscale microstructures using auto-arranging or self-assembling material

Definitions

  • the present disclosure relates to a pattern forming method of forming a pattern in a semiconductor fabricating process.
  • a lithography technology using deep ultraviolet (DUV) light with a wavelength of 193 nm and ArF gas as a light source has been predominantly used pursuant to the demand for miniaturization, thereby obtaining a fine pattern of about 40 nm.
  • DUV deep ultraviolet
  • DSA directed self-assembly
  • a block copolymer in which chains of A polymer and B polymer are bonded to each other at their ends is initially applied onto a substrate.
  • the chains of the A polymer and B polymer randomly dissolved in a solid are subjected to phase separation, so that the regions of the A polymer and B polymer are regularly arranged.
  • the block copolymer is patterned by removing any one of the regions of the A polymer and B polymer to form a mask with a predetermined pattern.
  • An example of the block copolymer includes a copolymer in which polystyrene (PS) and polymethyl methacrylate (PMMA) are bonded. In such block copolymer, a fine pattern up to 10 nm may be formed.
  • a photoresist for 193 nm exposure has a structurally insufficient strength.
  • the photoresist is formed in a fine pattern, there is a risk that the pattern may collapse due to wet development.
  • the roughness (e.g., line edge roughness (LER) or the like) of the pattern increases due to image blur caused by the wet development.
  • the photoresist film may have a roughened surface due to low resistance to dry etching (i.e., plasma etching) conducted after the formation of the pattern, or disappearance of the film may occur due to low mask selectivity. This may cause various problems, e.g., deterioration in shape of an etched pattern.
  • the pattern may collapse in the wet development. Further, the mask selectivity being low in an etching process may cause problems to obtain a desired pattern. Furthermore, it is required to form a guide pattern for obtaining the desired pattern. However, variations of the guide pattern affect the pattern to thereby make the process difficult.
  • the present disclosure provides a pattern forming method in which pattern collapse may not occur, the roughness of a pattern may be decreased, mask selectivity may be increased, and a fine pattern may be obtained without using a guide pattern.
  • a pattern forming method includes forming a pattern forming material film on a substrate as an etching target film, the pattern forming material film having an exposing section that has porosity upon exposure and a non-exposing section, patterning and exposing the pattern forming material film for the exposing section to have the porosity, selectively infiltrating a filling material into voids of the exposing section to reinforce the exposing section, and removing the non-exposing section of the pattern forming material film by dry etching to form a predetermined pattern.
  • FIG. 1 is a flowchart illustrating a pattern forming method in accordance with an embodiment of the present disclosure.
  • FIGS. 2A to 2D are sectional views of processes illustrating the pattern forming method in accordance with the embodiment of the present disclosure.
  • FIG. 3 is a sectional view illustrating a state of a case where a filled portion is formed in an entirety of an exposing section in forming the filled portion by infiltrating a filling material thereto.
  • FIG. 1 is a flowchart illustrating a pattern forming method according to an embodiment of the present disclosure
  • FIGS. 2A to 2D are sectional views of processes thereof.
  • a DSA material film 11 is formed on a surface of a semiconductor wafer 10 as a target film to be etched (Process 1 ; FIG. 2A ).
  • the DSA material film 11 for example, a block copolymer in which a first polymer chain and a second polymer chain are bonded to each other at their ends may be used.
  • An example of the block copolymer may include a copolymer in which polystyrene (PS) and polymethyl methacrylate (PMMA) are bonded.
  • the DSA material film 11 is formed on the semiconductor wafer 10 by a coating method.
  • the coating method may include a spin coating or slit coating.
  • an exposing section 12 becomes a porous section made of a second polymer, e.g., PMMA, while the DSA material remains on a non-exposing section 13 .
  • DUV light with a wavelength of 193 nm using ArF gas which is predominantly used in the recent photolithography technology, can be used as exposure light.
  • finer patterns may also be formed using extreme ultraviolet (EUV) light (wavelength of 13.5 nm) with a shorter wavelength or an electron beam (EB).
  • EUV extreme ultraviolet
  • EB electron beam
  • a filling material such as particles is selectively infiltrated into voids of at least a surface of the exposing section 12 (Process 3 ; FIG. 2C ).
  • This process is for reinforcing the porous exposing section 12 , and as a result, a filled portion 14 is formed on the at least surface of the exposing section 12 .
  • the filling material it is possible to employ reactant materials which become predetermined materials by reactions, nano particles, organic metal compounds (complexes, alkoxides, and the like), and solutions of derivatives of carbon nano tubes or nano fullerenes.
  • the reactant materials may include cyclopentasilane in which the voids are filled with aSi or SiN by reactions.
  • the nano particles may include colloidal silica (SiO 2 ), Si nano particles, TiO sol, SnO sol, CeO, HfO, ZrO, Ag, Cu and Au.
  • the organic metal compounds may include those that are decomposed to form any one of Al, AlO, ZrO, TiO, W and Si. Further, in case of using the solutions of derivatives of carbon nano tubes or nano fullerenes as the filling material, the carbon nano tubes or nano fullerenes are filled into the voids.
  • a thermal diffusion method may be used.
  • organic metal compounds are used as the filling material
  • hydrolysis may be utilized.
  • a method using supercritical fluids may also be employed.
  • the thermal diffusion method the filling material is diffused into the voids by heating the semiconductor wafer, for example, to about room temperature (23 degrees C.) to 150 degrees C.
  • the hydrolysis of the organic metal compounds is used, the voids are first filled with the organic metal compounds and then hydrolyzed. As a result, the voids are filled with any one of Al, AlO, ZrO, TiO, W and Si.
  • the filling material is infiltrated into the voids by using the nano permeability of the supercritical fluids (e.g., supercritical CO 2 ).
  • the filled portion 14 is formed by infiltrating the filling material into the voids on the at least surface of the porous exposing section 12 , so that the exposing section is reinforced. As shown in FIG. 3 , it is possible to form the entire exposing section 12 with the filled portion 14 , thereby obtaining superior effects.
  • a predetermined pattern is formed by removing the non-exposing section 13 via dry etching (Process 4 ; FIG. 2D ).
  • anisotropic etching by using a reactive ion etching (RIE) method may be used in the removal of the non-exposing section 13 . Since the filled portion 14 formed on at least the surface of the exposing section 12 has been reinforced by the filling material, most part of the filled portion are not removed by RIE, while only the non-exposing section 13 is substantially removed. In this manner, a predetermined pattern 15 can be formed.
  • RIE reactive ion etching
  • the mask selectivity can be increased in a subsequent etching process. Further, since the pattern is formed by the dry etching method, it is possible to increase the height of the pattern.
  • the pattern is formed without using the wet development, the pattern is not likely to collapse.
  • the image blur is not caused by the wet development, the roughness of the pattern can be lowered.
  • the DUV light is used as the exposure light
  • a fine pattern with a half pitch of about 40 nm which is a size obtainable in a current pattern forming technology by photolithography, can be formed.
  • a SADP technology when a SADP technology is combined, it is possible to obtain a fine pattern with a half pitch of down to about 20 nm. Further, upon application of the SADP technology, it is possible to widen the selectivity of the kinds of core materials.
  • the EUV having a shorter wavelength e.g., a wavelength of 13.5 nm
  • an electron beam (EB) enables the formation of a finer pattern.
  • the block copolymer consisting of PS and PMMA is used as the material for forming a pattern
  • other DSA material films consisting of a block copolymer in which ends of chains of first and second polymers are bonded to each other may be used.
  • the material for forming a pattern is not limited to such DSA material films.
  • the pattern forming material may be any inorganic or organic materials, as long as a porous body can be formed therefrom by exposure.
  • the DSA material film for forming a pattern is formed by a coating method
  • the present disclosure is not limited to this but a thin film forming technology such as CVD or the like may be used.
  • the exposing section is formed to have porosity by patterning and exposing the material film for forming a pattern and is reinforced by selectively infiltrating filling material into voids of the exposing section; and a non-exposing section is then removed via dry etching to form a pattern.
  • LER roughness

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  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Nanotechnology (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Drying Of Semiconductors (AREA)
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Abstract

A pattern forming method includes forming a pattern forming material film on a substrate as an etching target film, the pattern forming material film having an exposing section that has porosity upon exposure and a non-exposing section, patterning and exposing the pattern forming material film for the exposing section to have the porosity, selectively infiltrating a filling material into voids of the exposing section to reinforce the exposing section, and removing the non-exposing section of the pattern forming material film by dry etching to form a predetermined pattern.

Description

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the benefit of Japanese Patent Application No. 2012-216388, filed on Sep. 28, 2012 in the Japan Patent Office, the disclosure of which is incorporated herein in its entirety by reference.
TECHNICAL FIELD
The present disclosure relates to a pattern forming method of forming a pattern in a semiconductor fabricating process.
BACKGROUND
In fabricating a semiconductor device, a lithography technology using deep ultraviolet (DUV) light with a wavelength of 193 nm and ArF gas as a light source has been predominantly used pursuant to the demand for miniaturization, thereby obtaining a fine pattern of about 40 nm.
Further, combining the above-described photolithography technology using the light with the wavelength of 193 nm (ArF), as a basic technology, with a self-aligned double patterning (SADP) technology enables achievement of a miniaturization down to about 20 nm.
Meanwhile, a directed self-assembly (DSA) technology using a block copolymer has been proposed as a fine pattern forming technology which does not require an exposure apparatus.
In the DSA technology, for example, a block copolymer in which chains of A polymer and B polymer are bonded to each other at their ends is initially applied onto a substrate. Next, if the substrate is heated, the chains of the A polymer and B polymer randomly dissolved in a solid are subjected to phase separation, so that the regions of the A polymer and B polymer are regularly arranged. Then, the block copolymer is patterned by removing any one of the regions of the A polymer and B polymer to form a mask with a predetermined pattern. An example of the block copolymer includes a copolymer in which polystyrene (PS) and polymethyl methacrylate (PMMA) are bonded. In such block copolymer, a fine pattern up to 10 nm may be formed.
However, a photoresist for 193 nm exposure has a structurally insufficient strength. In this case, if the photoresist is formed in a fine pattern, there is a risk that the pattern may collapse due to wet development. Further, the roughness (e.g., line edge roughness (LER) or the like) of the pattern increases due to image blur caused by the wet development. Furthermore, the photoresist film may have a roughened surface due to low resistance to dry etching (i.e., plasma etching) conducted after the formation of the pattern, or disappearance of the film may occur due to low mask selectivity. This may cause various problems, e.g., deterioration in shape of an etched pattern.
Additionally, even in the DSA technology, the pattern may collapse in the wet development. Further, the mask selectivity being low in an etching process may cause problems to obtain a desired pattern. Furthermore, it is required to form a guide pattern for obtaining the desired pattern. However, variations of the guide pattern affect the pattern to thereby make the process difficult.
SUMMARY
The present disclosure provides a pattern forming method in which pattern collapse may not occur, the roughness of a pattern may be decreased, mask selectivity may be increased, and a fine pattern may be obtained without using a guide pattern.
According to an aspect of the present disclosure, a pattern forming method is disclosed. The method includes forming a pattern forming material film on a substrate as an etching target film, the pattern forming material film having an exposing section that has porosity upon exposure and a non-exposing section, patterning and exposing the pattern forming material film for the exposing section to have the porosity, selectively infiltrating a filling material into voids of the exposing section to reinforce the exposing section, and removing the non-exposing section of the pattern forming material film by dry etching to form a predetermined pattern.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present disclosure, and together with the general description given above and the detailed description of the embodiments given below, serve to explain the principles of the present disclosure.
FIG. 1 is a flowchart illustrating a pattern forming method in accordance with an embodiment of the present disclosure.
FIGS. 2A to 2D are sectional views of processes illustrating the pattern forming method in accordance with the embodiment of the present disclosure.
FIG. 3 is a sectional view illustrating a state of a case where a filled portion is formed in an entirety of an exposing section in forming the filled portion by infiltrating a filling material thereto.
 DETAILED DESCRIPTION
Reference will now be made in detail to various embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one of ordinary skill in the art that the present disclosure may be practiced without these specific details. In other instances, well-known methods, procedures, systems, and components have not been described in detail so as not to unnecessarily obscure aspects of the various embodiments.
FIG. 1 is a flowchart illustrating a pattern forming method according to an embodiment of the present disclosure, and FIGS. 2A to 2D are sectional views of processes thereof.
First, a DSA material film 11 is formed on a surface of a semiconductor wafer 10 as a target film to be etched (Process 1; FIG. 2A).
As the DSA material film 11, for example, a block copolymer in which a first polymer chain and a second polymer chain are bonded to each other at their ends may be used. An example of the block copolymer may include a copolymer in which polystyrene (PS) and polymethyl methacrylate (PMMA) are bonded. The DSA material film 11 is formed on the semiconductor wafer 10 by a coating method. The coating method may include a spin coating or slit coating.
Next, a pattern exposure is performed on the DSA material film 11 (Process 2; FIG. 2B).
As a result of the pattern exposure, an exposing section 12 becomes a porous section made of a second polymer, e.g., PMMA, while the DSA material remains on a non-exposing section 13. DUV light with a wavelength of 193 nm using ArF gas, which is predominantly used in the recent photolithography technology, can be used as exposure light. With this manner, a pattern with a half pitch of 40 nm can be formed. In addition, finer patterns may also be formed using extreme ultraviolet (EUV) light (wavelength of 13.5 nm) with a shorter wavelength or an electron beam (EB).
Next, a filling material such as particles is selectively infiltrated into voids of at least a surface of the exposing section 12 (Process 3; FIG. 2C).
This process is for reinforcing the porous exposing section 12, and as a result, a filled portion 14 is formed on the at least surface of the exposing section 12.
For the filling material, it is possible to employ reactant materials which become predetermined materials by reactions, nano particles, organic metal compounds (complexes, alkoxides, and the like), and solutions of derivatives of carbon nano tubes or nano fullerenes. The reactant materials may include cyclopentasilane in which the voids are filled with aSi or SiN by reactions. The nano particles may include colloidal silica (SiO2), Si nano particles, TiO sol, SnO sol, CeO, HfO, ZrO, Ag, Cu and Au. The organic metal compounds may include those that are decomposed to form any one of Al, AlO, ZrO, TiO, W and Si. Further, in case of using the solutions of derivatives of carbon nano tubes or nano fullerenes as the filling material, the carbon nano tubes or nano fullerenes are filled into the voids.
As for the infiltration method, a thermal diffusion method may be used. In addition, if organic metal compounds are used as the filling material, hydrolysis may be utilized. Moreover, a method using supercritical fluids may also be employed. When the thermal diffusion method is used, the filling material is diffused into the voids by heating the semiconductor wafer, for example, to about room temperature (23 degrees C.) to 150 degrees C. On the other hand, when the hydrolysis of the organic metal compounds is used, the voids are first filled with the organic metal compounds and then hydrolyzed. As a result, the voids are filled with any one of Al, AlO, ZrO, TiO, W and Si. In the method using supercritical fluids, the filling material is infiltrated into the voids by using the nano permeability of the supercritical fluids (e.g., supercritical CO2).
As such, the filled portion 14 is formed by infiltrating the filling material into the voids on the at least surface of the porous exposing section 12, so that the exposing section is reinforced. As shown in FIG. 3, it is possible to form the entire exposing section 12 with the filled portion 14, thereby obtaining superior effects.
Next, a predetermined pattern is formed by removing the non-exposing section 13 via dry etching (Process 4; FIG. 2D).
For example, anisotropic etching by using a reactive ion etching (RIE) method may be used in the removal of the non-exposing section 13. Since the filled portion 14 formed on at least the surface of the exposing section 12 has been reinforced by the filling material, most part of the filled portion are not removed by RIE, while only the non-exposing section 13 is substantially removed. In this manner, a predetermined pattern 15 can be formed.
As shown in FIG. 3, when the filled portions 14 are formed over the entire exposing section 12, anisotropy is not required and a pattern can be formed at a higher rate by using ashing through oxygen plasma as the dry etching method.
In accordance with the above-described pattern forming method, since at least the surface of the remaining exposing section 12 is reinforced by the filled portion 14, the mask selectivity can be increased in a subsequent etching process. Further, since the pattern is formed by the dry etching method, it is possible to increase the height of the pattern.
Moreover, since the pattern is formed without using the wet development, the pattern is not likely to collapse. In addition, since the image blur is not caused by the wet development, the roughness of the pattern can be lowered.
Further, it is not necessary to use an anti-reflection film or a guide pattern. Thus, it is possible to avoid complexity of the processes while the pattern is not affected by the variation of the guide pattern.
Further, since the DUV light is used as the exposure light, a fine pattern with a half pitch of about 40 nm, which is a size obtainable in a current pattern forming technology by photolithography, can be formed. Moreover, when a SADP technology is combined, it is possible to obtain a fine pattern with a half pitch of down to about 20 nm. Further, upon application of the SADP technology, it is possible to widen the selectivity of the kinds of core materials.
Furthermore, as described above, using the EUV having a shorter wavelength, e.g., a wavelength of 13.5 nm, or an electron beam (EB) enables the formation of a finer pattern.
Various modifications can be made without being limited to the embodiment of the present disclosure. For example, although it has been described in the embodiment that the block copolymer consisting of PS and PMMA is used as the material for forming a pattern, other DSA material films consisting of a block copolymer in which ends of chains of first and second polymers are bonded to each other may be used. Moreover, the material for forming a pattern is not limited to such DSA material films. The pattern forming material may be any inorganic or organic materials, as long as a porous body can be formed therefrom by exposure.
Although it has been described in the embodiment that the DSA material film for forming a pattern is formed by a coating method, the present disclosure is not limited to this but a thin film forming technology such as CVD or the like may be used.
According to the present disclosure, the exposing section is formed to have porosity by patterning and exposing the material film for forming a pattern and is reinforced by selectively infiltrating filling material into voids of the exposing section; and a non-exposing section is then removed via dry etching to form a pattern. Thus, it is possible to prevent collapsing of the pattern and/or to reduce the roughness (LER) of the pattern. Accordingly, it is possible to increase mask selectivity and to form a fine pattern without using an anti-reflection film or guide pattern.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosures. Indeed, the novel methods and apparatuses described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosures. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosures.

Claims (11)

What is claimed is:
1. A pattern forming method in manufacturing a semiconductor device, comprising:
forming a pattern forming material film on a substrate as an etching target film, the pattern forming material film having an exposing section that has porosity upon exposure and a non-exposing section;
exposing only the exposing section of the pattern forming material film, whereby the exposing section becomes a porous section and the non-exposing section remains unchanged;
selectively infiltrating a filling material into voids of the porous exposing section to reinforce the exposing section; and
removing the non-exposing section of the pattern forming material film by dry etching to form a predetermined pattern.
2. The method of claim 1, wherein the pattern forming material film is a directed self-assembly material film made of a block copolymer in which a first polymer chain and a second polymer chain are bonded to each other at their ends, and the exposing section comprises the second polymer.
3. The method of claim 2, wherein the first polymer is polystyrene, and the second polymer is polymethyl methacrylate.
4. The method of claim 1, wherein the pattern forming material film is formed by a coating method.
5. The method of claim 1, wherein the filling material is any one of reactant materials that become predetermined materials by reactions, nano particles, organic metal compounds, and solutions of derivatives of carbon nano tubes or nano fullerenes.
6. The method of claim 1, wherein the infiltrating is performed by a thermal diffusion method.
7. The method of claim 1, wherein the infiltrating is performed by hydrolysis, if organic metal compounds are used as the filling material.
8. The method of claim 1, wherein the infiltrating is performed by using supercritical fluids.
9. The method of claim 1, wherein the dry etching for the non-exposing section is reactive ion etching or ashing.
10. The method of claim 1, wherein the exposing is performed by using a deep ultraviolet light.
11. The method of claim 1, wherein the exposing is performed by using an extreme ultraviolet light or an electron beam.
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US9466534B1 (en) 2015-12-09 2016-10-11 International Business Machines Corporation Cointegration of directed self assembly and sidewall image transfer patterning for sublithographic patterning with improved design flexibility
US9632408B1 (en) 2016-10-12 2017-04-25 International Business Machines Corporation Graphoepitaxy directed self assembly

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150066151A (en) * 2013-12-06 2015-06-16 삼성전자주식회사 Purification methods of block copolymers and methods of forming patterns using the block copolymers
KR102326126B1 (en) 2014-12-05 2021-11-15 삼성전자주식회사 Photoresist polymers, photoresist compositions, methods of forming patterns and methods of manufacturing semiconductor devices
KR102203353B1 (en) * 2018-12-12 2021-01-14 한국세라믹기술원 Manufacturing method of BCP-based metal nano pattern

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005029779A (en) 1999-06-07 2005-02-03 Toshiba Corp Pattern-forming material, pattern-forming method, method for producing porous structure, electrochemical cell, method for producing porous carbon structure, and the porous carbon structure
US20080073743A1 (en) * 2006-02-17 2008-03-27 Lockheed Martin Corporation Templated growth of semiconductor nanostructures, related devices and methods
JP2008149447A (en) 2006-08-11 2008-07-03 Rohm & Haas Denmark Finance As Manufacturing method for nanostructured pattern
JP2009088085A (en) 2007-09-28 2009-04-23 Tokyo Electron Ltd Semiconductor device manufacturing method, semiconductor device manufacturing apparatus, control program, and program storage medium
US20090130380A1 (en) * 1999-06-07 2009-05-21 Koji Asakawa Method for manufacturing pourous structure and method for forming pattern
US20110003069A1 (en) * 2009-07-03 2011-01-06 National Tsing Hua University Fabrication method of nanomaterials by using polymeric nanoporous templates

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2885311B2 (en) * 1994-11-01 1999-04-19 工業技術院長 Surface processing method using polymer phase separation
US5753374A (en) * 1995-11-27 1998-05-19 Dow Corning Corporation Protective electronic coating
JP4454931B2 (en) * 2002-12-13 2010-04-21 キヤノン株式会社 Manufacturing method of substrate having dot pattern and manufacturing method of columnar structure
JP4421582B2 (en) * 2006-08-15 2010-02-24 株式会社東芝 Pattern formation method
JP5484373B2 (en) * 2011-02-14 2014-05-07 東京エレクトロン株式会社 Pattern formation method

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005029779A (en) 1999-06-07 2005-02-03 Toshiba Corp Pattern-forming material, pattern-forming method, method for producing porous structure, electrochemical cell, method for producing porous carbon structure, and the porous carbon structure
US20090130380A1 (en) * 1999-06-07 2009-05-21 Koji Asakawa Method for manufacturing pourous structure and method for forming pattern
US20080073743A1 (en) * 2006-02-17 2008-03-27 Lockheed Martin Corporation Templated growth of semiconductor nanostructures, related devices and methods
JP2008149447A (en) 2006-08-11 2008-07-03 Rohm & Haas Denmark Finance As Manufacturing method for nanostructured pattern
JP2009088085A (en) 2007-09-28 2009-04-23 Tokyo Electron Ltd Semiconductor device manufacturing method, semiconductor device manufacturing apparatus, control program, and program storage medium
US20110003069A1 (en) * 2009-07-03 2011-01-06 National Tsing Hua University Fabrication method of nanomaterials by using polymeric nanoporous templates

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9466534B1 (en) 2015-12-09 2016-10-11 International Business Machines Corporation Cointegration of directed self assembly and sidewall image transfer patterning for sublithographic patterning with improved design flexibility
US9632408B1 (en) 2016-10-12 2017-04-25 International Business Machines Corporation Graphoepitaxy directed self assembly

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