CROSS-REFERENCE TO RELATED APPLICATIONS
The present application claims the benefit of the Singapore patent application 201108625-3 filed Nov. 21, 2011, the contents of which are incorporated herein by reference for all purposes.
TECHNICAL FIELD
Embodiments relate generally to a data storage medium and a method for generating a reference clock signal. Specifically, embodiments relate to a data storage device having a dedicated servo layer, and to a method for generating a reference clock signal for synchronization of read and write operations of a data storage device.
BACKGROUND
Electronic devices, including mobile computing and/or communication devices, are becoming smaller thereby driving the weight and size of data storage devices down, while requiring large storage capacity in the terabyte range and low power consumption. An increasing storage capacity would require the need for increased precision in tracking the movement of the read/write head.
Data storage devices, for example hard disk drives (HDDs), employ servo systems for tracking and controlling the movement of the read/write head. Conventional servo systems, e.g., as shown in FIG. 1A, employ embedded servo where the servo information runs radially across the tracks 110 from the inner diameter (ID) to the outer diameter (OD) of the disc 100 in a series of “servo wedges” 120 interspersed with data 130. Therefore, the servo information is only detected when the read/write head moves over these servo wedges 120. In between the servo wedges, no servo information is received by the head.
Data storage devices also employ dedicated servo, e.g. as shown in FIG. 1B, where the servo information is provided on a servo layer 150 distinct from the data recording layer 160. In addition, conventional servo systems typically employs ABCD servo-burst-signal pattern.
Furthermore, in conventional hard disk drives and similar data storage devices, the head either reads or writes, but cannot perform both operations simultaneously.
SUMMARY
Various embodiments provide a recording medium. The recording medium may include a dedicated servo layer for providing servo information. The dedicated servo layer may include a plurality of tracks. A first track may include a first servo signal. A second track may include a second servo signal. The first servo signal and the second servo signal may include a plurality of common transitions. The common transitions may be provided at a pre-determined frequency.
Various embodiments provide a method for generating a reference clock signal for synchronization of at least one of a read operation and a write operation of a data storage device. The method may include generating the reference clock signal based on a plurality of tracks in a dedicated servo layer of the data storage device. A first track may include a first servo signal. A second track may include a second servo signal. The first servo signal and the second servo signal may include a plurality of common transitions, wherein the common transitions are provided at a pre-determined frequency.
BRIEF DESCRIPTION OF THE DRAWINGS
In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments are described with reference to the following drawings, in which:
FIG. 1A shows a disk surface with embedded servo, and FIG. 1B shows a dual layer medium with dedicated servo.
FIGS. 2A and 2B shows a recording medium according to various embodiments.
FIG. 3 shows a media structure with dedicated servo layer.
FIG. 4 shows a flow diagram illustrating a method for generating a reference clock signal according to various embodiments.
FIG. 5 shows a data storage device according to various embodiments.
FIG. 6A and FIG. 6B show servo information in accordance with various embodiments.
FIG. 7 shows a block diagram for timing recovery according to an embodiment.
DESCRIPTION
In general, a head-positioning servomechanism is provided in a data storage device, e.g. a hard disk drive (HDD), which acts as a control system. The control system may position the head (e.g. read/write (R/W) head) which is mounted on an actuator over a desired data track of a storage medium and reposition the head from one data track to another.
In a HDD servo control system, the position of the head relative to the center of the desired data track, and therefore the position error signal (PES), may be sensed and used by the servo system to generate the appropriate commands to the actuator, which in turn moves the head in an effort to reduce the position error. PES is a signal proportional to the relative difference of the positions of the centre of the head and the nearest track centre. Therefore, the PES may provide an indication of the position of the head relative to the storage medium, for example the position of the head relative to a data track, and whether the head is positioned at the centre of the data track (on track) or shifted relative to the centre of the data track (off track) and the magnitude of the shift, such that the position of the head may then be adjusted.
In a dedicated servo implementation, one disk surface (servo layer) is dedicated to store the position data referred to as servo data or servo signal. The servo layer may be a buried layer arranged beneath the data recording layer and may have a perpendicular or a longitudinal magnetization orientation for providing magnetic information for determining the location of the head in relation to the storage medium. The servo information is provided on the servo layer distinct from the data recording layer so as to allow continuously available servo readback to enable continual position feedback thereby providing continual position detection without utilizing any of the recording layer for position detection. This may provide higher positioning accuracy through continual location determination, while also removing the servo sectors/tracks from the recording layer, thereby increasing surface utilization of the storage space in the recording layer and further increasing the data recording track density by increasing the track positioning accuracy. Further, the servo layer and data layer may be put on the same side and they may be read and/or processed together; this may also be referred to as dedicated servo.
The dedicated servo layer may have a continuous track structure having a plurality of servo tracks in a concentric arrangement. Adjacent servo tracks may be alternately assigned different frequency signals, having respective frequencies f1 and f2, as illustrated in FIGS. 2A and 2B for a portion of the servo layer 200 towards its inner diameter, showing four servo tracks 202 a, 202 b, 202 c, 202 d. In this configuration, the head of the data storage device may be positioned in between two adjacent tracks (e.g. 202 a and 202 b; 202 b and 202 c), for example at the boundary of the two adjacent tracks, and may be able to obtain a readback servo signal having frequencies f1 and f2.
Therefore, in various embodiments of a dedicated servo system, each servo track has a single frequency. The position error signal (PES) may be produced from the frequency based servo signal, including dual/triple frequency based signals. Using the dual frequency based servo signal as an example, during track following, the center of the head may be positioned at the middle of two adjacent servo tracks, whereby the head picks up a readback servo signal having two frequencies from the two adjacent servo tracks at the same time.
For a data storage device with an embedded servo, the clock used to trig the write buffer is a free-run fixed clock during the writing of data. In order to decode the sequential readback data correctly, timing recovery is needed to generate a synchronization signal such that the readback data is sampled synchronously. The timing recovery is done by including a preamble in front of the data sectors and scrambling the user data, wherein the preamble is used to initialize a digital phase lock loop (DPLL) and the scrambling is used to prevent transitions in user data which may cause the DPLL to lose the phase lock. The scrambling of user data may reduce the coding efficiency for the read write channel.
The data storage device may include a memory which is for example used in the processing carried out by the data storage device. A memory used in the embodiments may be a volatile memory, for example a DRAM (Dynamic Random Access Memory) or a non-volatile memory, for example a PROM (Programmable Read Only Memory), an EPROM (Erasable PROM), EEPROM (Electrically Erasable PROM), or a flash memory, e.g., a floating gate memory, a charge trapping memory, an MRAM (Magnetoresistive Random Access Memory) or a PCRAM (Phase Change Random Access Memory).
In the context of various embodiments, a “circuit” may be understood as any kind of a logic implementing entity, which may be special purpose circuitry or a processor executing software stored in a memory, firmware, or any combination thereof. Thus, in an embodiment, a “circuit” may be a hard-wired logic circuit or a programmable logic circuit such as a programmable processor, e.g. a microprocessor (e.g. a Complex Instruction Set Computer (CISC) processor or a Reduced Instruction Set Computer (RISC) processor). A “circuit” may also be a processor executing software, e.g. any kind of computer program, e.g. a computer program using a virtual machine code such as e.g. Java. Any other kind of implementation of the respective functions which will be described in more detail below may also be understood as a “circuit” in accordance with an alternative embodiment.
In the context of various embodiments, the data storage device may be a hard disk drive (HDD).
In the context of various embodiments, the term “head” may include a magnetic head. In addition, the “head” may refer to the read/write head for reading/writing information or data from/to a storage/recording medium. The head includes a reader and a writer. The head is positioned over a storage medium and the reader may read signal or information from the storage medium and the writer may write information to the storage medium.
In the context of various embodiments, a data storage device includes a spindle which refers to a mechanical part, which may be rotatable, and that may serve as an axis for a rotatable part held by the spindle. As a non-limiting example, in a hard disk drive, the spindle holds a circular disk (or platter) as storage medium that holds data. A spindle index signal is generated each time the spindle makes a rotation, thereby providing an indication that the spindle has made one rotation (360-degree rotation) in a period between the generation of one spindle index signal and the generation of the next spindle index signal.
Various features described herein in the context of the data storage device may analogously hold true for the method of generating a reference clock signal for synchronization of at least one of a read operation or a write operation of a data storage device, and vice versa.
Various features described above in the context of the method of generating a reference clock signal for synchronization of at least one of read and write operations of a data storage device may analogously hold true for the corresponding device for generating the reference clock signal.
FIG. 3 shows a media structure 300 having a magnetic data layer 302, and a physically separate magnetic layer as a dedicated servo layer 304 for storing the servo information. However, a writing field from a recording/writing head 306 may affect both the magnetic data layer 302 and the dedicated servo layer 304. In other words, the servo information in the servo layer 304 may be overwritten by the writing field. FIG. 3 shows the structure and system configuration of magnetic recording medium with dedicated servo.
Thus, it is desirable that the servo layer 304 has a nucleation field which is high enough to be unaffected by the writing field for writing data on the magnetic data layer 302 (in other words, unlimited writing on the magnetic data layer 302). Therefore, the switching field of the servo layer 304 should be large so that it is harder to write on the servo layer 304 than the magnetic data layer 302.
Further, it is also desirable to place the servo layer 304 below the magnetic data layer 302. The servo layer 304 is arranged further from the recording/writing head 306 than the magnetic data layer 302. The head field decay to the servo layer 304 is larger due to the larger magnetic space from the recording/writing head 306 to the servo layer 304. The head field decay to the servo layer 304 may still be large even if a soft underlayer 308 is arranged below the servo layer 304.
As such, it becomes more difficult to write servo information onto the servo layer 304. A conventional recording/writing head is not able to write servo information onto the servo layer 304. The servo information on servo layer is written with a wide writer head in servo writing process.
With the dedicated servo layer, the majority or all of servo information may be moved from data recording layer to the servo layer. With more area for servo signals, the increased servo sampling rate and the improved signal to noise ratio of servo positioning signal may increase the track density significantly.
In the dedicated servo recording system, the positioning error signal (PES) may be produced from the dual frequency based single tone signal. One servo track may have a single frequency. During track following, the center of the head may stay in between of two servo tracks, A and B. It may pick up the two frequencies at the same time. When it moves more into servo track A, the reader may pick up more fA signal and less fB, signal, vice versa. The PES of (VfA−VfB)/(VfA+VfB) is feedback to servo control loop for track following, wherein V may represent the respective amplitude of different frequencies.
According to various embodiments, the continuous servo signals may be used to produce a reference signal for timing recovery in reading operation and for writing process to achieve synchronized writing. With the reference signal, the phase lock loop may control the writing or the reading with removing the time error due to various sources in magnetic recording system.
According to various embodiments, a recording medium may be provided. The recording medium may include a dedicated servo layer for providing servo information. The dedicated servo layer may include or may be a plurality of tracks. A first track may include a first servo signal. A second track may include a second servo signal. The first servo signal and the second servo signal may include a plurality of common transitions. The transitions may be provided at a pre-determined frequency.
The plurality of common transitions may include transitions on a cross track direction.
The first servo signal may include or may be a signal of a first frequency. The second servo signal may include or may be a signal of a second frequency. The first frequency and the second frequency may have an integer least common multiple.
The first frequency and the second frequency may have a ratio of n:m with integer numbers n and m.
The first frequency and the second frequency may have a ratio of n+1:n with an integer number n.
The servo signals may include or may be servo bursts.
Each servo pattern may include or may be a plurality of alternately arranged preambles and servo bursts.
Each servo signal may include information for providing positioning information.
According to various embodiments, a data storage device may be provided. The data storage device may include the recording medium (for example as described above).
The recording medium may further include a data layer configured to record data therein.
The data storage device may further include a phase lock loop circuit configured to generate a reference clock signal for synchronization of at least one of read and write operations, based on the servo signals.
FIG. 4 shows a flow diagram 400 illustrating a method for generating a reference clock signal for synchronization of at least one of a read operation and a write operation of a data storage device in accordance with various embodiments. In 402, the reference clock signal may be generated based on a plurality of tracks in a dedicated servo layer of the data storage device. A first track may include a first servo signal. A second track may include a second servo signal. The first servo signal and the second servo signal may include a plurality of common transitions. The common transitions may be provided at a pre-determined frequency.
The plurality of common transitions may include or may be transitions on a cross track direction
The method may further include: initializing a phase lock loop circuit upon reading of the first signal and the second signal, so as to generate the reference clock signal synchronous with the pre-determined frequency.
The first servo signal may include or may be a signal of a first frequency. The second servo signal may include or may be a signal of a second frequency. The first frequency and the second frequency may have an integer least common multiple.
The first frequency and the second frequency may have a ratio of n:m with integer numbers n and m.
The first frequency and the second frequency may have a ratio of n+1:n with an integer number n.
The servo signals may include or may be servo bursts.
Each servo pattern may include or may be a plurality of alternately arranged preambles and servo bursts.
Each servo signal may include information for providing positioning information.
FIG. 5 shows a data storage device 500 according to various embodiments. The data storage device 500 may include a clock reference generation circuit 502 configured to generate a reference clock signal for synchronization of at least one of a read operation and a write operation of a data storage device. The clock reference generation circuit 502 may be configured to generate the reference clock signal based on a plurality of tracks in a dedicated servo layer of the data storage device. A first track may include or may be a first servo signal. A second track may include or may be a second servo signal. The first servo signal and the second servo signal may include a plurality of common transitions. The common transitions may be provided at a pre-determined frequency.
The clock reference generation circuit 502 may include a phase lock loop circuit.
According to various embodiments, devices and methods may be provided for synchronization signal generation from synchronized two-frequency servo bursts in dedicated servo.
According to various embodiments, devices and methods may be provided for synchronization signal generation from synchronized two-frequency servo bursts in dedicated servo.
In the dedicated servo system, the PES may be produced from the dual/triple frequency based single tune signals. One servo track may have a single frequency. During track following, the center of the head may stay at the middle of two servo tracks and it picks up two frequency signals at the same time.
For the phase lock loop, it may precisely lock to the phase of one single frequency instantly. But if the head is moving away from the locked frequency track, the signal may become weak and the performance of the PLL may degrade.
According to various embodiments, the two servo frequencies may be arranged in the least common multiple of fraction. The signals may be written with proper phase synchronization.
FIG. 6A shows servo information 600 according to various embodiments. Several tracks (k, k+1, k+2, k+3) are shown, each including a preamble 602 and servo bursts 604. The servo bursts provide signals with such frequencies, that an alternation of the frequency is provided. For example, track k and track k+2 each may provide a first frequency 606 (as indicated by A in FIG. 6A), and track k+1 and track k+3 each may provide a second frequency 608 (as indicated by B in FIG. 6A).
In FIG. 6A, servo information according to various embodiments is shown which may be recorded in the dedicated servo layer with the frequency ratio (fA/fB)=2.
FIG. 6A shows the servo information according to various embodiments recorded in the dedicated servo layer. A preamble with a single tone signal may be stitch written along cross track direction from inner diameter to outer diameter. The preamble may be used to initialize the digital phase lock loop (DPLL). The dual frequency signals in servo track A and B may have the frequency ratio of (fA/fB)=2. With stitch written servo signal and frequency arrangement in FIG. 6A, the dash line of servo A may always be aligned with the transition line of servo B. No matter which position the reader moves, it may always pick up an fB frequency. In this case, the fB signal may always be used by DPLL as the reference for timing recovery.
According to various embodiments, devices and methods may be provided which provide a technology for timing reference.
A preamble may be used to initialize a DPLL (digital PLL).
The ratio of Frequency (A): frequency (B) may be 2:1 as shown in FIG. 6A, and the frequency of synchronized bit may be ½ of frequency of A or the same frequency of B. Low frequency may cause problem. The maximum of frequency may be limited by spacing loss. A frequency of a preamble may also be same as A.
FIG. 6B may be the proposed servo information recorded in the dedicated servo layer with the frequency ratio (fA/fB)=3/2 or even less. Several tracks (k, k+1, k+2, k+3) are shown, each including a preamble 612 and servo bursts 614. The servo bursts may provide signals with such frequencies, that an alternation of the frequency is provided. For example, track k and track k+2 each may provide a first frequency 616 (as indicated by A in FIG. 6B), and track k+1 and track k+3 each may provide a second frequency 618 (as indicated by B in FIG. 6B).
In FIG. 6A, the frequency ratio may be set at (fA/fB)=3/2. In this case, the stitched transitions may be aligned at every 3 cycles of fA and every 2 cycles of fB. The reference frequency used by DPLL may be fA/3. When the frequency of servo A and servo B becomes close, the signal intensity of two frequency signals may be more comparable. It may be preferred when the spacing loss of servo signal reading is significant.
It can also be extended to (fA/fB)=(n+1)/n. The frequency of reference signal may be fA/(n+1). Assume (fA/fB)=m/n (m>n), fA=1/mT, and fB=1/nT, where T is a time period. When the least common multiple of m and n, k=LCM(m,n), the reference frequency at fr=1/kT may be used for DPLL. The reference frequency may be pfr as well, where p may be an integer.
The ratio of Frequency (A): frequency (B) may be 3:2 to solve low frequency problem, by letting frequency of A closer to that of B. The frequency of synchronized bit may be ⅓ of frequency of A or ½ of frequency of B. According to various embodiments, other ratios, for example 4:3 or 5:4 may be provided.
FIG. 7 shows a block diagram for timing recovery according to an embodiment.
In FIG. 7, servo pattern and data from the recording medium are separated at servo & data separator 701. Servo data from the dedicated servo layer, for example, the signal representing the preamble in the servo pattern, may be input to a phase detector 703. The output of the phase detector 703 is input to a phase update 705 and a frequency update register 707. And a VCO (voltage controlled oscillator) 709 is configured to receive signals output from the phase update 705 and the frequency update register 707. The output signal of the VCO 709 is input to a phase mixer 711, which receives a signal output from a phase register 713 and output a phase mixed signal. The phase mixed signal output from the phase mixer 711 is converted to a digital signal at a ADC (analog-to-digital converter) 715, and the digital signal output from the ADC 715 is transmitted to the servo & data separator 701.
FIG. 7 shows is the diagram of digital phase lock loop (DPLL) used for the time recovery from the servo signals in dedicated servo layer. In other words, FIG. 7 shows the diagram of using DPLL to generate the timing recovery signal from the servo signals. The readback signal including both data and servo signals may be injected into analogy to digital converter (ADC). The digitized signal may be sent to the phase detector with reference phase information from previous bits. The phase error signal may be sent to phase and frequency registers with the updated phase and frequency. The new phase and frequency signals may be fed into voltage controlled oscillator (VCO) to produce the updated reference frequency signal. Then, the updated phase information may be feedback to the ADC and the mixed servo/data signals for the timing recovery and to provide the synchronized positioning signal along down track direction for synchronized writing and reading.
According to various embodiments, devices and methods may be provided which may provide a technology of using DPLL to do timing recovery.
A ratio of Frequency (A): frequency (B) may be M:N.
A preamble may be used to initialize the DPLL. The bursts may be sampled at LCM(M,N), which will not miss any transitions in A/B. As such, wherever the head stays, it may not miss the synchronous bit. The synchronous bit may keep DPLL working. If the data layer is written synchronously, while reading data-layer, it may not be needed to separate signals from servo and date layer phase detector. No matter what reading/writing data layer, as long the read-back signal is there, the DPLL may be working. Only one preamble may be needed.
According to various embodiments, a magnetic recording system may have a dedicated servo layer in recording medium. In the dedicated servo layer, a short length of single tone signals may be stitch written from inner diameter to outer diameter of disk medium, and it may be named as preamble. Followed by preamble, the continuous servo signals may be written at dual frequencies, fA and fB, alternatively.
According to various embodiments, the ratio of dual frequencies may be at (fA/fB)=2.
According to various embodiments, the reader may always reproduce the frequency signal at fB and may use it as the reference signal for digital phase lock loop (DPLL).
According to various embodiments, the DPLL may be used to lock the position along down track direction for the synchronized writing and reading.
According to various embodiments, the number of preamble along an entire track may only be one for the initialization of DPLL.
According to various embodiments, the number of preamble along a track may be more than one.
According to various embodiments, the ratio of dual frequencies is at (fA/fB)=(n+1)/n, where n may be an integer.
According to various embodiments, the frequency of the DPLL reference may be at fA/(n+1).
According to various embodiments, the ratio of dual frequencies may be (fA/fB)=m/n (m>n), fA=1/mT, and fB=1/nT, where T may be a time period.
According to various embodiments, the least common multiple k=LCM(m,n), and the reference frequency at fr=1/kT may be used for DPLL.
According to various embodiments, the reference frequency may be pfr, where p is an integer.
According to various embodiments, in the DPLL system, the phase information of previous bit or preamble may be used to provide the phase reference of coming servo signals for timing recovery purpose.
While the invention has been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The elements of the various embodiments may be incorporated into each of the other species to obtain the benefits of those elements in combination with such other species, and the various beneficial features may be employed in embodiments alone or in combination with each other. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.