US8902675B2 - Semiconductor memory device - Google Patents
Semiconductor memory device Download PDFInfo
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- US8902675B2 US8902675B2 US13/604,070 US201213604070A US8902675B2 US 8902675 B2 US8902675 B2 US 8902675B2 US 201213604070 A US201213604070 A US 201213604070A US 8902675 B2 US8902675 B2 US 8902675B2
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- column
- sense amplifier
- data latch
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/106—Data output latches
Definitions
- Embodiments described herein relate generally to a semiconductor memory device.
- semiconductor memory devices such as a NAND flash memory employ a configuration in accordance with the miniaturization in which one control circuit, one arithmetic circuit, one data bus, and the like are shared in units of one or more cell columns. Accordingly, the circuit scale of the control circuit and the like can be deceased, whereby an increase in the chip area can be suppressed. Particularly when one control circuit and the like are shared in units of a plurality of cell columns, it is large effective to suppress the chip area.
- a total number of cell columns of the semiconductor memory device is limited to a multiple of n.
- FIG. 1 is an exemplary block diagram illustrating a semiconductor memory device according to a first embodiment
- FIG. 2 is a diagram illustrating a configuration example of a sense amplifier and a data latch of a semiconductor memory device according to the embodiment
- FIG. 3 is a diagram illustrating the configurations of a sense amplifier-data latch unit of a semiconductor memory device according to a comparative example of the embodiment and a column control circuit using the sense amplifier-data latch units;
- FIG. 4 is a diagram illustrating configuration examples of a sense amplifier-data latch unit of a semiconductor memory device according to the embodiment and a column control circuit using the sense amplifier-data latch units;
- FIG. 5 is a diagram illustrating configuration examples of a sense amplifier-data latch unit of a semiconductor memory device according to a second embodiment and a column control circuit using the sense amplifier-data latch units;
- FIG. 6 is a diagram illustrating a configuration example of a sense amplifier-data latch unit of a semiconductor memory device according to the embodiment.
- a semiconductor memory device includes a memory cell array that includes a plurality of cell columns each configured by a plurality of memory cells and a column control circuit that includes a plurality of sense amplifier-data latch units each including a plurality of sense amplifiers that detect and amplify data of the memory cells and a plurality of data latches.
- One of the plurality of sense amplifier-data latch units is a first sense amplifier-data latch unit and another of the plurality of sense amplifier-data latch units is a second sense amplifier-data latch unit, the first sense amplifier-data latch unit and the second sense amplifier-data latch unit having different numbers of the cell columns capable of being handled.
- FIG. 1 is a block diagram illustrating a semiconductor memory device according to a first embodiment.
- a NAND flash memory is employed as the semiconductor memory device, this embodiment can be applied not only to NAND flash memories but also to all the semiconductor memory devices using a sense amplifier and a data latch.
- the NAND flash memory includes a NAND chip 10 and a controller 11 that controls the NAND chip 10 .
- the memory cell array 1 is configured by arranging a plurality of memory cells MCs each having a charge accumulating layer in a matrix pattern.
- a unit formed by a plurality of memory cells MCs aligned in the column direction may be referred to as a “cell column”.
- a row control circuit 2 On the periphery of the memory cell array 1 , a row control circuit 2 , a column control circuit 3 , and a voltage generating circuit 8 are arranged. These row control circuit 2 and the column control circuit 3 receive instructions from a sequence control circuit 7 to be described later and write or read data with respect to the memory cell array 1 in units of pages.
- the row control circuit 2 drives a word line and a selection gate line of the memory cell array 1 .
- the column control circuit 3 for example, includes sense amplifiers and data latches corresponding to one page. Data corresponding to one page, which is read by the column control circuit 3 , is output to an external I/O terminal through an I/O buffer 9 . In addition, the write data supplied from the I/O terminal is loaded into the column control circuit 3 . The write data corresponding to one page is loaded into the column control circuit 3 . A row address signal and a column address signal are input through the I/O buffer 9 and are transmitted to the row control circuit 2 and the column control circuit 3 .
- a row address register 5 a maintains an erasing block address or a page address.
- a first column address used for loading write data before the start of a write sequence or a first column address used for a read sequence is input to the column address register 5 b .
- the column address register 5 b maintains the input column address until a write enable /WE or a read enable /RE is toggled in a predetermined condition.
- bit line is connected to each sense amplifier.
- the bit line is connected to a memory cell of the memory cell array 1 . Data transmission and data reception between the memory cell and the sense amplifier are performed through the bit line.
- the sense amplifier can detect, amplify, and maintain data of the memory cell.
- a plurality of the bit lines may be connected to the sense amplifier.
- a plurality of the data latches can receive data of the memory cells from the sense amplifier and can maintain the data.
- the logic control circuit 6 receives commands of control signals such as a chip enable signal /CE, a command enable signal CLE, an address latch enable signal ALE, a write enable signal /WE, and a read enable signal /RE that are transmitted from the controller 11 .
- the logic control circuit 6 controls the input of an address and the input/output of data based on the commands.
- the logic control circuit 6 instructs the sequence control circuit 7 to perform sequence control of a read operation, a write operation, or an erasing operation.
- the voltage generating circuit 8 is controlled by the sequence control circuit 7 and generates predetermined voltages that are required for various operations.
- the controller 11 controls the writing or reading of data in a condition that is appropriate to the current writing state of the NAND chip 10 .
- the sense amplifier and the data latch of the semiconductor memory device will be described.
- the sense amplifier and the data latch are included in the column control circuit 3 .
- FIG. 2 is a diagram illustrating the configuration of the sense amplifier and the data latch of the semiconductor memory device according to this embodiment.
- the sense amplifier S/A and the data latch DL are interconnected through a data bus DB.
- the sense amplifier S/A and the data latch DL are controlled by the control circuit CT.
- This control circuit CT includes a circuit that performs simple decoding of data or temporary storage of data.
- the arithmetic circuit AR is connected to the sense amplifier S/A and the data latch DL through the data bus DB.
- the arithmetic circuit AR performs AND/OR of data of the sense amplifier S/A and data of the data latch DL or a logical operation that is necessary for determining the completion of data writing.
- This arithmetic circuit AR as illustrated in FIG. 3 , may be arranged between the sense amplifier S/A and the data latch DL.
- the arithmetic circuit AR is configured to be shared in units of cell columns. Accordingly, for example, in a case where one cell column is configured as 8 bits, data processing of 8 bits can be performed by one arithmetic circuit AR. Accordingly, compared to a conventional semiconductor memory device that is configured by eight arithmetic circuits AR for each column, the chip area can be decreased. Similarly, by sharing the control circuit CT in units of cell columns, the chip area corresponding thereto is decreased as well. In a case where the control circuit CT and the arithmetic circuit AR are shared in units of a plurality of cell columns, the chip area is decreased further.
- the sense amplifier-data latch unit that includes the sense amplifier S/A, the data latch DL, the data bus DB, the control circuit CT, and the arithmetic circuit AR in FIG. 2 can be configured in units of a plurality of cell columns.
- a unit acquired by configuring the sense amplifier-data latch unit in units of a plurality of cell columns may be referred to as a “cell column unit”.
- FIG. 3 is a diagram illustrating the configurations of a cell column unit of a semiconductor memory device according to a comparative example and a column control circuit using the cell column unit.
- a cell column unit that can be in correspondence with n hereinafter, a cell column unit that can be in correspondence with n (here, n is an integer that is one or more) cell columns will be referred to as an “n cell column unit”.
- n cell column unit a cell column unit that can be in correspondence with n (here, n is an integer that is one or more) cell columns
- 8 cell columns are arranged in the row direction.
- the cell column unit illustrated in FIG. 3 is an “8-cell column unit”.
- the 8-cell column unit CU 8 illustrated in FIG. 3 has a layout in which eight sense amplifier sets S/AS ⁇ i> each formed by eight sense amplifiers S/A ⁇ i, 0> to S/A ⁇ i, 7> (here, i is an integer in the range of 0 to 7) aligned in the column direction at the same position in the row direction are aligned in the row direction at the same position in the column direction.
- the number of sense amplifiers S/A included in the 8-cell column unit CU 8 may be the same as that of the data latches DL.
- the 8-cell column unit CU 8 has a layout in which eight data latch set DLS ⁇ i> configured by eight data latches DL ⁇ i, 0> to DL ⁇ i, 7> (here, i is an integer in the range of 0 to 7) aligned in the column direction at the same position in the row direction are aligned in the row direction at the same position in the column direction.
- the sense amplifier set S/AS ⁇ i> and the data latch set DLS ⁇ i> correspond to the i-th cell column of the memory cell array 1 .
- control/arithmetic circuit CT/AR ⁇ i> and a common control circuit CCT ⁇ i> are arranged between the sense amplifier set S/AS ⁇ i> and the data latch set DLS ⁇ i>.
- the control/arithmetic circuit CT/AR ⁇ i> is a functional block that corresponds to the arithmetic circuit AR and the control circuit CT illustrated in FIG. 2 .
- a configuration that includes the sense amplifier set S/SA ⁇ i>, the data latch set DLS ⁇ i>, and the control/arithmetic circuit CT/AR ⁇ i> may be referred to as a “column set CC”.
- each one of the common control circuits CCT ⁇ 0 > to CCT ⁇ 7 > includes one or a plurality of common control circuits CCT 1 to CCT 4 having the following functions.
- the common control circuit CCT 1 transmits a control signal S 0 so as to be common to the control/arithmetic circuits CT/AR ⁇ 0 > to CT/AR ⁇ 7 > through a signal line SL 0 and controls the control/arithmetic circuits.
- the common control circuit CCT 2 selects one set aligned in the row direction out of the sense amplifiers S/A ⁇ i, 0> to S/A ⁇ i, 7> by using a control signal S 1 .
- the common control circuit CCT 2 selects one set out of the sense amplifiers S/A ⁇ 0, 0> to S/A ⁇ 7, 0>, S/A ⁇ 0, 1> to S/A ⁇ 7, 1>, . . . , S/A ⁇ 0, 7> to S/A ⁇ 7, 7>.
- the control signal S 1 is transmitted to the sense amplifiers S/A ⁇ 0, j> to S/A ⁇ 7, j> (here, j is an integer in the range of 0 to 7) so as to be common thereto through a signal line SL 1 (in the case of FIG. 3 , only the signal line SL 1 traversing the sense amplifiers S/A ⁇ 0, 1> to S/A ⁇ 7, 1> is illustrated) disposed for each set of the sense amplifiers S/A ⁇ 0, j> to S/A ⁇ 7, j>.
- the common control circuit CCT 3 selects one set aligned in the row direction out of the data latches DL ⁇ i, 0> to DL ⁇ i, 7> by using a control signal S 2 .
- the common control circuit CCT 3 selects one set out of the data latches DL ⁇ 0, 0> to DL ⁇ 7, 0>, DL ⁇ 0, 1> to DL ⁇ 7, 1>, . . . , DL ⁇ 0, 7> to DL ⁇ 7, 7>.
- the control signal S 2 is transmitted to the data latches DL ⁇ 0, j> to DL ⁇ 7, j> so as to be common thereto through a signal line SL 2 (in the case of FIG.
- the common control circuit CCT 4 temporarily stores data, which is common to the cell column units CU, for each cell column unit CU.
- the control/arithmetic circuit CT/AR ⁇ i> performs a control operation and a calculation operation that are necessary for data processing of the sense amplifier set S/AS ⁇ i> and the data latch set DLS ⁇ i>.
- a column set to be selected out of the column sets CC 0 to CC 7 is designated in accordance with a column selection signal SEL ⁇ 0:7> that is input to the control/arithmetic circuit CT/AR ⁇ i>.
- the control/arithmetic circuit CT/AR ⁇ i> corresponding to the cell column designated in accordance with the column selection signal SEL ⁇ 0:7> instructs the common control circuit CCT to perform the following or the like.
- control/arithmetic circuit CT/AR ⁇ i> may make a calculation such as an inversion of the data.
- the column control circuit 3 of the semiconductor memory device according to the comparative example, as illustrated in FIG. 3 is configured by aligning a plurality of the above-described 8-cell column units CU 8 in the row direction. For example, by aligning 128 8-cell column units CU 8 , a column control circuit 3 that can handle 1024 cell columns can be configured. In addition, in a case where eight redundant cell columns used for replacing cell columns are arranged, one additional 8-cell column unit CU 8 may be further added. In such a case, a column control circuit 3 can be configured which can handle a total of 1032 cell columns acquired by adding 1024 cell columns that are normally used and eight redundant cell columns.
- the number of cell columns, which the column control circuit 3 can handle can be adjusted only to a multiple of eight.
- the optimal number of redundant cell columns is 12, it is necessary to add two 8-cell column units CU 8 .
- the arrangement area of the sense amplifiers S/A and the data latches DL corresponding to four cell columns is in surplus. In other words, an unnecessary increase in the chip area of the semiconductor memory device is caused.
- the product yield of the semiconductor memory device is decreased.
- the number of cell columns that are normally used is 1024
- the number of cell columns for storing an error correction code (ECC) is 12
- the number of redundant cell columns is limited to 8m+4 (here, m is an integer).
- the column control circuit 8 is configured only by the 8 cell column units CU 8
- the number of redundant cell columns is limited to 8m+k (here, k is an integer).
- the number of cell columns that the column control circuit 3 can handle needs to be adjusted to one of discrete values depending on the number of cell columns that can be handled by the 8-cell column units CU 8 .
- the column control circuit is configured only by one kind of cell column units CU, the selection of the number of redundant columns is restricted, whereby in that a system according to an optimal number of redundant columns cannot be configured.
- the column control circuit 3 is configured by a plurality of kinds of cell column units. Accordingly, the number of cell columns that the column control circuit 3 can handle can be freely adjusted.
- FIG. 4 is a diagram illustrating configuration examples of a cell column unit of the semiconductor memory device according to this embodiment and a column control circuit 3 using the cell column units.
- the column control circuit 3 is configured by a 9-cell column unit CU 9 (second sense amplifier-data latch unit), of which the number of cell columns that can be handled is nine, in addition to the above-described 8-cell column unit CU 8 (first sense amplifier-data latch unit).
- the 9-cell column unit CU 9 has nine layouts of the column set of the 8-cell column unit CU 8 illustrated in FIG. 3 .
- the 9-cell column unit CU 9 has a layout to which an expanded column set CC 8 having a layout that is almost equal to that of the column set CC of the 8-cell column unit CU 8 .
- the expanded column set CC 8 includes a sense amplifier set S/AS ⁇ 8 >, a data latch set DLS ⁇ 8 >, and a control/arithmetic circuit CT/AR ⁇ 8 >.
- the number of sense amplifiers S/A included in the 9-cell column unit CU 9 and the number of the data latches DL may be configured to be the same.
- the 9-cell column unit CU 9 includes an expanded sense amplifier set S/AS ⁇ 8 > having a layout equal to the sense amplifier set S/AS ⁇ i> of the 8-cell column unit CU 8 in an area Aesa that is adjacent to an area Asa′ corresponding to the area Asa, in which the sense amplifier sets S/AS ⁇ 0 > to S/AS ⁇ 7 > of the 8-cell column unit CU 8 are arranged, in the row direction at the same position in the column direction.
- the 9-cell column unit CU 9 includes an expanded data latch DLS ⁇ 8 > having a layout equal to the data latch DLS ⁇ i> of the 8-cell column unit CU 8 in an area Aedl that is adjacent to an area Adl′ corresponding to the area Adl, in which the data latch sets DLS ⁇ 0 > to DLS ⁇ 7 > of the 8-cell column unit CU 8 are arranged, in the row direction at the same position in the column direction.
- a control/arithmetic circuit CT/AR ⁇ i> having a layout equal to that of the control/arithmetic circuit CT/AR ⁇ i> of the 8-cell column unit CU 8 is included between the sense amplifier set SAS ⁇ 8 > and the data latch set DLS ⁇ 8 >.
- signal lines SL 0 , SL 1 , and SL 2 are extended in the row direction and are connected to the expanded control/arithmetic circuit CT/AR ⁇ 8 >, the expanded sense amplifier set S/AS ⁇ 8 >, and the expanded data latch set DLS ⁇ 8 >, and a column selection signal SEL ⁇ 8 > used for selecting the expanded control/arithmetic circuit CT/AR ⁇ 8 > is prepared, whereby the 9-cell column unit CU 9 can be configured.
- a common control circuit CCT (second common control circuit) of the 9-cell column unit CU 9 may have the same configuration as that of the common control circuit CCT (first common control circuit) of the 8-cell column unit CU 8 .
- the common control circuit CCT ⁇ 8 > of the 9-cell column unit CU 9 may be omitted.
- the 9-cell column unit CU 9 is generated. Accordingly, the circuit design can be made in an easy manner.
- a case will be considered in which a column set CC 0 of a certain 8-cell column unit CU 8 is defective.
- the control circuit 7 skips the defective column set CC 0 and transmits a signal used for selecting the column set CC 0 of the 8-cell column unit CU 8 , which is adjacent thereto, to the column control circuit 3 .
- the control/arithmetic circuit CT/AR ⁇ 0 > of the 8-cell column unit CU 8 which is adjacent thereto, is selected, and data stored in the data latches DL ⁇ 0, 0> to DL ⁇ 0, 7> is output to the I/O.
- the data may be temporarily stored and used for a calculation by the control/arithmetic circuit CT/AR ⁇ 1 >.
- the column set CC 0 is skipped as a defective set, there is a lack of one column set CC.
- the lack of the column set CC is supplemented with the column set CC 8 of the 9-cell column unit CU 9 .
- the control circuit 7 may be configured to replace the column selection signal SEL ⁇ 0 > with a column selection signal SEL ⁇ 8 > of the 9-cell column unit CU 9 and transmit the column selection signal SEL ⁇ 8 > to the column control circuit 3 .
- 12 9-cell column units CU 9 and 116 8-cell column units CU 8 may be aligned in the row direction.
- 4 9-cell column units CU 9 and 117 8-cell column units CU 8 may be aligned in the row direction.
- the arrangement area of an unnecessary column set or an extra area accompanied with the arrangement area may not be repeated.
- the column control circuit 3 corresponding to an optimal number of redundant cell columns can be configured in an appropriate chip area.
- the lack of column set CC may be supplemented with one of the column set CC of the 9-cell column unit CU 9 . Further, the lack of column set CC may be supplemented with one of the column set CC of the 8-cell column unit CU 8 . And the 9-cell column unit CU 9 may include a plurality of redundancy cell columns. The 8-cell column unit CU may include a plurality of redundancy cell columns, also.
- the column set CC 8 of the 9-cell column unit CU 9 is not limited to use only redundancy. So the column set CC 8 of the 9-cell column unit CU 9 can be used to adjust a total number of cell columns of the semiconductor memory device.
- control/arithmetic circuit CT/AR ⁇ i> is selected in accordance with a read column selection signal SEL ⁇ 0:7>, one selection column is selected.
- the selected control/arithmetic circuit CT/AR ⁇ i> outputs data stored in the data latch DL ⁇ i, j> belonging to the selected cell column to the outside at a time.
- the read column selection signal SEL ⁇ 0:7> may be given so as to sequentially increment “i” included in the control/arithmetic circuit CT/AR ⁇ i> in accordance with a clock signal and select the control/arithmetic circuit.
- the output of the data to the outside can be performed at a high speed.
- the cell column CC 0 is accessed in accordance with a column selection signal SEL ⁇ 0 > for all the 8-cell column units CU 8 and all the 9-cell column units CU 9 . Accordingly, for example, in the case of a read operation, the data of the cell column CC 0 corresponding to each 8-cell column unit CU 8 and each 9-cell column unit CU 9 can be prepared all at once by all the 8-cell column units CU 8 and all the 9-cell column units CU 9 , and accordingly, the data can be immediately read.
- the cell column set CC 1 is accessed in accordance with a column selection signal SEL ⁇ 1 > for all the 8-cell column units CU 8 and all the 9-cell column units CU 9 .
- These accesses are sequentially performed starting from the column set CC 1 of the 9-cell column unit CU 9 that is located on the leftmost side.
- similar operations are repeated, and, after the data of the column set CC 7 of the 8-cell column unit CU 8 that is located on the rightmost side in the column direction is output to the I/O, a column selection signal SEL ⁇ 8 > is transmitted from the control circuit 7 .
- the cell column set CC 8 is accessed in accordance with a column selection signal SEL ⁇ 8 > for all the 8-cell column units CU 8 and all the 9-cell column units CU 9 .
- These accesses are sequentially performed starting from the column set CC 8 of the 9-cell column unit CU 9 that is located on the leftmost side.
- the read operation is completed. Accordingly, from the viewpoint of a high-speed access, it is preferable that the column units CU 9 are continuously arranged.
- the sense amplifier set S/AS and the data latch set DLS extend in one row in the column direction.
- data of the sense amplifier set S/AS or data of the data latch set DLS is assigned in a plurality of rows in the column direction.
- the column control circuit 3 is configured by such cell column units.
- FIG. 5 is a diagram illustrating the configuration examples of a sense amplifier-data latch unit of a semiconductor memory device according to this embodiment and a column control circuit using the sense amplifier-data latch units.
- the column control circuit 3 according to this embodiment, as illustrated in FIG. 5 is configured by the 8-cell column units CU 8 (the first sense amplifier-data latch units) and 9-cell column units CU 9 (the second sense amplifier-data latch units).
- the assignment of data for the data latch set DLS ⁇ i> is different from that of the first embodiment.
- the 8-cell column unit CU 8 performs assignment in which matrix inversion is performed for data of the sense amplifiers SA ⁇ 0, 0> to SA ⁇ 0, 7> aligned in the column direction, and the resultant data is stored in the data latches ⁇ 0, 0>to ⁇ 7, 0>.
- data of the sense amplifiers SA ⁇ 1, 0> to SA ⁇ 1, 7> aligned in the column direction is stored in the data latches ⁇ 0, 1> to ⁇ 7, 1>.
- control/arithmetic circuit CT/AR ⁇ 1 > selects the sense amplifiers ⁇ 0, 1> to ⁇ 7, 1> in which the common control circuit CCT ⁇ 1 > is aligned in the row direction and stores the data stored in the sense amplifiers ⁇ 0, 1> to ⁇ 7, 1> in the data latches DL ⁇ 0, 1> to DL ⁇ 7, 1> aligned in the column direction.
- the data may be temporarily stored and used for a calculation by the control/arithmetic circuit CT/AR ⁇ 1 >.
- the 9-cell column unit CU 9 similarly to the first embodiment, one expanded column set formed from a sense amplifier set S/AS ⁇ 8 > and a data latch set DLS ⁇ 8 > is configured to be added to the 8-cell column unit CU 8 .
- a case will be considered in which a column set CC 0 of a certain 8-cell column unit CU 8 is defective.
- the control circuit 7 skips the defective column set CC 0 and transmits a signal used for selecting the column set CC 0 of the 8-cell column unit CU 8 , which is adjacent thereto, to the column control circuit 3 .
- the control/arithmetic circuit CT/AR ⁇ 0 > of the 8-cell column unit CU 8 which is adjacent thereto, is selected, and data stored in the data latches DL ⁇ 0, 0> to DL ⁇ 0, 7> is output to the I/O.
- the data may be temporarily stored and used for a calculation by the control/arithmetic circuit CT/AR ⁇ 0 >.
- the column set CC 0 is skipped as a defective set, there is a lack of one column set CC.
- the lack of the column set CC is supplemented with the column set CC 8 of the 9-cell column unit CU 9 .
- control circuit 7 may be configured to replace the column selection signal SEL ⁇ 0 > with a column selection signal SEL ⁇ 8 > of the 9-cell column unit CU 9 and transmit the column selection signal SEL ⁇ 8 > to the column control circuit 3 .
- the data latches DL ⁇ 8, 0> to DL ⁇ 8, 7> of the expanded column set can be arranged so as to be adjacent to the data latches DL ⁇ 7, 0> to DL ⁇ 7, 7> in the column direction.
- the width of the 9-cell column unit CU 9 and the width of the 8-cell column unit CU 8 in the column direction are different from each other.
- it is preferable that any one end of the 8-cell column unit CU 8 and the 9-cell column unit CU 9 in the column direction is uniformly arranged from the viewpoint of the layout.
- the expanded sense amplifier set S/AS ⁇ 8 > similarly to the first embodiment, is arranged in the area Aesa (first expanded area) that is adjacent to the area Asa′ corresponding to the area Asa (first area), in which the sense amplifier sets S/AS ⁇ 0 > to S/AS ⁇ 7 > of the 8-cell column unit CU 8 are arranged, in the row direction at the same position in the column direction.
- the area Asa in which the sense amplifier set S/AS ⁇ 0 > to S/AS ⁇ 7 > of the 8-cell column unit CU 8 are arranged and areas Asa′ and Adl′ corresponding to the area Adl (second area) in which the data latch sets DLS ⁇ 0 > to S/AS ⁇ 7 > are arranged are arranged in an external area Aex (second expanded area) that is located at a different position in the column direction.
- the external area Aex may be a portion that is adjacent to the data latches DL ⁇ 0, 7> to DL ⁇ 7, 7> in the row direction.
- an empty space that is present in the column control circuit may be used.
- an external data latch control circuit EDLCT used for controlling the expanded data latch set DSL ⁇ 8 > located in the external area Aex may be disposed.
- the data bus DB may be used, which is used for the data transmission between another sense amplifier ⁇ i, j> and the data latch DL ⁇ i, j>, to be common thereto.
- a temporary latch circuit TL is prepared on the data bus DB, and the data transmission is performed through the latch circuit between the sense amplifier set S/A ⁇ 8, j> and the data latch DL ⁇ 8, j>.
- a method of configuring the column control circuit 3 by using the 8-cell column units CU 8 and the 9-cell column units CU 9 , which are illustrated in FIGS. 5 and 6 , is similar to that of the first embodiment, and thus, the description thereof will not be presented here.
- the number of sense amplifiers S/A and the number of data latches DL that are included in the 9-cell column unit CU 9 may be configured to be same with the expanded data latch set DSL ⁇ 8 > located in the external area Aex being taken into account.
- the 8-cell column unit CU 8 is configured as the first sense amplifier-data latch unit
- the number of cell columns that can be handled by the first sense amplifier-data latch unit is arbitrary.
- both the second sense amplifier-data latch units according to the above-described embodiments have the number of cell columns, which can be handled, acquired by adding one to the number of cell columns of the first sense amplifier-data latch unit, there may be a difference of, for example, two or more, between the number of cell columns of the second sense amplifier-data latch unit, which can be handled, and the number of cell columns of the first sense amplifier-data latch unit, which can be handled.
- the column control circuit is configured by a combination of two types of sense amplifier-data latch sets, the column control circuit may be configured by a combination of three or more types of sense amplifier-data latch units.
- the second sense amplifier-data latch units according to the above-described embodiments have a layout that is acquired by adding another column set to a layout that is equal to that of the first sense amplifier-data latch unit, the first sense amplifier-data latch unit may be configured to have a layout that is completely different from that of the second sense amplifier-data latch unit.
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US20150078091A1 (en) * | 2013-09-13 | 2015-03-19 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
US20220244889A1 (en) * | 2021-02-02 | 2022-08-04 | SK Hynix Inc. | Memory device |
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