US8850294B1 - Decoding apparatus for digital communications and method for using the same - Google Patents
Decoding apparatus for digital communications and method for using the same Download PDFInfo
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- US8850294B1 US8850294B1 US11/733,003 US73300307A US8850294B1 US 8850294 B1 US8850294 B1 US 8850294B1 US 73300307 A US73300307 A US 73300307A US 8850294 B1 US8850294 B1 US 8850294B1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/3738—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35 with judging correct decoding
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2933—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using a block and a convolutional code
- H03M13/2936—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using a block and a convolutional code comprising an outer Reed-Solomon code and an inner convolutional code
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2957—Turbo codes and decoding
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/3776—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35 using a re-encoding step during the decoding process
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
- H03M13/618—Shortening and extension of codes
Definitions
- the present disclosure relates to a decoding apparatus, and more particularly, to a decoding apparatus for digital communications and a method for using the same.
- Concatenated codes are widely used for error correction of digital communication systems.
- the concatenated codes are based on outer Reed-Solomon codes and inner convolutional codes.
- FIG. 1 is a block diagram of a conventional digital communication system 100 which uses concatenated Reed-Solomon codes and convolutional codes.
- a transmitting terminal of the conventional digital communication system 100 processes an input bit stream BS_IN, using a Reed-Solomon encoder 110 , an interleaver 120 , a convolutional encoder 130 , and a modulator 140 .
- the processed bit stream is transmitted through a channel 150 .
- a receiving terminal of the conventional digital communication system 100 receives the transmitted bit stream and generates a decoding bit stream BSDEC using a demodulator 160 and a concatenated decoder 200 .
- FIG. 2 is a detailed block diagram of the concatenated decoder 200 illustrated in FIG. 1 .
- the concatenated decoder 200 included in the conventional digital communication system 100 decodes a received bit stream using a Soft-Input Viterbi decoder 210 , a deinterleaver 220 , and a hard-decision Reed-Solomon decoder 230 , and generates a decoding bit stream BS_DEC.
- concatenated decoder 200 included in the conventional digital communication system 100 cannot sufficiently use the error correction performance of concatenated Reed-Solomon codes and concatenated convolutional codes (hereinafter, referred to as concatenated RSC codes).
- Exemplary embodiments of the present invention provide a decoding apparatus that estimates a reliability value by detecting uncorrected packet errors.
- Exemplary embodiments of the present invention also provide a decoding method that estimates a reliability value by detecting uncorrected packet errors.
- a decoding apparatus includes a hard-decision unit and a reliability determination unit.
- the hard-decision unit performs hard-decision on a soft-input of a code.
- the reliability determination unit generates a reliability estimation value of the hard-decision result, according to whether a packet error exists in the hard-decision result.
- the hard-decision unit performs the hard-decision in response to the reliability estimation value.
- the hard-decision unit may include a hard-decision Reed-Solomon decoder for performing the hard-decision and outputting the hard-decision result to the reliability determination unit.
- the reliability determination unit may include a packet error detector that detects the packet error, in response to the hard-decision result of the hard-decision Reed-Solomon decoder.
- the reliability determination unit may further include a reliability estimation value generator that generates a reliability estimation value of the hard-decision result, according to whether the packet error is detected.
- the reliability estimation value generator may generate a reliability estimation value which changes in response to the hard-decision result when no packet error is detected.
- the reliability estimation value generator may generate a constant reliability estimation value when the packet error is detected.
- the reliability estimation value generator may also include a multiplexer that selects one of the hard-decision result values and a predetermined constant value in response to whether the packet error is detected.
- the hard-decision unit may also include a soft-input/hard-output decoder that generates a hard-output in response to the soft-input of the code and the reliability estimation value.
- the hard-decision Reed-Solomon decoder performs hard-decision on the hard-output generated by the soft-input/hard-output decoder.
- the soft-input/hard-output decoder may be a soft-input/hard-output Viterbi decoder or a soft-input/hard-output convolutional decoder.
- a decoding method includes a hard-decision operation and a reliability determination operation.
- the hard-decision operation performs hard-decision on a soft-input of a code.
- the reliability determination operation generates a reliability estimation value of the hard-decision result according to whether a packet error exists in the hard-decision result.
- the hard-decision operation performs the hard-decision in response to the reliability estimation value.
- the hard-decision operation may include a hard-decision Reed-Solomon decoding operation.
- the hard-decision Reed-Solomon decoding operation performs the hard-decision and outputs the hard-decision result to the reliability determination operation.
- the reliability determination operation may include a packet error detection operation.
- the packet error detection operation detects the packet error in response to the hard-decision result of the hard-decision Reed-Solomon decoding operation.
- the reliability determination operation may also include a reliability estimation value generating operation.
- the reliability estimation value generating operation generates a reliability estimation value of the hard-decision result according to whether the packet error is detected.
- FIG. 1 is a block diagram of a conventional digital communication system which uses concatenated Reed-Solomon codes and convolutional codes;
- FIG. 2 is a block diagram of the concatenated decoder illustrated in FIG. 1 ;
- FIG. 3 is a block diagram of a turbo decoder
- FIG. 4 is a block diagram of a concatenated Reed-Solomon and Convolutional (RSC) decoder
- FIG. 5 is a block diagram of a decoding apparatus according to an exemplary embodiment of the present invention.
- FIG. 6 illustrates a structure of a Reed-Solomon code
- FIG. 7 is a flowchart illustrating the operation of the packet error detector illustrated in FIG. 5 ;
- FIG. 8 is a block diagram of a decoding system according to an exemplary embodiment of the present invention.
- FIG. 9 is a block diagram of the decoder illustrated in FIG. 8 ;
- FIG. 10 is a graph showing simulation results of the operation of the decoding apparatus according to an exemplary embodiment of the present invention.
- a turbo decoder 300 and a concatenated Reed-Solomon and Convolutional (RSC) decoder 400 are described below.
- FIG. 3 is a block diagram of the turbo decoder 300 .
- the turbo decoder 300 includes a soft-input/soft-output (hereinafter, referred to as “SISO”) convolutional decoder 310 , a deinterleaver 320 , a SISO Reed-Solomon decoder 330 , and an interleaver 340
- SISO soft-input/soft-output
- the turbo decoder 300 includes two SISO decoders: the SISO convolutional decoder 310 and the SISO Reed-Solomon decoder 330 .
- One of the two SISO decoders 310 and 330 decodes outer codes and the other decodes inner codes.
- the inclusion of the SISO Reed-Solomon decoder 330 increases complexity of the turbo decoder 300 .
- FIG. 4 is a block diagram of the concatenated RSC decoder 400 .
- the concatenated RSC decoder 400 includes a Viterbi decoder 410 , a deinterleaver 420 , a Reed-Solomon decoder 430 , an interleaver 440 , and a convolutional encoder 450 .
- a demodulator 160 is illustrated in FIG. 4 .
- Data received from the demodulator 160 is transferred to the Reed-Solomon decoder 430 via the Viterbi decoder 410 and the deinterleaver 420 .
- the Reed-Solomon decoder 430 performs hard-decision.
- the convolutional encoder 450 encodes the hard-decision result and feeds back the encoded result to the Viterbi decoder 410 .
- the concatenated RSC decoder 400 illustrated in FIG. 4 may allow for the propagation of error.
- FIG. 5 is a block diagram of a decoding apparatus 500 according to an exemplary embodiment of the present invention.
- the decoding apparatus 500 includes a hard-decision unit 540 and a reliability determination unit 550 .
- the hard-decision unit 540 performs hard-decision on a soft-input of an input code IC and outputs a hard-decision result CD.
- the input code may be a code received from a demodulator.
- the reliability determination unit 550 generates a reliability estimation value OC of the hard-decision result CD, according to whether a packet error PE exists in the hard-decision result CD.
- the hard-decision unit 540 performs the hard-decision in response to the reliability estimation value OC of the hard-decision result CD.
- the hard-decision unit 540 may include a hard-decision Reed-Solomon decoder 530 .
- the hard-decision Reed-Solomon decoder 530 performs the hard-decision and outputs the hard-decision result CD to the reliability determination unit 550 .
- the reliability determination unit 550 can include a packet error detector 560 .
- the packet error detector 560 detects the packet error PE in response to the hard-decision result CD generated by the hard-decision Reed-Solomon decoder 530 . The operation of the packet error detector 560 is discussed below.
- the reliability determination unit 550 may also include a reliability estimation value generator 570 .
- the reliability estimation value generator 570 generates a reliability estimation value OC of the hard-decision result CD according to whether the packet error PE is detected. When no packet error PE is detected, the reliability estimation value generator 570 can generate a reliability estimation value OC which changes in response to the hard-decision result CD. When the packet error PE is detected, the reliability estimation value generator 570 can generate a reliability estimation value OC having a constant value.
- the reliability estimation generator 570 can generate a reliability estimation value OC having a value of + ⁇ when the hard-decision result CD is 1 and can generate a reliability estimation value OC having a value of ⁇ when the hard-decision result CD is 0.
- the reliability estimation value generator 570 can generate a reliability estimation value OC having a value of 0.
- the reliability estimation value generator 570 may also include a multiplexer 572 .
- the multiplexer 572 selects either the hard-decision result CD or a predetermined constant value in response to whether the packet error PE is detected.
- the reliability estimation value generator 570 may also include an adder 574 and an amplifier 576 to provide the reliable estimation value as described above.
- the hard-decision unit 540 may also include a soft-input/hard-output decoder 510 .
- the soft-input/hard-output decoder 510 generates a hard-output in response to the soft-input of the input code IC and the reliability estimation value OC.
- the hard-decision Reed-Solomon decoder 530 performs hard-decision on the hard-output generated by the soft-input/hard-output decoder 510 .
- the soft-input/hard-output decoder 510 may be a soft-input/hard-output Viterbi decoder or a soft-input/hard-output convolutional decoder.
- the decoding apparatus 500 may also include a deinterleaver 520 and an interleaver 590 .
- the deinterleaver 520 deinterleaves the hard-output of the soft-input/hard-output decoder 510 and outputs the deinterleaved result to the hard-decision Reed-Solomon decoder 530 .
- the interleaver 590 interleaves the reliability estimation value OC of the hard-decision result CD and outputs the interleaved result IU to the soft-input/hard-output decoder 510 .
- the soft-input/hard-output Viterbi decoder 510 can use the output value of the interleaver 590 to calculate a branch matrix. For example, the soft-input/hard-output Viterbi decoder 510 can calculate the branch matrix using Equation 2.
- BM′ BM+ Uk *INT( CD ), (2) where, BM denotes a conventional branch matrix, BM′ denotes a branch matrix according to the present invention, Uk denotes a bit corresponding a branch of the branch matrix, among the bits of the hard-decision result value CD, and INT(CD) denotes the output value of the interleaver 590 .
- the input code IC may be a concatenated code.
- FIG. 6 illustrates the structure of a Reed-Solomon code 600 .
- the entire length of the Reed-Solomon code 600 is N bytes (for example, 255 bytes).
- the upper R bytes (RB; for example, 255 bytes) of the Reed-Solomon code 600 can be all zero.
- the Reed-Solomon code 600 includes a long Reed-Solomon code type and a short Reed-Solomon code type.
- the upper R bytes of a short Reed-Solomon code may all be zero, and the upper R bytes of a long Reed-Solomon code may be non-zero.
- the Reed-Solomon code 600 can include sync bytes SB for synchronization.
- actual data is includes in a data area UB.
- the data area UB and the sync bytes SB may be K-R bytes (for example, 188 bytes).
- the Reed-Solomon code 600 can include parity bits PB.
- t denotes the number of bytes that can be corrected by the parity bits PB.
- the number of bytes that the Reed-Solomon code 600 can correct using the parity bits PB is limited. However, the Reed-Solomon code 600 can detect uncorrected error bytes.
- FIG. 7 is a flowchart illustrating the operation of the packet error detector 560 illustrated in FIG. 5 .
- the packet error detector 560 detects a packet error PE using a Reed-Solomon code (CD) 600 outputted by the hard-decision Reed-Solomon decoder 530 . Referring to FIG. 7 , the packet error detector 560 obtains an error location polynomial calculated by the Reed-Solomon code 600 (Step S 710 ). If the degree of the obtained error location polynomial is greater than t (No, Step S 720 ), it is determined that a packet error exists. The number of roots of the error location polynomial is calculated (Step S 730 ).
- CD Reed-Solomon code
- Step S 740 If the number of roots of the error location polynomial is different from the degree of the error location polynomial (No, Step S 740 ), it is determined that a packet error exists.
- the Reed-Solomon codeword received from the hard-decision Reed-Solomon decoder is decoded (Step S 750 ). If a byte which is not zero is included in the upper R bytes RB of the Reed-Solomon code 600 (No, Step S 760 , it is determined that a packet error exists. If the sync byte SB of the Reed-Solomon code 600 does not have a specific value, for example, 0x47 (No, Step S 770 ), it is determined that a packet error exists.
- Step S 720 if the degree of the obtained error location polynomial is less than or equal to t (Yes, Step S 720 ), the number of roots of the error location polynomial is the same as the degree of the error location polynomial (Yes, Step S 740 ), a byte which is zero is included in the upper R bytes RB of the Reed-Solomon code 600 (Yes, S 760 ), and the sync byte SB of the Reed-Solomon code 600 has the specific value (Yes, S 770 ) then it is determined that no packet error exists.
- a probability of detecting a packet error using the Reed-Solomon code 600 is represented by Equation 3.
- FIG. 8 is a block diagram of a decoding system 800 according to an exemplary embodiment of the present invention.
- FIG. 9 is a block diagram of the decoder 900 — i illustrated in FIG. 8 .
- the decoding system 800 includes first through N-th (N is a natural number) decoders 900 _ 1 , 900 _ 2 , 900 _ 3 , . . . , 900 n , and first through (N ⁇ 1)-th delay units 810 _ 1 , 800 _ 2 , 810 _ 3 , . . . , 800 _N ⁇ 1 (not shown).
- the first through N-th decoders 900 _ 1 through 900 — n and the first through (N ⁇ 1)-th delay units 810 _ 1 through 810 _(N ⁇ 1) are respectively connected in series with each other.
- the decoder 900 — i has a structure that is similar to the structure of the decoder 500 illustrated in FIG. 5 .
- the decoder 900 — i includes a soft-input/hard-output decoder 910 , a deinterleaver 920 , a hard-decision Reed-Solomon decoder 930 , a packet error detector 960 , a multiplexer 972 , an adder 974 , an amplifier 976 , and an interleaver 990 , each corresponding to an item of FIG. 5 above. Therefore, many details concerning the decoder 900 — i and the constituent items may be understood by the discussion above pertaining to the decoder of FIG.
- the output of a reliability determination unit (not shown) is not fed back to a soft-input/hard-output decoder (not shown).
- the output of the reliability determination unit of the decoder 900 — i is transferred to a hard-decision unit of a decoder 900 — i+ 1.
- the decoder 900 — i+ 1 performs hard-decision on a delayed soft-input in response to a reliability estimation value of a hard-decision result outputted from the decoder 900 — i.
- a decoding method includes hard-decision operations and reliability determination operation.
- hard-decision operation hard-decision is performed on a soft-input of a code.
- reliability determination operation a reliability estimation value of the hard-decision result is generated according to whether a packet error exists in the hard-decision result.
- the hard-decision operation the hard-decision is performed in response to the reliability estimation value.
- the hard-decision operation may include a hard-decision Reed-Solomon decoding operation.
- the hard-decision Reed-Solomon decoding operation the hard-decision is performed and the hard-decision result is outputted to the reliability determination operation.
- the reliability determination operation can include a packet error detection operation. In the packet error detection operation, the packet error is detected in response to the hard-decision result obtained by the hard-decision Reed-Solomon decoding operation.
- the reliability determination operation may also include a reliability estimation value generating operation. In the reliability estimation value generating operation, a reliability estimation value of the hard-decision result is generated according to whether the packet error is detected.
- the decoding method according to an exemplary embodiment of the present invention has a similar technical concept as the decoding apparatus 500 described above with respect to FIG. 5 .
- the structure of the decoding apparatus 900 — i corresponds to the structure of the decoding apparatus 500 . Therefore, the decoding method according to an exemplary embodiment of the present invention can be understood by those skilled in the art from the above descriptions.
- FIG. 10 is a graph showing simulation results of the operation of the decoding apparatus 500 according to an exemplary embodiment of present invention.
- FER frame error rate
- a frame error rate may be lowered when decoding and thus enhance gain characteristic.
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Abstract
Description
OC=α(1−2*CD), if no packet-error detected
OC=0, if packet-error detected (1)
BM′=BM+Uk*INT(CD), (2)
where, BM denotes a conventional branch matrix, BM′ denotes a branch matrix according to the present invention, Uk denotes a bit corresponding a branch of the branch matrix, among the bits of the hard-decision result value CD, and INT(CD) denotes the output value of the interleaver 590.
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US20150249469A1 (en) * | 2008-12-26 | 2015-09-03 | Panasonic Intellectual Property Corporation Of America | Transmission apparatus and method, and reception apparatus and method |
Citations (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6029264A (en) * | 1997-04-28 | 2000-02-22 | The Trustees Of Princeton University | System and method for error correcting a received data stream in a concatenated system |
US6212659B1 (en) * | 1997-05-30 | 2001-04-03 | Qualcomm Inc. | Method and apparatus for providing error protection for over the air file transfer |
US6351832B1 (en) * | 1999-05-28 | 2002-02-26 | Lucent Technologies Inc. | Turbo code symbol interleaver |
US20020029362A1 (en) * | 1998-12-30 | 2002-03-07 | Karen J. Stephen | Method and apparatus for encoding and decoding a turbo code in an integrated modem system |
US6356595B1 (en) * | 1997-10-14 | 2002-03-12 | Sony Corporation | Method and apparatus for decoding continuously coded convolutionally encoded messages |
US6606724B1 (en) * | 2000-01-28 | 2003-08-12 | Conexant Systems, Inc. | Method and apparatus for decoding of a serially concatenated block and convolutional code |
US6732327B1 (en) | 2000-05-05 | 2004-05-04 | Nokia Networks Oy | Scaled-feedback turbo decoder |
JP2004254348A (en) | 2004-05-28 | 2004-09-09 | Fujitsu Ltd | Turbo decoding apparatus |
US6789593B1 (en) | 2002-10-29 | 2004-09-14 | John Hui | Hole puncher and reinforcer |
US6810502B2 (en) * | 2000-01-28 | 2004-10-26 | Conexant Systems, Inc. | Iteractive decoder employing multiple external code error checks to lower the error floor |
US6963618B2 (en) * | 2000-04-18 | 2005-11-08 | Zenith Electronics Corporation | Enhanced slice prediction feedback |
US7035342B2 (en) * | 2000-09-12 | 2006-04-25 | Broadcom Corporation | Parallel concatenated code with soft-in soft-out interactive turbo decoder |
US7093179B2 (en) * | 2001-03-22 | 2006-08-15 | University Of Florida | Method and coding means for error-correction utilizing concatenated parity and turbo codes |
US7415079B2 (en) * | 2000-09-12 | 2008-08-19 | Broadcom Corporation | Decoder design adaptable to decode coded signals using min* or max* processing |
US7421044B2 (en) * | 2000-09-05 | 2008-09-02 | Broadcom Corporation | Quasi error free (QEF) communication using turbo codes |
US7519898B2 (en) * | 2004-03-25 | 2009-04-14 | Krishna Rama Narayanan | Iterative decoding of linear block codes by adapting the parity check matrix |
US7551236B2 (en) * | 2000-09-22 | 2009-06-23 | Lg Electronics Inc. | Communication system in digital television |
US7577893B2 (en) * | 2006-06-07 | 2009-08-18 | Agere Systems Inc. | Forward error correction decoding method and apparatus for satellite digital audio radio broadcasting |
US7587657B2 (en) * | 2005-04-29 | 2009-09-08 | Agere Systems Inc. | Method and apparatus for iterative error-erasure decoding |
US7796712B2 (en) * | 2005-12-23 | 2010-09-14 | Lg Electronics, Inc. | DTV receiver and method of processing broadcast signal in DTV receiver |
US7814398B2 (en) * | 2006-06-09 | 2010-10-12 | Seagate Technology Llc | Communication channel with Reed-Solomon encoding and single parity check |
-
2007
- 2007-04-09 US US11/733,003 patent/US8850294B1/en not_active Expired - Fee Related
Patent Citations (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6029264A (en) * | 1997-04-28 | 2000-02-22 | The Trustees Of Princeton University | System and method for error correcting a received data stream in a concatenated system |
US6212659B1 (en) * | 1997-05-30 | 2001-04-03 | Qualcomm Inc. | Method and apparatus for providing error protection for over the air file transfer |
US6553538B2 (en) * | 1997-05-30 | 2003-04-22 | Qualcomm Incorporated | Method and apparatus for providing error protection for over the air file transfer |
US6356595B1 (en) * | 1997-10-14 | 2002-03-12 | Sony Corporation | Method and apparatus for decoding continuously coded convolutionally encoded messages |
US20020029362A1 (en) * | 1998-12-30 | 2002-03-07 | Karen J. Stephen | Method and apparatus for encoding and decoding a turbo code in an integrated modem system |
US6484283B2 (en) * | 1998-12-30 | 2002-11-19 | International Business Machines Corporation | Method and apparatus for encoding and decoding a turbo code in an integrated modem system |
US6351832B1 (en) * | 1999-05-28 | 2002-02-26 | Lucent Technologies Inc. | Turbo code symbol interleaver |
US7310768B2 (en) * | 2000-01-28 | 2007-12-18 | Conexant Systems, Inc. | Iterative decoder employing multiple external code error checks to lower the error floor |
US6606724B1 (en) * | 2000-01-28 | 2003-08-12 | Conexant Systems, Inc. | Method and apparatus for decoding of a serially concatenated block and convolutional code |
US7568147B2 (en) * | 2000-01-28 | 2009-07-28 | Nxp B.V. | Iterative decoder employing multiple external code error checks to lower the error floor |
US6810502B2 (en) * | 2000-01-28 | 2004-10-26 | Conexant Systems, Inc. | Iteractive decoder employing multiple external code error checks to lower the error floor |
US6963618B2 (en) * | 2000-04-18 | 2005-11-08 | Zenith Electronics Corporation | Enhanced slice prediction feedback |
US6732327B1 (en) | 2000-05-05 | 2004-05-04 | Nokia Networks Oy | Scaled-feedback turbo decoder |
US7421044B2 (en) * | 2000-09-05 | 2008-09-02 | Broadcom Corporation | Quasi error free (QEF) communication using turbo codes |
US7460608B2 (en) * | 2000-09-12 | 2008-12-02 | Broadcom Corporation | Parallel concatenated code with soft-in soft-out interactive turbo decoder |
US7715503B2 (en) * | 2000-09-12 | 2010-05-11 | Broadcom Corporation | Parallel concatenated code with soft-in soft-out interactive turbo decoder |
US7409006B2 (en) * | 2000-09-12 | 2008-08-05 | Broadcom Corporation | Parallel concatenated code with soft-in-soft-out interactive turbo decoder |
US7415079B2 (en) * | 2000-09-12 | 2008-08-19 | Broadcom Corporation | Decoder design adaptable to decode coded signals using min* or max* processing |
US7035342B2 (en) * | 2000-09-12 | 2006-04-25 | Broadcom Corporation | Parallel concatenated code with soft-in soft-out interactive turbo decoder |
US7440521B2 (en) * | 2000-09-12 | 2008-10-21 | Broadcom Corporation | Method of normalization of forward metric (alpha) and reverse metric (beta) in a map decoder |
US7499503B2 (en) * | 2000-09-12 | 2009-03-03 | Broadcom Corporation | Parallel concatenated code with soft-in soft-out interactive turbo decoder |
US7158589B2 (en) * | 2000-09-12 | 2007-01-02 | Broadcom Corporation | Method and apparatus for parallel decoding of turbo encoded data |
US7551236B2 (en) * | 2000-09-22 | 2009-06-23 | Lg Electronics Inc. | Communication system in digital television |
US7093179B2 (en) * | 2001-03-22 | 2006-08-15 | University Of Florida | Method and coding means for error-correction utilizing concatenated parity and turbo codes |
US6789593B1 (en) | 2002-10-29 | 2004-09-14 | John Hui | Hole puncher and reinforcer |
US7519898B2 (en) * | 2004-03-25 | 2009-04-14 | Krishna Rama Narayanan | Iterative decoding of linear block codes by adapting the parity check matrix |
JP2004254348A (en) | 2004-05-28 | 2004-09-09 | Fujitsu Ltd | Turbo decoding apparatus |
US7587657B2 (en) * | 2005-04-29 | 2009-09-08 | Agere Systems Inc. | Method and apparatus for iterative error-erasure decoding |
US7796712B2 (en) * | 2005-12-23 | 2010-09-14 | Lg Electronics, Inc. | DTV receiver and method of processing broadcast signal in DTV receiver |
US7577893B2 (en) * | 2006-06-07 | 2009-08-18 | Agere Systems Inc. | Forward error correction decoding method and apparatus for satellite digital audio radio broadcasting |
US7814398B2 (en) * | 2006-06-09 | 2010-10-12 | Seagate Technology Llc | Communication channel with Reed-Solomon encoding and single parity check |
Non-Patent Citations (1)
Title |
---|
English Abstract Publication No. 2004-254348. |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20150249469A1 (en) * | 2008-12-26 | 2015-09-03 | Panasonic Intellectual Property Corporation Of America | Transmission apparatus and method, and reception apparatus and method |
US10693502B2 (en) | 2008-12-26 | 2020-06-23 | Panasonic Intellectual Property Corporation Of America | Transmission apparatus and method, and reception apparatus and method |
US11139837B2 (en) | 2008-12-26 | 2021-10-05 | Panasonic Intellectual Property Corporation Of America | Transmission apparatus and method, and reception apparatus and method |
US11722156B2 (en) | 2008-12-26 | 2023-08-08 | Panasonic Intellectual Property Corporation Of America | Transmission apparatus and method, and reception apparatus and method |
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