US8847325B2 - Fin field-effect transistor structure - Google Patents
Fin field-effect transistor structure Download PDFInfo
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- US8847325B2 US8847325B2 US13/689,720 US201213689720A US8847325B2 US 8847325 B2 US8847325 B2 US 8847325B2 US 201213689720 A US201213689720 A US 201213689720A US 8847325 B2 US8847325 B2 US 8847325B2
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- 230000005669 field effect Effects 0.000 title claims abstract description 35
- 229910052751 metal Inorganic materials 0.000 claims abstract description 68
- 239000002184 metal Substances 0.000 claims abstract description 68
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 125000006850 spacer group Chemical group 0.000 claims description 16
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 15
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical group [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052802 copper Inorganic materials 0.000 claims description 10
- 239000010949 copper Substances 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 239000012212 insulator Substances 0.000 claims description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 239000010937 tungsten Substances 0.000 claims description 5
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical group [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 2
- 229910021332 silicide Inorganic materials 0.000 claims 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims 1
- 239000010410 layer Substances 0.000 description 107
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 35
- 229920005591 polysilicon Polymers 0.000 description 35
- 238000000034 method Methods 0.000 description 33
- 230000008569 process Effects 0.000 description 33
- 238000004519 manufacturing process Methods 0.000 description 8
- 238000005530 etching Methods 0.000 description 5
- 238000002513 implantation Methods 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- PCLURTMBFDTLSK-UHFFFAOYSA-N nickel platinum Chemical compound [Ni].[Pt] PCLURTMBFDTLSK-UHFFFAOYSA-N 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Definitions
- the present invention relates to a fin field-effect transistor structure, and more particularly to a fin field-effect transistor structure applied to a semiconductor component.
- the present invention also relates to a manufacturing process of such a fin field-effect transistor structure.
- FIG. 1 is a schematic view illustrating a FinFET structure according to the prior art.
- the FinFET structure of FIG. 1 comprises a substrate 10 , a source 11 , a drain 12 , a gate insulator layer 13 and a gate conductor layer 14 .
- the FinFET structure has better current driving capability than the typical FET structure.
- downscaling and optimizing the FinFET structure is a challenge.
- the object of the present invention is to provide a fin field-effect transistor structure and a manufacturing process of the fin field-effect transistor structure in order to overcome the drawbacks encountered from the prior art.
- the present invention provides a manufacturing process of a fin field-effect transistor structure. Firstly, a substrate is provided. Then, a fin channel is formed on the substrate. Then, a polysilicon pseudo gate layer is formed on a surface of the fin channel. By defining the polysilicon pseudo gate layer, a polysilicon pseudo gate structure is formed. Then, by using the polysilicon pseudo gate structure as a mask, a first implantation process is performed to form a source/drain region in the fin channel. Then, a contact etch stop layer and a first dielectric layer are successively formed over the fin channel having the source/drain region, the polysilicon pseudo gate structure and the substrate.
- a first planarization process is performed on the substrate having the first dielectric layer and the contact etch stop layer until the polysilicon pseudo gate structure is exposed. Then, the polysilicon pseudo gate structure is removed to form a receiving space. Then, a high-k dielectric layer and a metal gate layer are successively formed on the substrate having the receiving space. Afterwards, a second planarization process is performed on the substrate having the metal gate layer until the first dielectric layer is exposed, so that a high-k metal gate is produced.
- the substrate is a silicon-on-insulator wafer including a handle wafer, a buried oxide layer and a silicon layer.
- the fin channel is formed by performing a photolithography and etching process on the silicon layer.
- the polysilicon pseudo gate structure layer includes an inter-layer dielectric layer, a polysilicon layer and a hard mask layer. A photolithography and etching process is performed to define the polysilicon pseudo gate structure layer, thereby forming the polysilicon pseudo gate structure.
- the polysilicon pseudo gate structure and the fin channel are perpendicular to each other.
- the first planarization process is performed until the polysilicon layer of the polysilicon pseudo gate structure is exposed.
- the step of forming the source/drain region in the fin channel includes sub-steps of performing a lightly doped drain implantation process on the fin channel by using the polysilicon pseudo gate structure as a mask, thereby forming a lightly doped drain region in the fin channel, forming a spacer structure on a sidewall of the polysilicon pseudo gate structure, and performing a source/drain implantation process on the fin channel that is uncovered by the polysilicon pseudo gate structure and the spacer structure, thereby forming the source/drain region in the fin channel.
- the manufacturing process further includes steps of performing a self-aligned salicidation process on the source/drain region that is uncovered by the polysilicon pseudo gate structure and the spacer structure, thereby forming a salicide layer on a surface of the source/drain region, and performing a sliming process on the spacer structure to reduce the thickness of the spacer structure or completely remove the spacer structure.
- the manufacturing process further includes steps of removing the first dielectric layer and the contact etch stop, which are arranged at both sides of the high-dielectric-constant metal gate, thereby forming at least two slot contact holes, and filling a metal layer in the slot contact holes to form plural slot contact structures.
- the metal layer is made of tungsten.
- the manufacturing process further includes steps of forming a metal gate cap layer and a dielectric layer on the substrate having the plural slot contact structures, forming plural contact holes in the metal gate cap layer and the dielectric layer over the high-k metal gate and the source/drain region, forming a barrier layer and a copper layer formed on the substrate having the plural contact holes, and performing a third planarization process to remove the excess copper layer to form copper contact structures.
- the present invention provides a fin field-effect transistor structure.
- the fin field-effect transistor structure includes a substrate, a fin channel and a high-k metal gate.
- the fin channel is formed on the substrate.
- a source/drain region is formed in both terminals of the fin channel.
- the high-k metal gate is formed on the substrate and the fin channel.
- the high-k metal gate includes a high-k dielectric layer and a metal gate layer. The high-k dielectric layer is arranged between the metal gate layer and the fin channel.
- the substrate is a silicon-on-insulator wafer including a handle wafer, a buried oxide layer and a silicon layer.
- the high-k metal gate and the fin channel are perpendicular to each other.
- the source/drain region further includes a lightly doped drain region.
- a spacer structure is formed on a sidewall of the high-k metal gate.
- the fin field-effect transistor structure further includes a salicide layer, which is formed on a surface of the source/drain region.
- the fin field-effect transistor structure further includes plural slot contact structures, which are arranged at both sides of the high-dielectric-constant metal gate.
- the slot contact structures are made of tungsten.
- the fin field-effect transistor structure further includes plural copper contact structures, which are arranged over the high-dielectric-constant metal gate and the source/drain region and connected with the high-dielectric-constant metal gate and the source/drain region.
- FIG. 1 is a schematic view illustrating a FinFET structure according to the prior art
- FIGS. 2A , 2 B, 2 C, 2 D, 2 E, 2 F, 2 G, 2 H, 2 I, 2 I' and 2 J are schematic views illustrating a FinFET structure according to an embodiment of the present invention
- FIGS. 3A , 3 B, 3 C, 3 D, 3 E, 3 F and 3 G are schematic views illustrating a process of forming metal lines and dielectric layers after the FinFET structure with the high-dielectric-constant metal gate as shown in FIG. 2J is produced;
- FIGS. 4A and 4B are schematic views illustrating a process of forming a salicide layer according to another embodiment of the present invention.
- FIGS. 2A , 2 B, 2 C, 2 D, 2 E, 2 F, 2 G, 2 H, 2 I and 2 J are schematic views illustrating a FinFET structure according to an embodiment of the present invention.
- a substrate 2 is provided.
- An example of the substrate 2 is a silicon-on-insulator (SOI) wafer with a three-layered configuration.
- the bottom layer 23 is a thicker handle wafer
- the intermediate layer is a thinner silicon dioxide insulator layer 22 such as a buried oxide (BOX) layer
- the top layer 21 is a thinner silicon layer.
- SOI silicon-on-insulator
- a photolithography and etching process is performed on the silicon layer 21 , thereby forming a fin channel 210 as shown in FIG. 2B .
- an inter-layer dielectric layer 211 and a polysilicon layer 212 are successively formed on the substrate 2 having the fin channel 210 .
- a planarization process e.g. a chemical mechanical planarization
- a hard mask layer 213 is formed on a surface of the polysilicon layer 212 .
- the resulting structure as shown in FIG. 2B is produced. Meanwhile, a polysilicon pseudo gate layer 299 comprising the inter-layer dielectric layer 211 , the polysilicon layer 212 and the hard mask layer 213 is formed.
- the polysilicon pseudo gate layer 299 is defined by a photolithography and etching process, thereby forming a polysilicon pseudo gate structure 298 .
- the polysilicon pseudo gate electrode 298 and the fin channel 210 are perpendicular to each other.
- LDD lightly doped drain
- a spacer structure 297 is formed on a sidewall of the polysilicon pseudo gate structure 298 . Then, as shown in FIG. 2E , a spacer structure 297 is formed on a sidewall of the polysilicon pseudo gate structure 298 . Then, the fin channel 210 uncovered by the polysilicon pseudo gate structure 298 and the spacer structure 297 is subject to a source/drain implantation process, so that a source/drain region 296 is formed in the fin channel 210 .
- the source/drain region 296 uncovered by the polysilicon pseudo gate structure 298 and the spacer structure 297 is subject to a self-aligned salicidation process, thereby forming a salicide layer 295 on the surface of the source/drain region 296 .
- a sliming process may be optionally performed on the spacer structure 297 , thereby reducing the thickness of the spacer structure 297 or completely removing the spacer structure 297 .
- the spacer structure 297 is not removed. In this embodiment, the following steps will be illustrated by referring to the case where the spacer structure 297 is not removed.
- a contact etch stop layer 294 and a first dielectric layer 293 are successively formed over the fin channel 210 having the source/drain region 296 , the polysilicon pseudo gate structure 298 and the substrate 2 .
- the substrate 2 having the first dielectric layer 293 and the contact etch stop layer 294 is subject to a planarization process (e.g. a chemical mechanical planarization) until the polysilicon layer 212 of the polysilicon pseudo gate structure 298 is exposed.
- a planarization process e.g. a chemical mechanical planarization
- the metal gate layer 290 is a multi-layered structure including a work function adjusting layer 290 a , a metal layer 290 b and the like. (as depicted in FIG. 2 I'). However, for convenience purpose, the metal gate layer 290 may be presented as a single layer in structure, as depicted in FIG. 2I , thereinafter.
- the substrate 2 with the metal gate layer 290 and the high-k dielectric layer 291 is subject to a planarization process (e.g. a chemical mechanical planarization) until the first dielectric layer 293 is exposed.
- a FinFET structure with the high-k metal gate (HKMG) is shown in FIG. 2J .
- the present invention provides a process of manufacturing a FinFET structure with a high-k metal gate (HKMG). Due to the high-k metal gate, the problems incurred in the process of downscaling and optimizing the FinFET structure will be overcome. Accordingly, the object of the present invention will be achieved.
- HKMG high-k metal gate
- FIGS. 3A , 3 B, 3 C, 3 D, 3 E, 3 F and 3 G are schematic views illustrating a process of forming metal lines and dielectric layers after the FinFET structure with the high-dielectric-constant metal gate as shown in FIG. 2J is produced.
- the first dielectric layer 293 and the contact etch stop layer 294 at both sides of the high-dielectric-constant metal gate are removed to form two slot contact holes 301 .
- a metal layer 302 (e.g. a tungsten layer) is formed on the substrate 2 and filled in the slot contact holes 301 .
- a planarization process (e.g. a chemical mechanical planarization) is performed to remove the excess metal layer 302 , thereby forming a plurality of slot contact structures 303 having a planarized surface 303 a approximately level with a top surface 290 c of the metal gate layer 290 serving as the metal gate electrode of the HKMG in the slot contact holes 301 .
- a metal gate cap layer 304 and a dielectric layer 305 are formed on the substrate 2 having the slot contact structures 303 . Then, by defining the regions of the metal gate cap layer 304 and the dielectric layer 305 over the source, the drain and the gate, thereby forming contact holes 306 (see FIG. 3E ). Then, a barrier layer 307 and a copper layer 308 are formed on the substrate 2 having the contact holes 306 . Then, as shown in FIG. 3F , a planarization process (e.g. a chemical mechanical planarization) is performed to remove the excess copper layer 308 , thereby forming a plurality of copper contact structures 309 .
- a planarization process e.g. a chemical mechanical planarization
- the above damascene process is performed again to form a dielectric layer 310 , a barrier layer 311 and a copper contact structure 312 , so that the metal lines and the dielectric layers are produced.
- FIGS. 4A and 4B are schematic views illustrating a process of forming a salicide layer according to another embodiment of the present invention. After the slot contact holes 301 as shown in FIG. 3A are produced, a selective epitaxial growth (SEG) process is performed to form a raised epi-layer 400 on the surface of the source/drain region 296 (see FIG.
- SEG selective epitaxial growth
- a silicon epitaxial layer is simultaneously deposited on the NMOS and the PMOS.
- different epitaxial materials may be respectively formed on the NMOS and the PMOS.
- a silicon carbide (SiC) epitaxial layer is formed on the NMOS, and a silicon germanium (SiGe) epitaxial layer is formed on the PMOS.
- the NMOS and the PMOS are respectively doped with different dopants.
- the NMOS is doped with a carbon dopant
- the PMOS is doped with a germanium dopant.
- the salicide layer 401 used in the present invention is made of NiPtSi, wherein the concentration of platinum is about 5-10% or even more than 10%.
- a platinum-nickel (NiPt) alloy and a silicon germanium (SiGe) epitaxial layer are collectively employed, a silicon epitaxial layer or a low-Ge (low-Ge-concentration) silicon germanium epitaxial layer may be firstly formed on a high-Ge (high-Ge-concentration) silicon germanium epitaxial layer and then electroplated with a platinum-nickel (NiPt) alloy. In such way, a NiPtSi(Ge) salicide layer is produced.
- the FinFET structure and the manufacturing process of the FinFET structure according to the present invention can effectively overcome the drawbacks encountered from the prior art.
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Abstract
Description
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US13/689,720 US8847325B2 (en) | 2011-03-21 | 2012-11-29 | Fin field-effect transistor structure |
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US13/052,338 US8361854B2 (en) | 2011-03-21 | 2011-03-21 | Fin field-effect transistor structure and manufacturing process thereof |
US13/689,720 US8847325B2 (en) | 2011-03-21 | 2012-11-29 | Fin field-effect transistor structure |
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US13/689,720 Active US8847325B2 (en) | 2011-03-21 | 2012-11-29 | Fin field-effect transistor structure |
US13/693,009 Active US8664055B2 (en) | 2011-03-21 | 2012-12-03 | Fin field-effect transistor structure and manufacturing process thereof |
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JP5569243B2 (en) * | 2010-08-09 | 2014-08-13 | ソニー株式会社 | Semiconductor device and manufacturing method thereof |
US9698229B2 (en) * | 2012-01-17 | 2017-07-04 | United Microelectronics Corp. | Semiconductor structure and process thereof |
US8981496B2 (en) * | 2013-02-27 | 2015-03-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal gate and gate contact structure for FinFET |
US9153483B2 (en) * | 2013-10-30 | 2015-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of semiconductor integrated circuit fabrication |
US9490323B2 (en) * | 2014-06-13 | 2016-11-08 | Samsung Electronics Co., Ltd. | Nanosheet FETs with stacked nanosheets having smaller horizontal spacing than vertical spacing for large effective width |
TWI663729B (en) | 2016-01-05 | 2019-06-21 | 聯華電子股份有限公司 | Semiconductor structure and method for manufacturing the same |
US10643893B2 (en) * | 2016-06-29 | 2020-05-05 | International Business Machines Corporation | Surface area and Schottky barrier height engineering for contact trench epitaxy |
US10083862B2 (en) | 2016-09-12 | 2018-09-25 | International Business Machines Corporation | Protective liner between a gate dielectric and a gate contact |
CN111312812B (en) * | 2018-12-11 | 2023-07-14 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Citations (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6376888B1 (en) | 1999-04-30 | 2002-04-23 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
US6436775B2 (en) | 2000-06-21 | 2002-08-20 | Hynix Semiconductor, Inc. | MOSFET device fabrication method capable of allowing application of self-aligned contact process while maintaining metal gate to have uniform thickness |
US6756277B1 (en) | 2001-02-09 | 2004-06-29 | Advanced Micro Devices, Inc. | Replacement gate process for transistors having elevated source and drain regions |
US6835609B1 (en) * | 2003-09-17 | 2004-12-28 | Chartered Semiconductor Manufacturing Ltd. | Method of forming double-gate semiconductor-on-insulator (SOI) transistors |
US6855607B2 (en) | 2003-06-12 | 2005-02-15 | Advanced Micro Devices, Inc. | Multi-step chemical mechanical polishing of a gate area in a FinFET |
US6869868B2 (en) | 2002-12-13 | 2005-03-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating a MOSFET device with metal containing gate structures |
US6921963B2 (en) | 2003-01-23 | 2005-07-26 | Advanced Micro Devices, Inc | Narrow fin FinFET |
US6970372B1 (en) * | 2004-06-29 | 2005-11-29 | International Business Machines Corporation | Dual gated finfet gain cell |
US6972461B1 (en) | 2004-06-30 | 2005-12-06 | International Business Machines Corporation | Channel MOSFET with strained silicon channel on strained SiGe |
US7026199B2 (en) * | 2003-10-31 | 2006-04-11 | Hynix Semiconductor Inc. | Transistor of semiconductor device and method for manufacturing the same |
US7045401B2 (en) * | 2003-06-23 | 2006-05-16 | Sharp Laboratories Of America, Inc. | Strained silicon finFET device |
US7091551B1 (en) | 2005-04-13 | 2006-08-15 | International Business Machines Corporation | Four-bit FinFET NVRAM memory device |
US7122412B2 (en) | 2004-04-30 | 2006-10-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating a necked FINFET device |
US20060286729A1 (en) | 2005-06-21 | 2006-12-21 | Jack Kavalieros | Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate |
US7176522B2 (en) * | 2003-11-25 | 2007-02-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having high drive current and method of manufacturing thereof |
US7208803B2 (en) * | 2004-05-05 | 2007-04-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a raised source/drain and a semiconductor device employing the same |
US7319063B2 (en) * | 2005-02-02 | 2008-01-15 | United Microelectronics Corp. | Fin field effect transistor and method for manufacturing fin field effect transistor |
US7348641B2 (en) | 2004-08-31 | 2008-03-25 | International Business Machines Corporation | Structure and method of making double-gated self-aligned finFET having gates of different lengths |
US20080157208A1 (en) | 2006-12-29 | 2008-07-03 | Fischer Kevin J | Stressed barrier plug slot contact structure for transistor performance enhancement |
US7425740B2 (en) | 2005-10-07 | 2008-09-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and structure for a 1T-RAM bit cell and macro |
US7531437B2 (en) | 2004-09-30 | 2009-05-12 | Intel Corporation | Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric material |
US20100072553A1 (en) | 2008-09-23 | 2010-03-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | METAL GATE STRESS FILM FOR MOBILITY ENHANCEMENT IN FinFET DEVICE |
US7727832B2 (en) * | 2007-02-05 | 2010-06-01 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
US7902581B2 (en) * | 2005-10-31 | 2011-03-08 | Globalfoundries Inc. | Semiconductor device comprising a contact structure based on copper and tungsten |
US7910994B2 (en) * | 2007-10-15 | 2011-03-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and method for source/drain contact processing |
US7943462B1 (en) * | 2009-10-30 | 2011-05-17 | Globalfoundries Inc. | Transistor including a high-K metal gate electrode structure formed prior to drain/source regions on the basis of a sacrificial carbon spacer |
US20120088345A1 (en) | 2010-10-12 | 2012-04-12 | Yi-Wei Chen | Method of forming silicide for contact plugs |
US8294211B2 (en) * | 2010-01-14 | 2012-10-23 | GlobalFoundries, Inc. | Semiconductor transistor device structure with back side gate contact plugs, and related manufacturing method |
US8350328B2 (en) * | 2009-04-14 | 2013-01-08 | Hitachi, Ltd. | Semiconductor device and method of manufacturing the same |
US8766319B2 (en) * | 2012-04-26 | 2014-07-01 | United Microelectronics Corp. | Semiconductor device with ultra thin silicide layer |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100339425B1 (en) * | 2000-07-21 | 2002-06-03 | 박종섭 | Semiconductor device and Method for Manufacturing with recessed SOI structure |
US6413802B1 (en) * | 2000-10-23 | 2002-07-02 | The Regents Of The University Of California | Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture |
US6855989B1 (en) * | 2003-10-01 | 2005-02-15 | Advanced Micro Devices, Inc. | Damascene finfet gate with selective metal interdiffusion |
US7041542B2 (en) * | 2004-01-12 | 2006-05-09 | Advanced Micro Devices, Inc. | Damascene tri-gate FinFET |
-
2011
- 2011-03-21 US US13/052,338 patent/US8361854B2/en active Active
-
2012
- 2012-11-29 US US13/689,720 patent/US8847325B2/en active Active
- 2012-12-03 US US13/693,009 patent/US8664055B2/en active Active
Patent Citations (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6376888B1 (en) | 1999-04-30 | 2002-04-23 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
US6436775B2 (en) | 2000-06-21 | 2002-08-20 | Hynix Semiconductor, Inc. | MOSFET device fabrication method capable of allowing application of self-aligned contact process while maintaining metal gate to have uniform thickness |
US6756277B1 (en) | 2001-02-09 | 2004-06-29 | Advanced Micro Devices, Inc. | Replacement gate process for transistors having elevated source and drain regions |
US6869868B2 (en) | 2002-12-13 | 2005-03-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating a MOSFET device with metal containing gate structures |
US6921963B2 (en) | 2003-01-23 | 2005-07-26 | Advanced Micro Devices, Inc | Narrow fin FinFET |
US6855607B2 (en) | 2003-06-12 | 2005-02-15 | Advanced Micro Devices, Inc. | Multi-step chemical mechanical polishing of a gate area in a FinFET |
US7045401B2 (en) * | 2003-06-23 | 2006-05-16 | Sharp Laboratories Of America, Inc. | Strained silicon finFET device |
US6835609B1 (en) * | 2003-09-17 | 2004-12-28 | Chartered Semiconductor Manufacturing Ltd. | Method of forming double-gate semiconductor-on-insulator (SOI) transistors |
US7026199B2 (en) * | 2003-10-31 | 2006-04-11 | Hynix Semiconductor Inc. | Transistor of semiconductor device and method for manufacturing the same |
US7176522B2 (en) * | 2003-11-25 | 2007-02-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having high drive current and method of manufacturing thereof |
US7122412B2 (en) | 2004-04-30 | 2006-10-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating a necked FINFET device |
US7208803B2 (en) * | 2004-05-05 | 2007-04-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a raised source/drain and a semiconductor device employing the same |
US6970372B1 (en) * | 2004-06-29 | 2005-11-29 | International Business Machines Corporation | Dual gated finfet gain cell |
US6972461B1 (en) | 2004-06-30 | 2005-12-06 | International Business Machines Corporation | Channel MOSFET with strained silicon channel on strained SiGe |
US7348641B2 (en) | 2004-08-31 | 2008-03-25 | International Business Machines Corporation | Structure and method of making double-gated self-aligned finFET having gates of different lengths |
US7531437B2 (en) | 2004-09-30 | 2009-05-12 | Intel Corporation | Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric material |
US7319063B2 (en) * | 2005-02-02 | 2008-01-15 | United Microelectronics Corp. | Fin field effect transistor and method for manufacturing fin field effect transistor |
US7091551B1 (en) | 2005-04-13 | 2006-08-15 | International Business Machines Corporation | Four-bit FinFET NVRAM memory device |
US20060286729A1 (en) | 2005-06-21 | 2006-12-21 | Jack Kavalieros | Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate |
US7425740B2 (en) | 2005-10-07 | 2008-09-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and structure for a 1T-RAM bit cell and macro |
US7902581B2 (en) * | 2005-10-31 | 2011-03-08 | Globalfoundries Inc. | Semiconductor device comprising a contact structure based on copper and tungsten |
US7968952B2 (en) * | 2006-12-29 | 2011-06-28 | Intel Corporation | Stressed barrier plug slot contact structure for transistor performance enhancement |
US20080157208A1 (en) | 2006-12-29 | 2008-07-03 | Fischer Kevin J | Stressed barrier plug slot contact structure for transistor performance enhancement |
US7727832B2 (en) * | 2007-02-05 | 2010-06-01 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
US7910994B2 (en) * | 2007-10-15 | 2011-03-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and method for source/drain contact processing |
US20100072553A1 (en) | 2008-09-23 | 2010-03-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | METAL GATE STRESS FILM FOR MOBILITY ENHANCEMENT IN FinFET DEVICE |
US8350328B2 (en) * | 2009-04-14 | 2013-01-08 | Hitachi, Ltd. | Semiconductor device and method of manufacturing the same |
US7943462B1 (en) * | 2009-10-30 | 2011-05-17 | Globalfoundries Inc. | Transistor including a high-K metal gate electrode structure formed prior to drain/source regions on the basis of a sacrificial carbon spacer |
US8294211B2 (en) * | 2010-01-14 | 2012-10-23 | GlobalFoundries, Inc. | Semiconductor transistor device structure with back side gate contact plugs, and related manufacturing method |
US20120088345A1 (en) | 2010-10-12 | 2012-04-12 | Yi-Wei Chen | Method of forming silicide for contact plugs |
US8766319B2 (en) * | 2012-04-26 | 2014-07-01 | United Microelectronics Corp. | Semiconductor device with ultra thin silicide layer |
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US8664055B2 (en) | 2014-03-04 |
US20120241863A1 (en) | 2012-09-27 |
US20130087810A1 (en) | 2013-04-11 |
US20130089957A1 (en) | 2013-04-11 |
US8361854B2 (en) | 2013-01-29 |
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