US8817538B2 - Nonvolatile semiconductor memory device and method for erasing data thereof - Google Patents
Nonvolatile semiconductor memory device and method for erasing data thereof Download PDFInfo
- Publication number
- US8817538B2 US8817538B2 US13/493,370 US201213493370A US8817538B2 US 8817538 B2 US8817538 B2 US 8817538B2 US 201213493370 A US201213493370 A US 201213493370A US 8817538 B2 US8817538 B2 US 8817538B2
- Authority
- US
- United States
- Prior art keywords
- voltage
- side select
- memory
- source
- line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active, expires
Links
- 239000004065 semiconductor Substances 0.000 title claims description 106
- 238000000034 method Methods 0.000 title claims description 17
- 238000009825 accumulation Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- 239000010410 layer Substances 0.000 description 175
- 102100038712 Cap-specific mRNA (nucleoside-2'-O-)-methyltransferase 1 Human genes 0.000 description 31
- 101710203121 Cap-specific mRNA (nucleoside-2'-O-)-methyltransferase 1 Proteins 0.000 description 31
- 238000012546 transfer Methods 0.000 description 31
- 230000006870 function Effects 0.000 description 17
- 101100292586 Caenorhabditis elegans mtr-4 gene Proteins 0.000 description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 14
- 238000005304 joining Methods 0.000 description 12
- 102100038716 Cap-specific mRNA (nucleoside-2'-O-)-methyltransferase 2 Human genes 0.000 description 11
- 101710203126 Cap-specific mRNA (nucleoside-2'-O-)-methyltransferase 2 Proteins 0.000 description 11
- 230000002093 peripheral effect Effects 0.000 description 11
- 230000008859 change Effects 0.000 description 9
- 239000000463 material Substances 0.000 description 9
- 238000009826 distribution Methods 0.000 description 8
- 230000005641 tunneling Effects 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 7
- 101000796673 Homo sapiens Transformation/transcription domain-associated protein Proteins 0.000 description 5
- 102100032762 Transformation/transcription domain-associated protein Human genes 0.000 description 5
- 101100426900 Caenorhabditis elegans trd-1 gene Proteins 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 101100370282 Caenorhabditis elegans tra-4 gene Proteins 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000006399 behavior Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
- H01L29/7926—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/71—Three dimensional array
Definitions
- Embodiments described herein relate to a nonvolatile semiconductor memory device in which data is electrically rewritable and a method for erasing the data.
- a nonvolatile semiconductor memory device such as a NAND-type flash memory
- stacking of memory cells is desired since a miniaturizing technique is about to reach the limit.
- a stacked NAND-type flash memory constructing memory transistors with use of vertical transistors.
- the stacked NAND-type flash memory has a memory string containing a plurality of memory transistors connected in series in a stacking direction and selected transistors provided on both ends of the memory string.
- this stacked NAND-type flash memory for the purpose of decreasing a circuit area of a peripheral circuit such as a row decoder, a structure in which a plurality of memory strings arranged in a matrix form are connected in common to one word line is adopted.
- the plurality of memory strings sharing the word line constitute a memory block, which is a minimum unit at the time of data erasure.
- the size of one memory block increases, which causes the minimum unit for data erasure to be larger.
- Making the minimum unit for data erasure smaller substantially means decreasing a data storage capacity, which is not favorable. Accordingly, development of a stacked flash memory enabling only a part of memory cells in one memory block to be erased selectively is desired.
- FIG. 1 illustrates a memory cell array MA and a control circuit CC of a nonvolatile semiconductor memory device according to a first embodiment.
- FIG. 2 is a perspective view illustrating a stacking structure of the memory cell array MA according to the first embodiment.
- FIG. 3 is a cross-sectional view illustrating the stacking structure of the memory cell array MA according to the first embodiment.
- FIG. 4 is a top view illustrating a word line conductive layer 41 a.
- FIG. 5 is a circuit diagram illustrating the control circuit CC according to the first embodiment.
- FIG. 6 is a circuit diagram illustrating a sense amplifier circuit 17 .
- FIG. 7A illustrates voltages to be applied to various wires at the time of executing a selective erasing operation in a memory block according to the first embodiment.
- FIG. 7B illustrates states of respective memory units MU at the time of executing the selective erasing operation in one memory block.
- FIG. 8 illustrates potential relations in a memory unit MU( 1 , 1 ) in the erasing operation according to the first embodiment.
- FIG. 9 illustrates potential relations in a memory unit MU( 1 , 2 ) in the erasing operation according to the first embodiment.
- FIG. 10 illustrates potential relations in a memory unit MU( 2 , 1 ) in the erasing operation according to the first embodiment.
- FIG. 11 illustrates potential relations in a memory unit MU( 2 , 2 ) in the erasing operation according to the first embodiment.
- FIG. 12 is a first timing chart of the erasing operation according to the first embodiment.
- FIG. 13 is a second timing chart of the erasing operation according to the first embodiment.
- FIG. 14 is a timing chart illustrating soft-erasing according to the first embodiment.
- FIG. 15 schematically illustrates an erasing operation according to a second embodiment.
- a nonvolatile semiconductor memory device comprises a semiconductor substrate, a memory cell array, a plurality of word lines, a bit line, a source line, a drain-side select transistor, a source-side select transistor, and a control circuit.
- the memory cell array has a memory string containing a plurality of memory cells.
- the memory cells are stacked on the semiconductor substrate.
- the plurality of word lines are connected to the plurality of memory cells.
- the bit line is electrically connected to one end of the memory string.
- the source line is electrically connected to the other end of the memory string.
- the drain-side select transistor is provided between one end of the memory string and the bit line.
- the source-side select transistor is provided between the other end of the memory string and the source line.
- the control circuit is configured to control voltages to be applied to the memory string, the plurality of word lines, the bit line, and the source line.
- the control circuit is configured to set the drain-side select transistor and the source-side select transistor connected to a selected memory string to non-conductive states.
- the control circuit is configured to apply a first voltage to a non-selected word line connected to a gate of a non-selected memory cell in the selected memory string.
- the control circuit is configured to apply a second voltage to a selected word line connected to a gate of a selected memory cell in the selected memory string. The second voltage is smaller than the first voltage in an erasing operation.
- the nonvolatile semiconductor memory device according to the first embodiment includes a memory cell array MA and a peripheral circuit CC as shown in FIG. 1 .
- a specific configuration of the peripheral circuit CC will be described later in FIG. 5 .
- the memory cell array MA includes m memory blocks MB( 1 ) . . . MB(m) as shown in FIG. 1 . It is to be noted that, in the following description, all the memory blocks MB( 1 ) . . . MB(m) may be collectively described as memory blocks MB.
- Each memory block MB has two sub blocks SB( 1 ) and SB( 2 ). Having two sub blocks is illustrative only, and the number is not limited to this.
- the sub block SB( 1 ) has n memory units MU( 1 , 1 ) to MU( 1 , n).
- the sub block SB( 2 ) has n memory units MU( 2 , 1 ) to MU( 2 , n). Having n memory units is illustrative only, and the number is not limited to this. It is to be noted that, in the following description, all the sub blocks SB( 1 ) and SB( 2 ) may be collectively described as sub blocks SB. Also, all the memory units MU( 1 , 1 ) to MU( 2 , n) may be collectively described as memory units MU.
- bit line BL is formed to extend in a column direction so as to stride over the plurality of memory blocks MB.
- bit lines BL may be collectively described as bit lines BL.
- the memory unit MU has a memory string MS, a source-side select transistor SSTr, and a drain-side select transistor SDTr.
- the memory string MS has memory transistors MTr 1 to MTr 8 (memory cells) and a back gate transistor BTr connected in series as shown in FIG. 1 .
- the memory transistors MTr 1 to MTr 4 and MTr 5 to MTr 8 are connected in series, respectively.
- the back gate transistor BTr is connected between the memory transistor MTr 4 and the memory transistor MTr 5 .
- Each of the memory transistors MTr 1 to MTr 8 holds data by accumulating charges in a charge accumulation layer thereof.
- the back gate transistor BTr is in a conductive state in a case where at least the memory string MS is selected as an operating target.
- word lines WL 1 to WL 8 are connected in common to gates of the memory transistors MTr 1 to MTr 8 arranged in an n-row, 2-column matrix form, respectively.
- a back gate line BG is connected in common to gates of the n-row, 2-column back gate transistors BTr.
- a drain of the source-side select transistor SSTr is connected to a source of the memory string MS.
- a source of the source-side select transistor SSTr is connected to the source line SL.
- each of source-side select gate lines SGS( 1 ) and SGS( 2 ) is connected in common to gates of the n source-side select transistors SSTr arranged in a line in a row direction. It is to be noted that, in the following description, the source-side select gate lines SGS( 1 ) and ( 2 ) may be collectively referred to as source-side select gate lines SGS without distinguishing them.
- a source of the drain-side select transistor SDTr is connected to a drain of the memory string MS.
- a drain of the drain-side select transistor SDTr is connected to the bit line BL.
- each of drain-side select gate lines SGD( 1 ) and SGD( 2 ) is connected in common to gates of the n drain-side select transistors SDTr arranged in a line in a row direction. It is to be noted that, in the following description, the drain-side select gate lines SGD( 1 ) and ( 2 ) may be collectively referred to as drain-side select gate lines SGD without distinguishing them.
- Each memory block MB has a back gate layer 30 , a memory layer 40 , a select transistor layer 50 , and a wiring layer 60 stacked sequentially on a semiconductor substrate as shown in FIGS. 2 and 3 .
- the back gate layer 30 functions as the back gate transistor BTr.
- the memory layer 40 functions as the memory transistors MTr 1 to MTr 8 .
- the select transistor layer 50 functions as the drain-side select transistor SDTr and the source-side select transistor SSTr.
- the wiring layer 60 functions as the source line SL and the bit line BL.
- the back gate layer 30 has a back gate conductive layer 31 as shown in FIGS. 2 and 3 .
- the back gate conductive layer 31 functions as the back gate line BG and a gate of the back gate transistor BTr.
- the back gate conductive layer 31 is formed to spread in a plate shape two-dimensionally in the row direction and the column direction parallel to the semiconductor substrate 20 .
- the back gate conductive layer 31 is made of, e.g., a polysilicon (poly-Si) material.
- the back gate layer 30 has a memory gate insulating layer 43 and a joining semiconductor layer 44 B as shown in FIG. 3 .
- the memory gate insulating layer 43 is provided between the joining semiconductor layer 44 B and the back gate conductive layer 31 .
- the joining semiconductor layer 44 B functions as a body (channel) of the back gate transistor BTr.
- the joining semiconductor layer 44 B is formed to dig in the back gate conductive layer 31 .
- the joining semiconductor layer 44 B is formed approximately in a rectangular shape whose longitudinal direction is a column direction as seen from the upper surface.
- the joining semiconductor layers 44 B are formed in a matrix form in the row direction and the column direction in each memory block MB.
- the joining semiconductor layer 44 B is made of, e.g., a polysilicon (poly-Si) material.
- the memory layer 40 is formed in an upper layer of the back gate layer 30 as shown in FIGS. 2 and 3 .
- the memory layer 40 has four-layered word line conductive layers 41 a to 41 d .
- the word line conductive layer 41 a functions as the word line WL 4 and a gate of the memory transistor MTr 4 .
- the word line conductive layer 41 a also functions as the word line WL 5 and a gate of the memory transistor MTr 5 .
- the word line conductive layers 41 b to 41 d function as the word lines WL 1 to WL 3 and gates of the memory transistors MTr 1 to MTr 3 , respectively.
- the word line conductive layers 41 b to 41 d also function as the word lines WL 6 to WL 8 and gates of the memory transistors MTr 6 to MTr 8 , respectively.
- the word line conductive layers 41 a to 41 d are stacked to sandwich an interlayer insulating layer 45 therebetween vertically. Each of the word line conductive layers 41 a to 41 d is formed to extend in the row direction (vertical direction of the drawing sheet of FIG. 3 ) as a longitudinal direction.
- the word line conductive layers 41 a to 41 d are made of, e.g., a polysilicon (poly-Si) material.
- the memory layer 40 has the memory gate insulating layer 43 , a columnar semiconductor layer 44 A, and a dummy semiconductor layer 44 D as shown in FIGS. 2 and 3 .
- the memory gate insulating layer 43 is provided between the columnar semiconductor layer 44 A and the word line conductive layers 41 a to 41 d .
- the columnar semiconductor layer 44 A functions as bodies (channels) of the memory transistors MTr 1 to MTr 8 .
- the dummy semiconductor layer 44 D is provided in relation to the arrangement pitch and does not constitute a part of the memory transistors MTr 1 to MTr 8 .
- the memory gate insulating layer 43 has a block insulating layer 43 a , a charge accumulation layer 43 b , and a tunnel insulating layer 43 c from a lateral side of the word line conductive layers 41 a to 41 d to a side of a memory semiconductor layer 44 .
- the charge accumulation layer 43 b is configured to enable accumulation of charges.
- the block insulating layer 43 a is formed to have a predetermined thickness on lateral walls of the word line conductive layers 41 a to 41 d .
- the charge accumulation layer 43 b is formed to have a predetermined thickness on a lateral wall of the block insulating layer 43 a .
- the tunnel insulating layer 43 c is formed to have a predetermined thickness on a lateral wall of the charge accumulation layer 43 b .
- the block insulating layer 43 a and the tunnel insulating layer 43 c are made of a silicon oxide (SiO 2 ) material.
- the charge accumulation layer 43 b is made of a silicon nitride (SiN) material.
- the columnar semiconductor layer 44 A is formed to penetrate the word line conductive layers 41 a to 41 d and the interlayer insulating layer 45 .
- the columnar semiconductor layer 44 A extends in a vertical direction to the semiconductor substrate 20 .
- the columnar semiconductor layers 44 A forming a pair are formed to match vicinities of end portions of the joining semiconductor layer 44 B in the column direction.
- the columnar semiconductor layer 44 A is made of, e.g., a polysilicon (poly-Si) material.
- the dummy semiconductor layer 44 D is formed to penetrate the word line conductive layers 41 a to 41 d and the interlayer insulating layer 45 .
- the dummy semiconductor layer 44 D does not constitute a part of the memory transistors MTr 1 to MTr 8 as described above, the dummy semiconductor layer 44 D is not provided with the joining semiconductor layer 44 B and the back gate conductive layer 31 on a lower side thereof.
- a pair of the columnar semiconductor layers 44 A and the joining semiconductor layer 44 B joining their lower ends constitute the memory semiconductor layer 44 functioning as a body (channel) of the memory string MS.
- the memory semiconductor layer 44 is formed in a U shape as seen from the row direction.
- the back gate conductive layer 31 is formed to surround a side surface and a lower surface of the joining semiconductor layer 44 B via the memory gate insulating layer 43 .
- the word line conductive layers 41 a to 41 d are formed to surround a side surface of the columnar semiconductor layer 44 A via the memory gate insulating layer 43 .
- the select transistor layer 50 has a source-side conductive layer 51 a , a drain-side conductive layer 51 b , and a dummy conductive layer 51 c as shown in FIGS. 2 and 3 .
- the source-side conductive layer 51 a functions as the source-side select gate line SGS and a gate of the source-side select transistor SSTr.
- the drain-side conductive layer 51 b functions as the drain-side select gate line SGD and a gate of the drain-side select transistor SDTr.
- the dummy conductive layer 51 c is provided in relation to the arrangement pitch and does not function as the source-side select gate line SGS and the drain-side select gate line SGD.
- the source-side conductive layer 51 a is formed in an upper layer of one columnar semiconductor layer 44 A constituting the memory semiconductor layer 44 .
- the drain-side conductive layer 51 b is on the same layer as the source-side conductive layer 51 a and is formed in an upper layer of the other columnar semiconductor layer 44 A constituting the memory semiconductor layer 44 .
- the dummy conductive layer 51 c is on the same layer as the source-side conductive layer 51 a and is provided at a part other than the upper layers of the columnar semiconductor layers 44 A.
- a plurality of source-side conductive layers 51 a , drain-side conductive layers 51 b , and dummy conductive layers 51 c are formed to extend in the row direction.
- the source-side conductive layers 51 a and the drain-side conductive layers 51 b are made of, e.g., a polysilicon (poly-Si) material.
- the select transistor layer 50 has a source-side gate insulating layer 53 a , a source-side columnar semiconductor layer 54 a , a drain-side gate insulating layer 53 b , a drain-side columnar semiconductor layer 54 b , and a dummy semiconductor layer 54 D as shown in FIG. 3 .
- the source-side columnar semiconductor layer 54 a functions as a body (channel) of the source-side select transistor SSTr.
- the drain-side columnar semiconductor layer 54 b functions as a body (channel) of the drain-side select transistor SDTr.
- the source-side gate insulating layer 53 a is provided between the source-side conductive layer 51 a and the source-side columnar semiconductor layer 54 a .
- the source-side columnar semiconductor layer 54 a is formed to penetrate the source-side conductive layer 51 a .
- the source-side columnar semiconductor layer 54 a is connected to a side surface of the source-side gate insulating layer 53 a and an upper surface of one of the columnar semiconductor layers 44 A forming a pair and is formed in a columnar shape so as to extend in the vertical direction to the semiconductor substrate 20 .
- the source-side columnar semiconductor layer 54 a is made of, e.g., a polysilicon (poly-Si) material.
- the drain-side gate insulating layer 53 b is provided between the drain-side conductive layer 51 b and the drain-side columnar semiconductor layer 54 b .
- the drain-side columnar semiconductor layer 54 b is formed to penetrate the drain-side conductive layer 51 b .
- the drain-side columnar semiconductor layer 54 b is connected to a side surface of the drain-side gate insulating layer 53 b and an upper surface of the other of the columnar semiconductor layers 44 A forming a pair and is formed in a columnar shape so as to extend in the vertical direction to the semiconductor substrate 20 .
- the drain-side columnar semiconductor layer 54 b is made of, e.g., a polysilicon (poly-Si) material.
- the dummy semiconductor layer 54 D is formed to penetrate the dummy conductive layer 51 c .
- the dummy semiconductor layer 54 D is formed in an I shape.
- a lower surface of the dummy semiconductor layer 54 D contacts an upper surface of the dummy semiconductor layer 44 D.
- the wiring layer 60 has a source line layer 61 , a bit line layer 62 , and a plug layer 63 .
- the source line layer 61 functions as the source line SL.
- the bit line layer 62 functions as the bit line BL.
- the source line layer 61 contacts an upper surface of the source-side columnar semiconductor layer 54 a and is formed to extend in the row direction.
- the bit line layer contacts an upper surface of the drain-side columnar semiconductor layer 54 b via the plug layer 63 and is formed to extend in the column direction.
- the source line layer 61 , the bit line layer 62 , and the plug layer 63 are made of, e.g., a metal material such as tungsten.
- the shape of the word line conductive layer 41 a will be described in detail. It is to be noted that description of the word line conductive layers 41 b to 41 d is not repeated here since they have similar shapes to that of the word line conductive layer 41 a.
- a pair of word line conductive layers 41 a is provided in each memory block MB as shown in FIG. 4 .
- One word line conductive layer 41 a is formed in a T shape (protruded shape) as seen from the upper surface.
- the other word line conductive layer 41 a is formed in a U shape (recessed shape) so as to be opposed to the T-shaped word line conductive layer 41 a.
- the peripheral circuit CC has an address decoder circuit 11 , booster circuits 12 a to 12 c , word line driving circuits 13 a and 13 b , a back gate line driving circuit 14 , select gate line driving circuits 15 a and 15 b , a source line driving circuit 16 , a sense amplifier circuit 17 , a sequencer 18 , and row decoder circuits 19 a and 19 b as shown in FIG. 5 .
- the address decoder circuit 11 is connected to the row decoders 19 a and 19 b via buses.
- the address decoder circuit 11 outputs a signal BAD to the row decoder circuits 19 a and 19 b .
- the signal BAD is a signal to designate a memory block MB(block address).
- Each of the booster circuits 12 a to 12 c generates a booster voltage by raising a base voltage.
- the booster circuit 12 a is connected to the word line driving circuits 13 a and 13 b .
- the booster circuit 12 a transfers a booster voltage to the word line driving circuits 13 a and 13 b .
- the booster circuit 12 b is connected to the source line driving circuit 16 .
- the booster circuit 12 b outputs a booster voltage to the source line driving circuit 16 .
- the booster circuit 12 c is connected to the row decoder circuits 19 a and 19 b .
- the booster circuit 12 c outputs a booster signal RDEC to the row decoder circuits 19 a and 19 b.
- the word line driving circuit 13 a is connected to the row decoder 19 a .
- the word line driving circuit 13 a outputs signals VCG 5 to VCG 8 to the row decoder 19 a .
- the word line driving circuit 13 b is connected to the row decoder 19 b .
- the word line driving circuit 13 b outputs signals VCG 1 to VCG 4 to the row decoder 19 b .
- the signals VCG 1 to VCG 8 are used when the word lines WL 1 to WL 8 in a selected memory block MB are driven.
- the back gate line driving circuit 14 is connected to the row decoder 19 b .
- the back gate line driving circuit 14 outputs a signal VBG to the row decoder 19 b .
- the signal VBG is used when the back gate line BG in the selected memory block MB is driven.
- the select gate line driving circuit 15 a is connected to the row decoder 19 a .
- the select gate line driving circuit 15 a outputs a signal VSGS 2 , a signal VSGD 1 , and a signal VSGOFF to the row decoder 19 a .
- the select gate line driving circuit 15 b is connected to the row decoder 19 b .
- the select gate line driving circuit 15 b outputs a signal VSGS 1 , a signal VSGD 2 , and a signal VSGOFF to the row decoder 19 b .
- the signals VSGS 1 and VSGS 2 are used when the source-side select gate lines SGS( 1 ) and SGS( 2 ) in the select memory block MB are driven, respectively.
- the signals VSGD 1 and VSGD 2 are used when the drain-side select gate lines SGD( 1 ) and SGD( 2 ) in the select memory block MB are driven, respectively.
- the signals VSGOFF are used when the source-side select gate lines SGS( 1 ) and SGS( 2 ) and the drain-side select gate lines SGD( 1 ) and SGD( 2 ) in a non-select memory block MB are driven.
- the aforementioned signals VSGS 2 , VSGD 1 , and VSGOFF are input from the select gate line driving circuit 15 a via the row decoder circuit 19 a to various wires. Also, the signals VSGOFF, VSGD 2 , and VSGS 1 are input from the select gate line driving circuit 15 b via the row decoder circuit 19 b to various wires.
- the source line driving circuit 16 is connected to the source line SL.
- the source line driving circuit 16 outputs a signal VSL to the source line SL.
- the signal VSL is used when the source line SL is driven.
- the sense amplifier circuit 17 is connected to the bit line BL.
- the sense amplifier circuit 17 outputs a signal VBL to charge the bit line BL to reach a predetermined voltage and thereafter determines holding data of the memory transistors MTr 1 to MTr 8 based on changes in the voltage of the bit line BL.
- the sequencer 18 is connected to the aforementioned circuits 11 to 17 .
- the sequencer 18 supplies the circuits 11 to 17 with control signals to control these circuits.
- Each of the row decoder circuits 19 a and 19 b is provided for each memory block MB.
- the row decoder 19 a is connected to the word lines WL 5 to WL 8 , the source-side select gate line SGS( 2 ), and the drain-side select gate line SGD( 1 ).
- the row decoder 19 b is connected to the word lines WL 1 to WL 4 , the back gate line BG, the drain-side select gate line SGD( 2 ), and the source-side select gate line SGS( 1 ).
- the row decoder circuit 19 a inputs signals VCG 5 ⁇ i> to VCG 8 ⁇ i> to the gates of the memory transistors MTr 5 to MTr 8 via the word lines WL 5 to WL 8 based on the signal BAD and the signals VCG 5 to VCG 8 .
- the row decoder circuit 19 a also selectively inputs a signal VSGS 2 ⁇ i> to the gate of the source-side select transistor SSTr in the sub block SB( 2 ) via the source-side select gate line SGS( 2 ) based on the signal BAD, the signal VSGS 2 , and the signal VSGOFF.
- the row decoder circuit 19 a further selectively inputs a signal VSGD 1 ⁇ i> to the gate of the drain-side select transistor SDTr in the sub block SB( 1 ) via the drain-side select gate line SGD( 1 ) based on the signal BAD, the signal VSGD 1 , and the signal VSGOFF.
- the row decoder circuit 19 a has a voltage converting circuit 19 aa , first transfer transistors Tra 1 to Tra 6 , and second transfer transistors Trb 1 and Trb 2 .
- the voltage converting circuit 19 aa is connected to the address decoder circuit 11 , the booster circuit 12 c , gates of the first transfer transistors Tra 1 to Tra 6 , and gates of the second transfer transistors Trb 1 and Trb 2 .
- the voltage converting circuit 19 aa generates a signal VSELa ⁇ i> based on the signal BAD and the signal RDEC and outputs it to the gates of the first transfer transistors Tra 1 to Tra 6 .
- the voltage converting circuit 19 aa also generates a signal VUSELa ⁇ i> based on the signal BAD and the signal RDEC and outputs it to the gates of the second transfer transistors Trb 1 and Trb 2 .
- the first transfer transistors Tra 1 to Tra 4 are connected between the word line driving circuit 13 a and the word lines WL 5 to WL 8 , respectively.
- the first transfer transistors Tra 1 to Tra 4 output the signals VCG 5 ⁇ i> to VCG 8 ⁇ i> to the word lines WL 5 to WL 8 based on the signals VCG 5 to VCG 8 and VSELa ⁇ i>, respectively.
- the first transfer transistor Tra 5 is connected between the select gate line driving circuit 15 a and the drain-side select gate line SGD( 1 ).
- the first transfer transistor Tra 5 outputs the signal VSGD 1 ⁇ i> to the drain-side select gate line SGD( 1 ) based on the signal VSGD 1 and the signal VSELa ⁇ i>.
- the first transfer transistor Tra 6 is connected between the select gate line driving circuit 15 a and the source-side select gate line SGS( 2 ).
- the first transfer transistor Tra 6 outputs the signal VSGS 2 ⁇ i> to the source-side select gate line SGS( 2 ) based on the signal VSGS 2 and the signal VSELa ⁇ i>.
- the second transfer transistor Trb 1 is connected between the select gate line driving circuit 15 a and the drain-side select gate line SGD( 1 ).
- the second transfer transistor Trb 2 is connected between the select gate line driving circuit 15 a and the source-side select gate line SGS( 2 ).
- the row decoder circuit 19 b inputs signals VCG 1 ⁇ i> to VCG 4 ⁇ i> to the gates of the memory transistors MTr 1 to MTr 4 via the word lines WL 1 to WL 4 based on the signal BAD and the signals VCG 1 to VCG 4 .
- the row decoder circuit 19 b also inputs a signal VBG ⁇ i> to the gate of the back gate transistor BTr via the back gate line BG based on the signal BAD and the signal VBG.
- the row decoder circuit 19 b further selectively inputs a signal VSGS 1 ⁇ i> to the gate of the source-side select transistor SSTr in the sub block SB( 1 ) via the source-side select gate line SGS( 1 ) based on the signal BAD, the signal VSGS 1 , and the signal VSGOFF.
- the row decoder circuit 19 b still further selectively inputs a signal VSGD 2 ⁇ i> to the gate of the drain-side select transistor SDTr in the sub block SB( 2 ) via the drain-side select gate line SGD( 2 ) based on the signal BAD, the signal VSGD 2 , and the signal VSGOFF.
- the row decoder circuit 19 b has a voltage converting circuit 19 ba , first transfer transistors Trc 1 to Trc 7 , and second transfer transistors Trd 1 and Trd 2 .
- the voltage converting circuit 19 ba is connected to the address decoder circuit 11 , the booster circuit 12 c , gates of the first transfer transistors Trc 1 to Trc 7 , and gates of the second transfer transistors Trd 1 and Trd 2 .
- the voltage converting circuit 19 ba generates a signal VSELb ⁇ i> based on the signal BAD and the signal RDEC and outputs it to the gates of the first transfer transistors Trc 1 to Trc 7 .
- the voltage converting circuit 19 ba also generates a signal VUSELb ⁇ i> based on the signal BAD and the signal RDEC and outputs it to the gates of the second transfer transistors Trd 1 and Trd 2 .
- the first transfer transistors Trc 1 to Trc 4 are connected between the word line driving circuit 13 b and the word lines WL 1 to WL 4 , respectively.
- the first transfer transistors Trc 1 to Trc 4 output the signals VCG 1 ⁇ i> to VCG 4 ⁇ i> to the word lines WL 1 to WL 4 based on the signals VCG 1 to VCG 4 and VSELb ⁇ i>, respectively.
- the first transfer transistor Trc 5 is connected between the back gate line driving circuit 14 and the back gate line BG.
- the first transfer transistor Trc 5 outputs the signal VBG ⁇ i> to the back gate line BG based on the signal VBG and the signal VSELb ⁇ i>.
- the first transfer transistor Trc 6 is connected between the select gate line driving circuit 15 b and the source-side select gate line SGS( 1 ).
- the first transfer transistor Trc 6 outputs the signal VSGS 1 ⁇ i> to the source-side select gate line SGS( 1 ) based on the signal VSGS 1 and the signal VSELb ⁇ i>.
- the first transfer transistor Trc 7 is connected between the select gate line driving circuit 15 b and the drain-side select gate line SGD( 2 ).
- the first transfer transistor Trc 7 outputs the signal VSGD 2 ⁇ i> to the drain-side select gate line SGD( 2 ) based on the signal VSGD 2 and the signal VSELb ⁇ i>.
- the second transfer transistor Trd 1 is connected between the select gate line driving circuit 15 b and the source-side select gate line SGS( 1 ).
- the second transfer transistor Trd 2 is connected between the select gate line driving circuit 15 b and the drain-side select gate line SGD( 2 ).
- the configuration of the peripheral circuit CC described above and shown in FIG. 5 enables an erasing operation of the first embodiment to be executed.
- the sense amplifier circuit 17 has a plurality of select circuits 171 and voltage converting circuits 172 A and 172 B as shown in FIG. 6 .
- the select circuit 171 selectively connects the bit line BL to the source line SL and sets a potential of the bit line BL to be equal to a potential of the source line SL.
- the select circuit 171 has a page buffer 171 a and transistors 171 b and 171 c as shown in FIG. 6 .
- the page buffer 171 a receives a signal from the bit line BL and inputs an output based on the signal to an input-output terminal I/O and the address decoder circuit 11 (refer to FIG. 5 ).
- One end of the transistor 171 b is connected to the page buffer 171 a .
- the other end of the transistor 171 b is connected to the bit line BL, and a control gate thereof receives an output signal VCUT from the voltage converting circuit 172 A.
- One end of the transistor 171 c is connected to the bit line BL.
- the other end of the transistor 171 c is connected to the source line SL, and a control gate thereof receives an output signal VRST from the voltage converting circuit 172 B.
- the voltage converting circuit 172 A receives a signal from the sequencer 18 and outputs the signal VCUT based on the signal.
- the voltage converting circuit 172 B receives a signal from the sequencer 18 and outputs the signal VRST based on the signal.
- FIG. 7A illustrates voltages to be applied to various wires in a case of performing such a selective erasing operation.
- FIG. 7A schematically illustrates a memory unit MU( 1 , 1 ) containing a memory transistor targeted for erasure and memory units MU( 1 , 2 ), MU( 2 , 1 ), and MU( 2 , 2 ) in the same block.
- FIG. 7B illustrates individual states of the respective memory units MU at the time of executing the aforementioned selective erasing operation.
- the memory transistors MTr 5 to MTr 8 are not shown, and bodies of the memory strings MS are shown to extend in a stacking direction.
- the memory unit MU( 1 , 2 ) is connected in common to the memory unit MU( 1 , 1 ) by the source-side select gate line SGS( 1 ) and the drain-side select gate line SGD( 1 ).
- the memory unit MU( 2 , 2 ) is connected in common to the memory unit MU( 2 , 1 ) by the source-side select gate line SGS( 2 ) and the drain-side select gate line SGD( 2 ).
- the memory unit MU( 2 , 1 ) is connected in common to the memory unit MU( 1 , 1 ) by the bit line BL( 1 ). Also, the memory unit MU( 2 , 2 ) is connected in common to the memory unit MU( 1 , 2 ) by the bit line BL( 2 ).
- the peripheral circuit CC executes an erasing operation selectively to a memory string MS (selected memory string) contained in the memory unit MU( 1 , 1 ) in the memory block MB( 1 ) (selected memory block). More specifically, the peripheral circuit CC executes the erasing operation selectively, e.g., to the memory transistor MTr 3 (selected memory transistor) of the memory string MS.
- the peripheral circuit CC prohibits the erasing operation of the other memory transistors MTr 1 , MTr 2 , and MTr 4 to MTr 8 (non-selected memory transistors) in the selected memory unit MU( 1 , 1 ).
- the peripheral circuit CC prohibits the erasing operation of non-selected memory strings in the memory cell units MU(memory units MU( 1 , 2 ), MU( 2 , 1 ), and MU( 2 , 2 )) other than the selected memory unit MU( 1 , 1 ) in the memory block MB( 1 ).
- the bit line BL( 1 ) connected to the memory unit MU( 1 , 1 ) is applied thereto a voltage Vmid (5 to 15 V or so).
- the source line SL is applied thereto a voltage Vmid.
- a voltage Vt is a threshold voltage of the select transistors SSTr and SDTr or a voltage value approximate to it and is 1.5 V or so, for example.
- ground potential To the word line WL 3 (selected word line) connected to the gate of the selected memory transistor MTr 3 is given a ground potential (GND).
- GND ground potential
- the word lines WL 1 , WL 2 , WL 4 to WL 8 (non-selected word lines) and the back gate line BG are given ground potentials immediately after a start of the erasing operation and are thereafter given voltages Vera (Vera>Vmid) at after-mentioned timing.
- drain-side select gate line SGD( 1 ) and the source-side select gate line SGS( 1 ) connected to the selected memory unit ( 1 , 1 ) are applied thereto voltages Vmid.
- the drain-side select transistor SDTr and the source-side select transistor SSTr are in non-conductive states, and the columnar semiconductor layer 44 A (body) of the memory unit MU( 1 , 1 ) is in a floating state, as shown in FIG. 7B .
- the voltages Vera are applied to the non-selected word lines WL 1 , WL 2 , and WL 4 connected to the gates of the non-selected memory transistors (MTr 1 to 2 , MTr 4 to 8 ) in the memory unit ( 1 , 1 ) while the ground voltage GND is applied to the selected word line WL 3 connected to the gate of the selected memory transistor MTr 3 .
- the potential of the body of each of the non-selected memory transistors MTr 1 to 2 and MTr 4 to 8 is raised close to the voltage Vera by capacitive coupling.
- the potential of the body of the selected memory transistor MTr 3 is maintained close to the ground potential GND.
- the potential difference of the body of the memory transistor MTr 3 and the potential differences of the bodies of the memory transistors MTr 2 and MTr 4 cause tunneling current in the memory transistor MTr 3 . Holes generated by this tunneling current are injected into the body of the memory transistor MTr 3 , and the voltage of the body of the memory transistor MTr 3 is raised. By doing so, a high voltage is applied between the gate and the body of the memory transistor MTr 3 (selected memory transistor), and the erasing operation is executed selectively to the memory transistor MTr 3 .
- the non-selected memory unit MU( 1 , 2 ) is connected to the word lines WL 1 to WL 8 , the back gate line BG, the drain-side select gate line SGD( 1 ), the source-side select gate line SGS( 1 ), and the source line SL in common with the selected memory unit MU( 1 , 1 ).
- the non-selected memory unit MU( 1 , 2 ) is connected to the bit line BL( 2 ), which is different from the bit line BL( 1 ) connected to the selected memory unit MU( 1 , 1 ).
- a voltage Vmid ⁇ Vt To this bit line BL( 2 ) is applied a voltage Vmid ⁇ Vt.
- the source-side select transistor SSTr is maintained to be in a non-conductive state.
- the voltage Vmid ⁇ Vt is applied to the bit line BL( 2 ) while the voltage Vmid is applied to the drain-side select gate line SGD( 1 ), and thus, when the voltage of the body of the non-selected memory unit MU( 1 , 2 ) is raised to the voltage Vmid or higher, the drain-side select transistor SDTr is conductive.
- the potential of the body of the non-selected memory unit MU( 1 , 2 ) is raised by coupling because the potential of each of the non-selected word lines WL 1 , WL 2 , and WL 4 is raised to Vera in a similar manner to the selected memory unit MU( 1 , 1 ).
- the drain-side select transistor SDTr and the source-side select transistor SSTr turn on.
- the potential of the body of the non-selected memory unit MU( 1 , 2 ) is not raised to the voltage Vmid or higher.
- the voltage of the body of each of the memory transistors MTr 1 to 2 and 4 to 8 is maintained close to the voltage Vmid.
- the potential difference between the voltage Vmid and the voltage Vera is set to a value that prevents a sufficient erasing operation from being executed.
- the potential difference between the voltage Vmid and the ground voltage GND is set to a value that prevents a sufficient erasing operation from being executed in a similar manner to the potential difference between the voltage Vmid and the voltage Vera.
- data held in the memory transistor MTr 3 does not change.
- the non-selected memory unit MU( 2 , 1 ) is connected to the word lines WL 1 to WL 8 , the back gate line BG, the bit line BL( 1 ), and the source line SL in common with the selected memory unit MU( 1 , 1 ).
- the non-selected memory unit MU( 2 , 1 ) is connected to the drain-side select gate line SGD( 2 ) and the source-side select gate line SGS( 2 ), which are different from the drain-side select gate line SGD( 1 ) and the source-side select gate line SGS( 1 ) connected to the selected memory unit MU( 1 , 1 ).
- the source-side select transistor SSTr is conductive. Also, since the voltage Vmid is applied to the bit line BL( 1 ), and the voltage Vmid+Vt is applied to the drain-side select gate line SGD( 2 ), the drain-side select transistor SDTr is conductive. Thus, the potential of the body of the non-selected memory unit MU( 2 , 1 ) is not raised to the voltage Vmid or higher. Accordingly, a sufficient erasing operation is not executed to the memory transistors MTr 1 to 8 , and data held in the memory transistors MTr 1 to 8 does not change.
- the non-selected memory unit MU( 2 , 2 ) is connected to the word lines WL 1 to WL 8 , the back gate line BG, and the source line SL in common with the selected memory unit MU( 1 , 1 ).
- the non-selected memory unit MU( 2 , 2 ) also is connected to the bit line BL( 2 ) in common with the non-selected memory unit MU( 1 , 2 ).
- the non-selected memory unit MU( 2 , 2 ) further is connected to the drain-side select gate line SGD( 2 ) and the source-side select gate line SGS( 2 ) in common with the non-selected memory unit MU( 2 , 1 ).
- the source-side select transistor SSTr and the drain-side select transistor SDTr are conductive as shown in FIG. 7B .
- the potential of the body of the non-selected memory unit MU( 2 , 2 ) is not raised to the voltage Vmid or higher. Accordingly, a sufficient erasing operation is not executed to the memory transistors MTr 1 to 8 , and data held in the memory transistors MTr 1 to 8 does not change.
- FIG. 8 the potential relations of the selected memory unit MU( 1 , 1 ) will be described.
- a voltage is applied as in FIG. 7A described above in an initial state (“a” in FIG. 8 )
- the drain-side select transistor SDTr and the source-side select transistor SSTr are in non-conductive states (OFF) (“b” in FIG. 8 ) in the selected memory unit MU( 1 , 1 ).
- the bodies of the memory transistors MTr 1 to MTr 8 in the selected memory unit MU( 1 , 1 ) are in floating states.
- the voltages Vera are applied to the gates of the memory transistors MTr 1 , MTr 2 , and MTr 4 to MTr 8 , and the voltage GND is applied to the gate of the memory transistor MTr 3 . Accordingly, while the voltages of the bodies of the memory transistors MTr 1 , MTr 2 , and MTr 4 to MTr 8 are raised to the voltages Vera as the bodies are coupled with their gates, the voltage of the body of the memory transistor MTr 3 is not raised and is approximately the ground voltage GND. This causes potential constrictions between the memory transistor MTr 3 and each of the memory transistors MTr 2 and MTr 4 . At each of these potential constricted parts, tunneling current is generated beyond the potential barrier (“b” in FIG. 8 ).
- FIG. 9 the potential relations of the non-selected memory unit MU( 1 , 2 ) will be described.
- a voltage is applied as in FIG. 7A described above in an initial state (“a” in FIG. 9 )
- the voltages of the bodies of the memory transistors MTr 4 to 8 are raised to the voltages Vmid or higher
- the drain-side select transistor SDTr is in a conductive state (ON) while the source-side select transistor SSTr is maintained to be in a non-conductive state (OFF) (“b” in FIG. 9 ).
- the memory transistors MTr 1 and MTr 2 are in floating states (“b” in FIG. 9 ).
- the bodies of the memory transistors MTr 1 and MTr 2 are coupled with their gates, to which the voltages Vera are applied, and are charged to reach the voltages Vera.
- the gate of the memory transistor MTr 3 is grounded (GND). This causes a potential constriction between the memory transistor MTr 2 and the memory transistor MTr 3 . At this potential constricted part, tunneling current is generated beyond the potential barrier (“b” in FIG. 9 ).
- a memory unit ( 1 , 3 ) to an MU( 1 , n) have similar potential relations to those of the non-selected memory unit MU( 1 , 2 ), and data in the memory transistors MTr 1 to MTr 8 contained therein does not change.
- the drain-side select transistor SDTr and the source-side select transistor SSTr are in conductive states (ON) (“b” in FIG. 10 ) in the non-selected memory unit MU( 2 , 1 ).
- the bodies of the memory transistors MTr 1 , 2 , and 4 to 8 are charged to reach the voltages Vmid.
- tunneling current is not generated, and the voltage of the body of the memory transistor MTr 3 is only raised close to the voltage Vmid. Accordingly, in the non-selected memory unit MU( 2 , 1 ), no high voltage is applied between the gate and the body of the memory transistor MTr 3 , and data in the memory transistor MTr 3 does not change.
- FIG. 11 the potential relations of the non-selected memory unit MU( 2 , 2 ) will be described.
- a voltage is applied as in FIG. 7A described above in an initial state (“a” in FIG. 11 )
- the drain-side select transistor SDTr and the source-side select transistor SSTr are in conductive states (ON) (“b” in FIG. 11 ) in the memory unit MU( 2 , 2 ).
- the charges trapped in the charge accumulation layer have an effect of shielding electric field exerted to the body by the gate.
- the potential in the body can be different from that in FIGS. 8 to 11 depending on the writing state in the memory transistor.
- the tunneling effect occurs when the potential is above a potential difference and does not occur when the potential is below it for simplicity. Also, in the description, the charge flow occurs only in forward bias and stops in backward bias (until the tunneling effect occurs). However, since an intermediate state exists in an actual case, behaviors of charges are not always as simple as in FIGS. 8 to 11 , and the potential in the body can be different from that in FIGS. 8 to 11 .
- the impurity concentration in the body is constant for simplicity.
- the internal impurity concentration is adjusted at the time of manufacture.
- the potential in the body can be different from that in FIGS. 8 to 11 .
- FIGS. 5 and 12 control timing of various wires at the time of the erasing operation will be described in detail.
- an i-th memory block MB ⁇ i> is selected while the other memory block MB ⁇ x> is not selected.
- a j-th bit line BL ⁇ j> is selected while a bit line BL ⁇ k> (k is a natural number other than j) is not selected.
- the voltages of the signal VSELa ⁇ i> and the signal VSELb ⁇ i> in the memory block MB ⁇ i> are first raised to voltages Vpp.
- the voltages of the other signal VSELa ⁇ x> and signal VSELb ⁇ x> are maintained to be voltages VNN.
- only the selected memory block MB ⁇ i> is selected while the other memory block MB ⁇ x> is not selected.
- the voltages of the signals VSGD 1 ⁇ i> and VSGS 1 ⁇ i> in the selected memory block MB ⁇ i> are raised to the voltages Vmid.
- the voltages of the source-side select gate line SGS( 1 ) and the drain-side select gate line SGD( 1 ) are raised to the voltages Vmid.
- the voltages of the signals VSGD 2 ⁇ i> and VSGS 2 ⁇ i> are raised to the voltages Vmid+Vt. By doing so, the voltages of the source-side select gate line SGS( 2 ) and the drain-side select gate line SGD( 2 ) are raised to the voltages Vmid+Vt.
- the voltages of signals VBL ⁇ j> and VBL ⁇ k> are raised to the voltages Vmid and Vmid ⁇ Vt, respectively.
- the voltages of the selected bit line BL ⁇ j> and the non-selected bit line BL ⁇ k> are raised to the voltages Vmid and Vmid ⁇ Vt, respectively.
- the voltages of the signals VCG 1 ⁇ i> to 2 ⁇ i> and 4 ⁇ i> to 8 ⁇ i> are raised to the voltages Vera.
- the voltages of the non-selected word lines WL 1 , WL 2 , and WL 4 to WL 8 and the back gate line BG in the selected memory block MB ⁇ i> are raised to the voltages Vera in a predetermined period of time from time t 13 to t 14 .
- the control timing of various wires at the time of the erasing operation of the present embodiment is not limited to the timing control shown in FIG. 12 and may be timing control shown in FIG. 13 .
- the timing control shown in FIG. 13 at time t 12 , after the voltages of the signals VCG 1 ⁇ i> to 2 ⁇ i> and 4 ⁇ i> to 8 ⁇ i> are once raised to the voltages Vdd, they are maintained to be the voltages Vdd from time t 12 to t 13 a .
- the voltages of the signals VCG 1 ⁇ i> to 2 ⁇ i> and 4 ⁇ i> to 8 ⁇ i> are then raised to the voltages Vera in a predetermined period of time from time t 13 a to t 14 .
- the voltages of the non-selected word lines WL 1 , WL 2 , and WL 4 to WL 8 and the back gate line BG in the selected memory block MB ⁇ i> are once raised to the voltages Vdd and are then maintained to be the voltages Vdd from time t 12 to t 13 a .
- the voltages of the non-selected word lines WL 1 , WL 2 , and WL 4 to WL 8 and the back gate line BG are raised to the voltages Vera in a predetermined period of time from time t 13 a to t 14 .
- the aforementioned erasing operation can be applied to soft-erasing, which is conducted to change the threshold distribution of a memory transistor MTr in an over-programmed state into an appropriate threshold distribution.
- the over-programmed state represents a state in which an excessive writing operation is performed to cause the threshold distribution of the memory transistor MTr to exceed an allowable range.
- a writing operation at level A has been performed to the memory transistor MTr, but when the threshold distribution of the memory transistor MTr exceeds an allowable range, and an excessive writing operation is performed to have a threshold voltage at level B, for example, data is possibly read erroneously.
- the over-programmed state means a state in which an upper limit voltage Vth of the threshold voltage distribution of the memory transistor is higher than a predetermined allowable voltage Vmax.
- Soft-erasing means an operation in which the threshold voltage distribution is shifted so that the upper limit of the threshold voltage distribution of the memory transistor may be below the allowable voltage Vmax.
- the soft-erasing is executed as a flowchart shown in FIG. 14 .
- the soft-erasing shall be executed to the selected memory transistor MTr 3 in the selected memory unit MU( 1 , 1 ).
- verifying readout is executed to the memory transistor MTr 3 (step S 101 ).
- the verifying readout to the selected memory transistor MTr 3 is executed in the following manner, for example. That is, the bit line BL 1 is first charged to reach a predetermined voltage, and the source line SL is grounded (GND).
- the drain-side select transistor SDTr, the source-side select transistor SSTr, and the non-selected memory transistors MTr 1 , MTr 2 , MTr 4 to MTr 8 are in conductive states.
- the gate of the selected memory transistor MTr 3 is applied thereto an allowable voltage Vmax.
- step S 101 when it is determined by the verifying operation at step S 101 that the memory transistor MTr 3 is in an over-programmed state (step S 102 , N), the soft-erasing is executed selectively to the memory transistor MTr 3 (step S 103 ), and step S 101 is thereafter executed.
- step S 101 when it is determined by the verifying operation at step S 101 that the memory transistor MTr 3 is not in an over-programmed state (step S 102 , Y), the processing ends.
- the soft-erasing at step S 103 is executed selectively to the memory transistor MTr 3 contained in the selected memory unit MU( 1 , 1 ) in the selected memory block MB( 1 ) and is not executed to the other memory transistors MTr.
- a conventional erasing operation employs a method of performing erasure to all the memory transistors MTr contained in the memory block MB( 1 ) at a time.
- data of all the memory transistors MTr contained in the selected memory block MB( 1 ) are erased at a time, and a writing operation is thereafter performed again selectively to the memory transistors MTr. That is, data of all the memory transistors MTr contained in the non-selected memory block MB do not need to be erased.
- the nonvolatile semiconductor memory device of the present embodiment can shorten operating time as much as time for erasing data of all the memory transistors MTr contained in the non-selected memory block MB, compared with the conventional one.
- nonvolatile semiconductor memory device According to a second embodiment, Description of a configuration of the second embodiment is not repeated here since the second embodiment is configured in a similar manner to that of the first embodiment.
- the second embodiment differs from the first embodiment in terms of an erasing operation described below.
- the drain-side select gate line SGD( 1 ) and the source-side select gate line SGS( 1 ) are grounded (GND).
- the drain-side select gate line SGD( 2 ) and the source-side select gate line SGS( 2 ) are applied thereto the voltages Vt.
- the selected word line WL 3 is applied thereto voltage—Vmid.
- the non-selected word lines WL 1 , WL 2 , and WL 4 to WL 8 are applied thereto the voltages Vmid.
- the bit line BL( 1 ) and the source line SL are grounded (GND), and the bit line BL( 2 ) is applied thereto voltage ⁇ Vt.
- the second embodiment can execute the erasing operation selectively to one selected memory transistor MTr 3 in the selected memory unit MU( 1 , 1 ) in a similar manner to that of the first embodiment.
- the voltages applied to the wirings SL, BL, SGS, SGD, WL 1 to WL 8 , and BG are not limited to the voltages shown in FIG. 7A or FIG. 15 , and need only have a relative relation of the voltages shown in FIG. 7A or FIG. 15 .
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
Claims (18)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/338,975 US20140334231A1 (en) | 2011-06-14 | 2014-07-23 | Nonvolatile semiconductor memory device and method for erasing data thereof |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011132424A JP5524134B2 (en) | 2011-06-14 | 2011-06-14 | Nonvolatile semiconductor memory device |
JP2011-132424 | 2011-06-14 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/338,975 Continuation US20140334231A1 (en) | 2011-06-14 | 2014-07-23 | Nonvolatile semiconductor memory device and method for erasing data thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
US20120320698A1 US20120320698A1 (en) | 2012-12-20 |
US8817538B2 true US8817538B2 (en) | 2014-08-26 |
Family
ID=47353569
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/493,370 Active 2032-09-05 US8817538B2 (en) | 2011-06-14 | 2012-06-11 | Nonvolatile semiconductor memory device and method for erasing data thereof |
US14/338,975 Abandoned US20140334231A1 (en) | 2011-06-14 | 2014-07-23 | Nonvolatile semiconductor memory device and method for erasing data thereof |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/338,975 Abandoned US20140334231A1 (en) | 2011-06-14 | 2014-07-23 | Nonvolatile semiconductor memory device and method for erasing data thereof |
Country Status (2)
Country | Link |
---|---|
US (2) | US8817538B2 (en) |
JP (1) | JP5524134B2 (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8891306B2 (en) * | 2013-01-02 | 2014-11-18 | SK Hynix Inc. | Semiconductor memory device |
US20150009755A1 (en) * | 2010-11-29 | 2015-01-08 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
US20150036429A1 (en) * | 2013-07-30 | 2015-02-05 | SK Hynix Inc. | Semiconductor memory device |
US9799403B2 (en) * | 2014-03-14 | 2017-10-24 | Toshiba Memory Corporation | Semiconductor memory device |
US20230034752A1 (en) * | 2021-07-21 | 2023-02-02 | Micron Technology, Inc. | Fast bit erase for upper tail tightening of threshold voltage distributions |
US20230032500A1 (en) * | 2012-06-06 | 2023-02-02 | Kioxia Corporation | Semiconductor storage device and controller |
TWI817353B (en) * | 2021-08-18 | 2023-10-01 | 日商鎧俠股份有限公司 | semiconductor memory device |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012069205A (en) | 2010-09-22 | 2012-04-05 | Toshiba Corp | Nonvolatile semiconductor memory |
US20140036565A1 (en) * | 2012-08-02 | 2014-02-06 | Nanya Technology Corporation | Memory device and method of manufacturing memory structure |
KR20140076097A (en) * | 2012-12-12 | 2014-06-20 | 에스케이하이닉스 주식회사 | Resistive memory device and manufacturing method of the same |
JP2014235757A (en) * | 2013-05-30 | 2014-12-15 | 株式会社東芝 | Controller |
US9299391B2 (en) | 2014-01-21 | 2016-03-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Three-dimensional wordline sharing memory |
JP2015176627A (en) | 2014-03-17 | 2015-10-05 | 株式会社東芝 | semiconductor memory device |
US9620217B2 (en) * | 2014-08-12 | 2017-04-11 | Macronix International Co., Ltd. | Sub-block erase |
US10283171B2 (en) | 2015-03-30 | 2019-05-07 | Taiwan Semicondutor Manufacturing Company, Ltd. | Stacked die semiconductor device with separate bit line and bit line bar interconnect structures |
US20170117036A1 (en) * | 2015-10-22 | 2017-04-27 | Sandisk Technologies Llc | Source line driver for three dimensional non-volatile memory |
US9711229B1 (en) * | 2016-08-24 | 2017-07-18 | Sandisk Technologies Llc | 3D NAND with partial block erase |
US10566059B2 (en) * | 2018-04-30 | 2020-02-18 | Sandisk Technologies Llc | Three dimensional NAND memory device with drain select gate electrode shared between multiple strings |
JP2022142226A (en) | 2021-03-16 | 2022-09-30 | キオクシア株式会社 | semiconductor storage device |
Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007266143A (en) | 2006-03-27 | 2007-10-11 | Toshiba Corp | Non-volatile semiconductor memory device and manufacturing method therefor |
US20080310230A1 (en) | 2007-06-12 | 2008-12-18 | Samsung Electronics Co., Ltd. | Flash Memory Devices Having Three Dimensional Stack Structures and Methods of Driving Same |
JP2009146954A (en) | 2007-12-11 | 2009-07-02 | Toshiba Corp | Non-volatile semiconductor storage device |
US20100038703A1 (en) | 2008-08-12 | 2010-02-18 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor storage device |
US20100118610A1 (en) | 2008-11-13 | 2010-05-13 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
US20100172189A1 (en) | 2009-01-08 | 2010-07-08 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor storage device |
US20110051527A1 (en) | 2009-09-01 | 2011-03-03 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
US8107286B2 (en) * | 2009-09-18 | 2012-01-31 | Kabushiki Kaisha Toshiba | Three-dimensional nonvolatile semiconductor memory device for curbing a leak current and method of data read therein |
US20120069663A1 (en) | 2010-09-22 | 2012-03-22 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
US8194467B2 (en) * | 2009-09-16 | 2012-06-05 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
US8199584B2 (en) * | 2008-07-04 | 2012-06-12 | Samsung Electronics Co., Ltd. | Nonvolatile memory device for preventing program disturbance and method of programming the nonvolatile memory device |
US8339856B2 (en) * | 2009-12-28 | 2012-12-25 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device and semiconductor device |
US8488378B2 (en) * | 2011-03-25 | 2013-07-16 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
US8599610B2 (en) * | 2011-03-17 | 2013-12-03 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor storage device having a control circuit configured to execute a read operation |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11177071A (en) * | 1997-12-11 | 1999-07-02 | Toshiba Corp | Nonvolatile semiconductor storage device |
JP4287222B2 (en) * | 2003-09-03 | 2009-07-01 | 株式会社東芝 | Nonvolatile semiconductor memory device |
JP2010118580A (en) * | 2008-11-14 | 2010-05-27 | Toshiba Corp | Non-volatile semiconductor memory device |
JP2011198435A (en) * | 2010-03-23 | 2011-10-06 | Toshiba Corp | Nonvolatile semiconductor memory device |
JP2012203969A (en) * | 2011-03-25 | 2012-10-22 | Toshiba Corp | Nonvolatile semiconductor memory device |
US8665652B2 (en) * | 2011-06-24 | 2014-03-04 | Macronix International Co., Ltd. | Method for erasing memory array |
JP2013058276A (en) * | 2011-09-07 | 2013-03-28 | Toshiba Corp | Semiconductor memory device |
-
2011
- 2011-06-14 JP JP2011132424A patent/JP5524134B2/en active Active
-
2012
- 2012-06-11 US US13/493,370 patent/US8817538B2/en active Active
-
2014
- 2014-07-23 US US14/338,975 patent/US20140334231A1/en not_active Abandoned
Patent Citations (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007266143A (en) | 2006-03-27 | 2007-10-11 | Toshiba Corp | Non-volatile semiconductor memory device and manufacturing method therefor |
US20070252201A1 (en) | 2006-03-27 | 2007-11-01 | Masaru Kito | Nonvolatile semiconductor memory device and manufacturing method thereof |
US20110284947A1 (en) | 2006-03-27 | 2011-11-24 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and manufacturing method thereof |
US20110287597A1 (en) | 2006-03-27 | 2011-11-24 | Kabushiki Kaisha Toshiba | Nonvolatile semicondutor memory device and manufacturing method thereof |
US7936004B2 (en) | 2006-03-27 | 2011-05-03 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and manufacturing method thereof |
US20080310230A1 (en) | 2007-06-12 | 2008-12-18 | Samsung Electronics Co., Ltd. | Flash Memory Devices Having Three Dimensional Stack Structures and Methods of Driving Same |
JP2008310949A (en) | 2007-06-12 | 2008-12-25 | Samsung Electronics Co Ltd | Flash memory device having three-dimensional structure with improved driving system, and method of driving the same |
JP2009146954A (en) | 2007-12-11 | 2009-07-02 | Toshiba Corp | Non-volatile semiconductor storage device |
US20100207195A1 (en) | 2007-12-11 | 2010-08-19 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor storage device and method of manufacturing the same |
US8199584B2 (en) * | 2008-07-04 | 2012-06-12 | Samsung Electronics Co., Ltd. | Nonvolatile memory device for preventing program disturbance and method of programming the nonvolatile memory device |
JP2010045149A (en) | 2008-08-12 | 2010-02-25 | Toshiba Corp | Non-volatile semiconductor storage apparatus |
US20100038703A1 (en) | 2008-08-12 | 2010-02-18 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor storage device |
JP2010118530A (en) | 2008-11-13 | 2010-05-27 | Toshiba Corp | Nonvolatile semiconductor memory device |
US20100118610A1 (en) | 2008-11-13 | 2010-05-13 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
US20100172189A1 (en) | 2009-01-08 | 2010-07-08 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor storage device |
JP2010161199A (en) | 2009-01-08 | 2010-07-22 | Toshiba Corp | Non-volatile semiconductor memory device |
US20110051527A1 (en) | 2009-09-01 | 2011-03-03 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
US8320182B2 (en) * | 2009-09-01 | 2012-11-27 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
US8194467B2 (en) * | 2009-09-16 | 2012-06-05 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
US8107286B2 (en) * | 2009-09-18 | 2012-01-31 | Kabushiki Kaisha Toshiba | Three-dimensional nonvolatile semiconductor memory device for curbing a leak current and method of data read therein |
US8339856B2 (en) * | 2009-12-28 | 2012-12-25 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device and semiconductor device |
US20120069663A1 (en) | 2010-09-22 | 2012-03-22 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
US8514627B2 (en) * | 2010-09-22 | 2013-08-20 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
US8599610B2 (en) * | 2011-03-17 | 2013-12-03 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor storage device having a control circuit configured to execute a read operation |
US8488378B2 (en) * | 2011-03-25 | 2013-07-16 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
Cited By (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10229741B2 (en) | 2010-11-29 | 2019-03-12 | Toshiba Memory Corporation | Nonvolatile semiconductor memory device |
US9953713B2 (en) | 2010-11-29 | 2018-04-24 | Toshiba Memory Corporation | Nonvolatile semiconductor memory device |
US11062778B2 (en) | 2010-11-29 | 2021-07-13 | Toshiba Memory Corporation | Nonvolatile semiconductor memory device |
US9159431B2 (en) * | 2010-11-29 | 2015-10-13 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
US9484105B2 (en) | 2010-11-29 | 2016-11-01 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
US9595337B2 (en) | 2010-11-29 | 2017-03-14 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
US9747988B2 (en) | 2010-11-29 | 2017-08-29 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
US20150009755A1 (en) * | 2010-11-29 | 2015-01-08 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
US9852797B2 (en) | 2010-11-29 | 2017-12-26 | Toshiba Memory Corporation | Nonvolatile semiconductor memory device |
US10460812B2 (en) | 2010-11-29 | 2019-10-29 | Toshiba Memory Corporation | Nonvolatile semiconductor memory device |
US10714188B2 (en) | 2010-11-29 | 2020-07-14 | Toshiba Memory Corporation | Nonvolatile semiconductor memory device |
US10090054B2 (en) | 2010-11-29 | 2018-10-02 | Toshiba Memory Corporation | Nonvolatile semiconductor memory device |
US11908525B2 (en) | 2010-11-29 | 2024-02-20 | Kioxia Corporation | Nonvolatile semiconductor memory device |
US11967833B2 (en) | 2010-11-29 | 2024-04-23 | Kioxia Corporation | Nonvolatile semiconductor memory device |
US11923012B2 (en) * | 2012-06-06 | 2024-03-05 | Kioxia Corporation | Semiconductor storage device and controller |
US20230032500A1 (en) * | 2012-06-06 | 2023-02-02 | Kioxia Corporation | Semiconductor storage device and controller |
US8891306B2 (en) * | 2013-01-02 | 2014-11-18 | SK Hynix Inc. | Semiconductor memory device |
US20150036429A1 (en) * | 2013-07-30 | 2015-02-05 | SK Hynix Inc. | Semiconductor memory device |
US9799403B2 (en) * | 2014-03-14 | 2017-10-24 | Toshiba Memory Corporation | Semiconductor memory device |
US11270773B2 (en) | 2014-03-14 | 2022-03-08 | Kioxia Corporation | Semiconductor memory device |
US10854298B2 (en) | 2014-03-14 | 2020-12-01 | Toshiba Memory Corporation | Semiconductor memory device |
US11705204B2 (en) | 2014-03-14 | 2023-07-18 | Kioxia Corporation | Semiconductor memory device |
US10074434B2 (en) | 2014-03-14 | 2018-09-11 | Toshiba Memory Corporation | Semiconductor memory device |
US10381084B2 (en) | 2014-03-14 | 2019-08-13 | Toshiba Memory Corporation | Semiconductor memory device |
US20230034752A1 (en) * | 2021-07-21 | 2023-02-02 | Micron Technology, Inc. | Fast bit erase for upper tail tightening of threshold voltage distributions |
US11961566B2 (en) * | 2021-07-21 | 2024-04-16 | Micron Technology, Inc. | Fast bit erase for upper tail tightening of threshold voltage distributions |
TWI817353B (en) * | 2021-08-18 | 2023-10-01 | 日商鎧俠股份有限公司 | semiconductor memory device |
Also Published As
Publication number | Publication date |
---|---|
US20120320698A1 (en) | 2012-12-20 |
JP5524134B2 (en) | 2014-06-18 |
JP2013004127A (en) | 2013-01-07 |
US20140334231A1 (en) | 2014-11-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8817538B2 (en) | Nonvolatile semiconductor memory device and method for erasing data thereof | |
US9490019B2 (en) | Nonvolatile semiconductor memory device and data erase method thereof | |
US9437307B2 (en) | Nonvolatile semiconductor memory device | |
USRE45890E1 (en) | Nonvolatile semiconductor memory device | |
US11742032B2 (en) | Semiconductor memory device | |
USRE46957E1 (en) | Nonvolatile semiconductor memory device | |
US8107286B2 (en) | Three-dimensional nonvolatile semiconductor memory device for curbing a leak current and method of data read therein | |
US9460794B2 (en) | Nonvolatile semiconductor memory device | |
KR101020845B1 (en) | Nonvolatile semiconductor memory and method for driving the same | |
US20120069660A1 (en) | Nonvolatile semiconductor memory device | |
US8724391B2 (en) | Semiconductor memory device | |
US8724397B2 (en) | Non-volatile semiconductor memory device and method of reading data thereof | |
US8760925B2 (en) | Non-volatile semiconductor memory device | |
US8724383B2 (en) | Nonvolatile semiconductor memory device | |
US20130080718A1 (en) | Semiconductor memory device and method of operating the same | |
US8760924B2 (en) | Nonvolatile semiconductor memory device and method of data write therein |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: KABUSHIKI KAISHA TOSHIBA, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ITAGAKI, KIYOTARO;YAMADA, KUNIHIRO;IWATA, YOSHIHISA;SIGNING DATES FROM 20120530 TO 20120601;REEL/FRAME:028353/0840 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
AS | Assignment |
Owner name: TOSHIBA MEMORY CORPORATION, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KABUSHIKI KAISHA TOSHIBA;REEL/FRAME:043709/0035 Effective date: 20170706 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551) Year of fee payment: 4 |
|
AS | Assignment |
Owner name: K.K. PANGEA, JAPAN Free format text: MERGER;ASSIGNOR:TOSHIBA MEMORY CORPORATION;REEL/FRAME:055659/0471 Effective date: 20180801 Owner name: TOSHIBA MEMORY CORPORATION, JAPAN Free format text: CHANGE OF NAME AND ADDRESS;ASSIGNOR:K.K. PANGEA;REEL/FRAME:055669/0401 Effective date: 20180801 Owner name: KIOXIA CORPORATION, JAPAN Free format text: CHANGE OF NAME AND ADDRESS;ASSIGNOR:TOSHIBA MEMORY CORPORATION;REEL/FRAME:055669/0001 Effective date: 20191001 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |