US8773413B2 - Liquid crystal display panel, liquid crystal display device, and gate driving method of liquid crystal display panel - Google Patents

Liquid crystal display panel, liquid crystal display device, and gate driving method of liquid crystal display panel Download PDF

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US8773413B2
US8773413B2 US13/376,083 US201113376083A US8773413B2 US 8773413 B2 US8773413 B2 US 8773413B2 US 201113376083 A US201113376083 A US 201113376083A US 8773413 B2 US8773413 B2 US 8773413B2
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gate
circuit
switch circuit
signal
gout
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US20130063405A1 (en
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Xiufeng Zhou
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G09G2310/062—Waveforms for resetting a plurality of scan lines at a time

Definitions

  • the present invention relates to the field of liquid crystal displays (LCDs), and more particularly to a LCD panel, a LCD device, and a gate driving method of LCD panel.
  • LCDs liquid crystal displays
  • GOA gate on array
  • GIP TFT-LCD panel
  • the aim of the present invention is to provide a LCD panel, a LCD device, and a gate driving method of LCD panel capable of reducing the board area around a panel, reducing the Tact time of MOD Bonding, increasing the stability and reliability of the GOA circuits of the panel, and reducing the power consumption and delay of signals.
  • a LCD panel comprises multiple gate lines, and a gate drive circuit connected with the gate lines;
  • the gate drive circuit comprises multiple shift register units which are used for shifting signals to sequentially drive all the gate lines; each shift register unit comprises a former signal GOUT(n ⁇ 1) interface and a latter signal GOUT(n) interface which are connected with adjacent two gate lines; the GOUT(n) output by the GOUT(n) interface exceeds the GOUT(n ⁇ 1) output by the GOUT(n ⁇ 1) interface at one scanning interval.
  • the LCD panel also comprises a first switch circuit and a second switch circuit, and GOUT(n ⁇ 1) interface shares a common interface with the GOUT(n) interface.
  • a common signal output by the common interface is used as GOUT(n ⁇ 1) or GOUT(n) to be output to the corresponding gate line, and is connected to the other adjacent gate line through the first switch circuit.
  • An output interface is shared by the GOUT(n ⁇ 1) and the GOUT(n), and the output interval is controlled by the first switch circuit so that the circuit structure is simple.
  • the common signal output by the common interface is kept for two scanning intervals within one scanning period; and the first switch circuit is kept for one scanning interval.
  • This is a specific control mode of the GOUT(n ⁇ 1)/GOUT(n) output.
  • the GOUT(n ⁇ 1) is taken from the GOUT(n).
  • the GOUT(n) must be kept for more than two scanning intervals.
  • two scanning intervals are preferable.
  • the GOUT(n) output is kept for two scanning intervals, and the GOUT(n) exceeds the GOUT(n ⁇ 1) at one scanning interval.
  • the first switch circuit should be connected when a high-level signal is output by the GOUT(n) interface, and disconnected after being kept for one scanning interval.
  • the problem of undercharge may occur.
  • the GOUT(n) is kept for two scanning intervals within one scanning period, and the gate lines are pre-charged in the former scanning interval, to ensure a pixel to achieve the required potential within defined time.
  • the LCD panel also comprises a first switch circuit, and the GOUT(n) interface shares a common interface with the GOUT(n ⁇ 1) interface.
  • the common interface is used as a GOUT(n ⁇ 1) or GOUT(n) interface to output a signal to the corresponding gate line, and is connected to the other adjacent gate line by the first switch circuit; and the other adjacent gate line is connected to the reference low-level signal of the shift register unit by the second switch circuit.
  • the common signal is kept for two scanning intervals within one scanning period.
  • the first switch circuit and the second switch circuit are alternatively connected, and are connected for one scanning interval each time. This is the other specific control mode of the GOUT(n ⁇ 1)/GOUT(n) output. Take the common signal as GOUT(n ⁇ 1) for example, the GOUT(n ⁇ 1) is taken from the GOUT(n). To ensure that the GOUT(n) exceeds the GOUT(n ⁇ 1) at one scanning interval, the GOUT(n) must be kept for more than two scanning intervals. Thus, two scanning intervals are preferable.
  • the first switch circuit and the second switch circuit are respectively used for connecting and disconnecting the GOUT(n ⁇ 1).
  • the GOUT(n) output is kept for two scanning intervals, and the GOUT(n) exceeds the GOUT(n ⁇ 1) at one scanning interval. Therefore, the first switch circuit should be connected when a high-level signal is output by the GOUT(n) interface, and disconnected after being kept for one scanning interval. To ensure the reliability of actions, when the first switch circuit is disconnected, the second switch circuit is connected, and the GOUT(n ⁇ 1) is forcibly kept at a low-level position.
  • the common signal is output by the common interface through a third switch circuit, and the control ends of the second switch circuit and the third switch circuit are connected to the same control signal.
  • the third switch circuit can ensure that the scanning of the other gate line is in an off state when the current gate line is scanned.
  • the scanning interval of every two gate lines is guaranteed as one scanning interval, benefitting to keep the scanning consistency of gate lines and improve display quality.
  • the LCD panel also comprises an intensifier circuit; the intensifier circuit is connected to the other end of the gate line, and is matched with the gate drive circuit to simultaneously drive and scan the same gate line.
  • the intensifier circuit is added, and then the drive capability of each gate line is improved.
  • the structure of the intensifier circuit at the other end of the gate line is completely the same as that of the gate drive circuit at one end of the gate line. This is one specific embodiment of the intensifier circuit.
  • the intensifier circuit is a buffer circuit
  • the buffer circuit comprises multiple buffer units.
  • Each buffer unit comprises a fourth switch circuit and a fifth switch circuit which are in series connection.
  • the input end of the fourth switch circuit is connected with a gate line corresponding to the common signal
  • the output end of the fourth switch circuit is connected with a gate line corresponding to the output end of the first switch circuit, and is connected with a reference low-level signal of the intensifier circuit through the fifth switch circuit.
  • a same control signal is used by the fourth switch circuit and the first switch circuit.
  • a same control signal is used by the fifth switch circuit and the second switch circuit.
  • a LCD device wherein the LCD device comprises the aforementioned LCD panel.
  • a gate driving method of LCD panel comprising the following steps: selecting multiple shift register units which are used for shifting signals to sequentially drive all the gate lines; connecting each shift register unit with adjacent two gate lines; and outputting GOUT(n ⁇ 1) and GOUT(n) between which one scanning interval exists by each shift register unit to its corresponding adjacent two gate lines.
  • the GOUT(n) is kept for two scanning intervals.
  • the GOUT(n ⁇ 1) is connected with the GOUT(n) by the first switch circuit, and is connected with the Voff of the shift register unit by the second switch circuit.
  • the first switch circuit and the second switch circuit are alternatively connected, and are connected for one scanning interval each time.
  • each shift register unit can scan two gate lines.
  • N Gate line signals are output by only at least n/2+1 shift register units.
  • the circuit is greatly simplified; the RC distortion of input clock signals is reduced; the signal delay effect is greatly reduced; and the reliability and stability of circuits are increased. Meanwhile, on the premise of guaranteeing circuit drive, the GOA circuit is further simplified, and the space occupied by the circuit is further reduced.
  • FIG. 1 is a schematic diagram of a LCD panel of the present invention
  • FIG. 2 is a schematic diagram of a principle conception of the present invention
  • FIG. 3 is a functional block diagram of embodiment 1 of the present invention.
  • FIG. 4 is a functional block diagram of embodiment 2 of the present invention.
  • FIG. 5 is a waveform diagram of the input and output signals of embodiment 2 of the present invention.
  • FIG. 6 is a functional block diagram of embodiment 3 of the present invention.
  • FIG. 7 is a waveform diagram of the input and output signals of embodiment 3 of the present invention.
  • FIG. 8 is a schematic diagram of a LCD panel of embodiment 4 of the present invention.
  • FIG. 9 is a principle diagram of embodiment 4 of the present invention.
  • FIG. 10 is a principle diagram of a buffer unit of embodiment 4 of the present invention.
  • 1 LCD panel; 2 . gate drive circuit; 21 . shift register unit; 3 . liquid crystal drive IC (COF); 4 . first switch circuit; 5 . second switch circuit; 6 . third switch circuit; 7 . intensifier circuit; 8 . buffer unit; 81 . fourth switch circuit; 82 . fifth switch circuit.
  • 1 LCD panel
  • 2 gate drive circuit
  • 21 shift register unit
  • 3 liquid crystal drive IC (COF)
  • 4 first switch circuit
  • 5 second switch circuit
  • 6 third switch circuit
  • 7 intensifier circuit
  • 8 buffer unit
  • a LCD device comprises a LCD panel.
  • the LCD panel 1 comprises multiple gate lines and data lines (arranged on the LCD panel 1 and not shown in the figure), a gate drive circuit 2 connected with the gate lines, and liquid crystal drive ICs (COF) 3 connected with the data lines.
  • the gate drive circuit 2 comprises multiple shift register units 21 .
  • Each shift register unit 21 comprises a GOUT(n ⁇ 1) interface and a GOUT(n) interface which are connected with adjacent two gate lines; the GOUT(n) output by the GOUT(n) interface exceeds the GOUT(n ⁇ 1) output by the GOUT(n ⁇ 1) interface at one scanning interval.
  • the scanning interval refers to the average scanning time of all gate lines within one scanning period.
  • Embodiment 1 as shown in FIG. 3 , the GOUT(n ⁇ 1) interface shares a common interface with the GOUT(n) interface. A common signal output by the common interface is used as GOUT(n ⁇ 1) or GOUT(n) to be output to the corresponding gate line, and is connected to the other adjacent gate line through a first switch circuit 4 .
  • the common signal output by the common interface is kept for two scanning intervals within one scanning period, and the first switch circuit is kept for one scanning interval.
  • the common signal Take the common signal as GOUT(n) for example, the GOUT(n ⁇ 1) is taken from the GOUT(n).
  • the GOUT(n) must be kept for more than two scanning intervals. Thus, two scanning intervals are preferable.
  • the GOUT(n) output is kept for two scanning intervals, and the GOUT(n) exceeds the GOUT(n ⁇ 1) at one scanning interval. Therefore, the first switch circuit 4 should be connected when a high-level signal is output by the GOUT(n) interface, and disconnected after being kept for one scanning interval.
  • An output interface is shared by the GOUT(n) and the GOUT(n ⁇ 1), and the output interval is controlled by the first switch circuit 4 so that the circuit structure is simple.
  • Embodiment 2 as shown in FIG. 4 and FIG. 5 , a common interface is shared by the GOUT(n ⁇ 1) interface and the GOUT(n) interface.
  • the common interface is used as a GOUT(n ⁇ 1) interface or a GOUT(n) interface to output a signal to the corresponding gate line, and is connected to the other adjacent gate line by the first switch circuit 4 ; and the other adjacent gate line is connected to the reference low-level signal Voff of the shift register unit 21 by the second switch circuit 5 .
  • the common signal is kept for two scanning intervals within one scanning period.
  • the first switch circuit 4 and the second switch circuit 5 are alternatively connected, and are connected for one scanning interval each time. Take the common signal as GOUT(n) for example:
  • the GOUT(n ⁇ 1) is taken from the GOUT(n). To ensure that the GOUT(n) exceeds the GOUT(n ⁇ 1) at one scanning interval, the GOUT(n) must be kept for more than two scanning intervals. Thus, two scanning intervals are preferable.
  • the first switch circuit 4 and the second switch circuit 5 are respectively used for controlling the connection and the disconnection of the GOUT(n ⁇ 1).
  • the GOUT(n) output is kept for two scanning intervals.
  • the GOUT(n) exceeds the GOUT(n ⁇ 1) at one scanning interval. Therefore, the first switch circuit 4 should be connected when a high-level signal is output by the GOUT(n) interface, and is disconnected after being kept for one scanning interval.
  • the GOUT(n ⁇ 1) is forcibly kept at a low-level position.
  • the problem of undercharge may occur. Therefore, corresponding gate lines should be pre-charged to ensure a pixel to achieve the required potential within defined time.
  • the GOUT(n) exceeds the GOUT(n ⁇ 1) at one scanning interval, and the signal output is kept in one scanning interval when the GOUT(n ⁇ 1) is output to pre-charge the corresponding gate line. Therefore, the GOUT(n) is kept for two scanning intervals within one scanning period.
  • the first switch circuit 4 is a switch tube T 15
  • the second switch circuit 5 is a switch tube T 16
  • a chip select (CS) STV is externally provided by the circuit to control clock signals (CLK 1 ,CLK 2 ,CLK 3 ,CLK 4 ), and the reference low-level signal Voff of the shift register unit 21 .
  • the GOUT(n), the STV(n) of the following shift register unit 21 and the GOUT(n ⁇ 1) are output through the aforementioned function modules.
  • the switch tube T 1 and the switch tube T 15 are pull-up units and output the GOUT(n) and GOUT(n ⁇ 1)
  • the switch tube T 4 is a carry unit and outputs STV(n+2).
  • Switch tubes T 2 , T 6 , T 7 , T 8 , T 9 and T 11 are holding units, and hold the Gate out output to the required potential; switch tubes T 3 , T 5 , T 12 , T 13 and T 16 are discharge units, and pull down high potential to low potential; and a switch tube T 14 is a discharge reset unit.
  • the current shift register unit 21 accepts the CS STV(n) of the former shift register unit 21 . Only after the STV(n) is accepted, the output of the current shift register unit 21 is controlled. If the current shift register unit 21 is the first shift register unit 21 , its STV(n) comes from an external enable pulse STVP. After the current shift register unit 21 is started, the level switch of the scanning signal GOUT(n) is controlled by CLK 1 and CLK 2 , the GOUT(n ⁇ 1) level switch is controlled by CLK 3 and CLK 4 , and a reference low level is provided by Voff. Reset provides a reset signal, the high level is effective, and the data of all the shift register units are cleared.
  • a CS STV(n+2) of the following shift register unit 21 is produced; the following shift register unit 21 responds to CLK 1 to CLK 4 after starting; the GOUT(n+1) is fed back to the former shift register unit 21 when the current gate line is driven; the former shift register unit 21 is cleared and reset; and the former shift register unit 21 does not respond to the clock signals before the next STV(n) is produced.
  • Embodiment 3 as shown in FIG. 6 , the common signal is output by the common interface through a third switch circuit 6 ; and the control ends of the second switch circuit 5 and the third switch circuit 6 are connected to the same control signal.
  • the embodiment can be used in the technical schemes of the aforementioned embodiment 1 and embodiment 2.
  • the GOUT(n) is kept for two scanning intervals, and the control end of the first switch circuit 4 is connected to the CLK 3 .
  • the control ends of the second switch circuit 5 and the third switch circuit 6 are connected to the CLK 4 , and the first switch circuit 4 and the second switch circuit 5 are alternatively connected, and are connected for one scanning interval each time.
  • the first switch circuit 4 is connected when a high-level signal is output by the GOUT(n) interface.
  • the output time of either the GOUT(n ⁇ 1) or the GOUT(n) is one scanning interval.
  • the equal scanning interval benefits to guarantee display consistency, and the preferable display quality of the LCD panel 1 .
  • Embodiment 4 to preferably increase the speed of circuit charge and discharge, a design of drive of double sides is used; an intensifier circuit 7 on the left side may be designed with the same circuit structure as that of the gate drive circuit on the right side to improve the circuit drive capability; alternatively, the intensifier circuit 7 on the left side may be only designed into a buffer circuit for charge and discharge to improve the circuit drive capability.
  • the LCD panel 1 also comprises an intensifier circuit 7 .
  • the intensifier circuit 7 is connected to the other end of the gate line, and is matched with the gate drive circuit 2 to simultaneously drive and scan the same gate line.
  • the embodiment can be used in any one of the technical schemes of the aforementioned embodiment 1 to embodiment 3. To simplify description, take the application of embodiment 2 as an example to further describe the technical scheme:
  • the intensifier circuit 7 comprises multiple buffer units 8 .
  • Each buffer unit 8 comprises a fourth switch circuit 81 and a fifth switch circuit 82 which are in series connection.
  • the input end of the fourth switch circuit 81 is connected with a gate line corresponding to the common signal, and the output end of the fourth switch circuit 81 is connected with a gate line corresponding to the output end of the first switch circuit 4 , and is connected with a reference low-level signal VGL of the intensifier circuit 7 through the fifth switch circuit 82 .
  • a same control signal is used by the fourth switch circuit 81 and the first switch circuit 4 , namely the CLK 3 ; and a same control signal is used by the fifth switch circuit 82 and the second switch circuit 5 , namely the CLK 4 .
  • the intensifier circuit 7 can simultaneously drive the corresponding gate line from the other end when driving the gate line from one end, so that the scanning drive capability of the gate line is enhanced.
  • the left side and the right side of a circuit are simultaneously charged and discharged; the response speed of the circuit is rapidly increased; and the panel image quality uniformity is improved.
  • the conception of the present invention is not limited to the aforementioned embodiments, all the intensifier circuits which are connected to the other end of each gate line, matched with the gate drive circuit, and used for synchronously driving and scanning the same gate line should be considered to belong to the protection scope of the present invention.
  • a gate driving method of LCD panel which is used by the aforementioned LCD panel, comprising the following steps: selecting multiple shift register units which are used for shifting signals to sequentially drive all gate lines; connecting each shift register unit with adjacent two gate lines; and outputting GOUT(n ⁇ 1) and GOUT(n)1 between which one scanning interval exists by each shift register unit to its corresponding adjacent two gate lines.
  • the GOUT(n) is kept for two scanning intervals.
  • the GOUT(n ⁇ 1) is connected with the GOUT(n) by the first switch circuit, and is connected with the reference low-level signal Voff of the shift register unit by the second switch circuit.
  • the first switch circuit and the second switch circuit are alternatively connected, and are connected for one scanning interval each time.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Shift Register Type Memory (AREA)

Abstract

An LCD panel includes multiple gate lines, and a gate drive circuit connected with the gate lines. The gate drive circuit includes multiple shift register units which are used for outputting shifting signals to sequentially drive all gate lines; each shift register unit includes a first output interface and a second output interface which are connected with adjacent two gate lines. The first output interface outputs a first gate signal, the second output interface outputs a second gate signal; and a duration of the second gate signal is two times of a duration of the first gate signal in a scanning period.

Description

TECHNICAL FIELD
The present invention relates to the field of liquid crystal displays (LCDs), and more particularly to a LCD panel, a LCD device, and a gate driving method of LCD panel.
BACKGROUND
It is well-known that the technique of gate on array (GOA)/gate in TFT-LCD panel (GIP) can reduce integrated circuit (IC) cost, reduce the board area around a panel, and reduce the Tact time of MOD Bonding. However, the stability, the reliability, the power consumption, etc. of the complicated GOA circuits of the panel become problems which are difficult to solve for designers. One gate line signal is output by a general GOA circuit through at least one shift register unit. Thus, for n gate lines, more than n+1 shift register units are required to form a completed circuit loop structure. Because external CLK and VGL lines enter the more than n+1 shift register units simultaneously in accordance with requirements, the power consumption and delay of signals become more serious.
SUMMARY
The aim of the present invention is to provide a LCD panel, a LCD device, and a gate driving method of LCD panel capable of reducing the board area around a panel, reducing the Tact time of MOD Bonding, increasing the stability and reliability of the GOA circuits of the panel, and reducing the power consumption and delay of signals.
The purpose of the present invention is achieved by the following technical schemes.
A LCD panel comprises multiple gate lines, and a gate drive circuit connected with the gate lines; the gate drive circuit comprises multiple shift register units which are used for shifting signals to sequentially drive all the gate lines; each shift register unit comprises a former signal GOUT(n−1) interface and a latter signal GOUT(n) interface which are connected with adjacent two gate lines; the GOUT(n) output by the GOUT(n) interface exceeds the GOUT(n−1) output by the GOUT(n−1) interface at one scanning interval.
Preferably, the LCD panel also comprises a first switch circuit and a second switch circuit, and GOUT(n−1) interface shares a common interface with the GOUT(n) interface. A common signal output by the common interface is used as GOUT(n−1) or GOUT(n) to be output to the corresponding gate line, and is connected to the other adjacent gate line through the first switch circuit. This is a specific embodiment of the present invention. An output interface is shared by the GOUT(n−1) and the GOUT(n), and the output interval is controlled by the first switch circuit so that the circuit structure is simple.
Preferably, the common signal output by the common interface is kept for two scanning intervals within one scanning period; and the first switch circuit is kept for one scanning interval. This is a specific control mode of the GOUT(n−1)/GOUT(n) output. Take the common signal as GOUT(n) for example, the GOUT(n−1) is taken from the GOUT(n). To ensure that the GOUT(n) exceeds the GOUT(n−1) at one scanning interval, the GOUT(n) must be kept for more than two scanning intervals. Thus, two scanning intervals are preferable. The GOUT(n) output is kept for two scanning intervals, and the GOUT(n) exceeds the GOUT(n−1) at one scanning interval. Therefore, the first switch circuit should be connected when a high-level signal is output by the GOUT(n) interface, and disconnected after being kept for one scanning interval. In addition, in the application of a large panel, the problem of undercharge may occur. The GOUT(n) is kept for two scanning intervals within one scanning period, and the gate lines are pre-charged in the former scanning interval, to ensure a pixel to achieve the required potential within defined time.
Preferably, the LCD panel also comprises a first switch circuit, and the GOUT(n) interface shares a common interface with the GOUT(n−1) interface. The common interface is used as a GOUT(n−1) or GOUT(n) interface to output a signal to the corresponding gate line, and is connected to the other adjacent gate line by the first switch circuit; and the other adjacent gate line is connected to the reference low-level signal of the shift register unit by the second switch circuit. This is the other embodiment of the present invention. The reliability becomes higher because the output interval of the common signal output to the other gate line is controlled by two switch circuits.
Preferably, the common signal is kept for two scanning intervals within one scanning period. The first switch circuit and the second switch circuit are alternatively connected, and are connected for one scanning interval each time. This is the other specific control mode of the GOUT(n−1)/GOUT(n) output. Take the common signal as GOUT(n−1) for example, the GOUT(n−1) is taken from the GOUT(n). To ensure that the GOUT(n) exceeds the GOUT(n−1) at one scanning interval, the GOUT(n) must be kept for more than two scanning intervals. Thus, two scanning intervals are preferable. The first switch circuit and the second switch circuit are respectively used for connecting and disconnecting the GOUT(n−1). The GOUT(n) output is kept for two scanning intervals, and the GOUT(n) exceeds the GOUT(n−1) at one scanning interval. Therefore, the first switch circuit should be connected when a high-level signal is output by the GOUT(n) interface, and disconnected after being kept for one scanning interval. To ensure the reliability of actions, when the first switch circuit is disconnected, the second switch circuit is connected, and the GOUT(n−1) is forcibly kept at a low-level position.
Preferably, the common signal is output by the common interface through a third switch circuit, and the control ends of the second switch circuit and the third switch circuit are connected to the same control signal. The third switch circuit can ensure that the scanning of the other gate line is in an off state when the current gate line is scanned. Thus, the scanning interval of every two gate lines is guaranteed as one scanning interval, benefitting to keep the scanning consistency of gate lines and improve display quality.
Preferably, the LCD panel also comprises an intensifier circuit; the intensifier circuit is connected to the other end of the gate line, and is matched with the gate drive circuit to simultaneously drive and scan the same gate line. The intensifier circuit is added, and then the drive capability of each gate line is improved.
Preferably, the structure of the intensifier circuit at the other end of the gate line is completely the same as that of the gate drive circuit at one end of the gate line. This is one specific embodiment of the intensifier circuit.
Preferably, the intensifier circuit is a buffer circuit, and the buffer circuit comprises multiple buffer units. Each buffer unit comprises a fourth switch circuit and a fifth switch circuit which are in series connection. The input end of the fourth switch circuit is connected with a gate line corresponding to the common signal, and the output end of the fourth switch circuit is connected with a gate line corresponding to the output end of the first switch circuit, and is connected with a reference low-level signal of the intensifier circuit through the fifth switch circuit. A same control signal is used by the fourth switch circuit and the first switch circuit. A same control signal is used by the fifth switch circuit and the second switch circuit. This is the other specific embodiment of the intensifier circuit so that the circuit has simple structure and low cost.
A LCD device, wherein the LCD device comprises the aforementioned LCD panel.
A gate driving method of LCD panel, comprising the following steps: selecting multiple shift register units which are used for shifting signals to sequentially drive all the gate lines; connecting each shift register unit with adjacent two gate lines; and outputting GOUT(n−1) and GOUT(n) between which one scanning interval exists by each shift register unit to its corresponding adjacent two gate lines.
Preferably, the GOUT(n) is kept for two scanning intervals. The GOUT(n−1) is connected with the GOUT(n) by the first switch circuit, and is connected with the Voff of the shift register unit by the second switch circuit. The first switch circuit and the second switch circuit are alternatively connected, and are connected for one scanning interval each time.
In the present invention, each shift register unit can scan two gate lines. N Gate line signals are output by only at least n/2+1 shift register units. The circuit is greatly simplified; the RC distortion of input clock signals is reduced; the signal delay effect is greatly reduced; and the reliability and stability of circuits are increased. Meanwhile, on the premise of guaranteeing circuit drive, the GOA circuit is further simplified, and the space occupied by the circuit is further reduced.
BRIEF DESCRIPTION OF FIGURES
FIG. 1 is a schematic diagram of a LCD panel of the present invention;
FIG. 2 is a schematic diagram of a principle conception of the present invention;
FIG. 3 is a functional block diagram of embodiment 1 of the present invention;
FIG. 4 is a functional block diagram of embodiment 2 of the present invention;
FIG. 5 is a waveform diagram of the input and output signals of embodiment 2 of the present invention;
FIG. 6 is a functional block diagram of embodiment 3 of the present invention;
FIG. 7 is a waveform diagram of the input and output signals of embodiment 3 of the present invention;
FIG. 8 is a schematic diagram of a LCD panel of embodiment 4 of the present invention;
FIG. 9 is a principle diagram of embodiment 4 of the present invention; and
FIG. 10 is a principle diagram of a buffer unit of embodiment 4 of the present invention.
Wherein: 1. LCD panel; 2. gate drive circuit; 21. shift register unit; 3. liquid crystal drive IC (COF); 4. first switch circuit; 5. second switch circuit; 6. third switch circuit; 7. intensifier circuit; 8. buffer unit; 81. fourth switch circuit; 82. fifth switch circuit.
DETAILED DESCRIPTION
The present invention will further be described in detail in accordance with the figures and the preferred embodiments.
A LCD device comprises a LCD panel. As shown in FIG. 1 and FIG. 2, the LCD panel 1 comprises multiple gate lines and data lines (arranged on the LCD panel 1 and not shown in the figure), a gate drive circuit 2 connected with the gate lines, and liquid crystal drive ICs (COF) 3 connected with the data lines. The gate drive circuit 2 comprises multiple shift register units 21. Each shift register unit 21 comprises a GOUT(n−1) interface and a GOUT(n) interface which are connected with adjacent two gate lines; the GOUT(n) output by the GOUT(n) interface exceeds the GOUT(n−1) output by the GOUT(n−1) interface at one scanning interval. The scanning interval refers to the average scanning time of all gate lines within one scanning period. The invention will further be described in detail in accordance the embodiments.
Embodiment 1: as shown in FIG. 3, the GOUT(n−1) interface shares a common interface with the GOUT(n) interface. A common signal output by the common interface is used as GOUT(n−1) or GOUT(n) to be output to the corresponding gate line, and is connected to the other adjacent gate line through a first switch circuit 4.
The common signal output by the common interface is kept for two scanning intervals within one scanning period, and the first switch circuit is kept for one scanning interval. Take the common signal as GOUT(n) for example, the GOUT(n−1) is taken from the GOUT(n). To ensure that the GOUT(n) exceeds the GOUT(n−1) at one scanning interval, the GOUT(n) must be kept for more than two scanning intervals. Thus, two scanning intervals are preferable. The GOUT(n) output is kept for two scanning intervals, and the GOUT(n) exceeds the GOUT(n−1) at one scanning interval. Therefore, the first switch circuit 4 should be connected when a high-level signal is output by the GOUT(n) interface, and disconnected after being kept for one scanning interval.
An output interface is shared by the GOUT(n) and the GOUT(n−1), and the output interval is controlled by the first switch circuit 4 so that the circuit structure is simple.
Embodiment 2: as shown in FIG. 4 and FIG. 5, a common interface is shared by the GOUT(n−1) interface and the GOUT(n) interface. The common interface is used as a GOUT(n−1) interface or a GOUT(n) interface to output a signal to the corresponding gate line, and is connected to the other adjacent gate line by the first switch circuit 4; and the other adjacent gate line is connected to the reference low-level signal Voff of the shift register unit 21 by the second switch circuit 5. The common signal is kept for two scanning intervals within one scanning period. The first switch circuit 4 and the second switch circuit 5 are alternatively connected, and are connected for one scanning interval each time. Take the common signal as GOUT(n) for example:
The GOUT(n−1) is taken from the GOUT(n). To ensure that the GOUT(n) exceeds the GOUT(n−1) at one scanning interval, the GOUT(n) must be kept for more than two scanning intervals. Thus, two scanning intervals are preferable. The first switch circuit 4 and the second switch circuit 5 are respectively used for controlling the connection and the disconnection of the GOUT(n−1). The GOUT(n) output is kept for two scanning intervals. The GOUT(n) exceeds the GOUT(n−1) at one scanning interval. Therefore, the first switch circuit 4 should be connected when a high-level signal is output by the GOUT(n) interface, and is disconnected after being kept for one scanning interval. To ensure the reliability of actions, when the first switch circuit 4 is disconnected, the second switch circuit 5 is connected, and the GOUT(n−1) is forcibly kept at a low-level position. In the application of a large panel, the problem of undercharge may occur. Therefore, corresponding gate lines should be pre-charged to ensure a pixel to achieve the required potential within defined time. The GOUT(n) exceeds the GOUT(n−1) at one scanning interval, and the signal output is kept in one scanning interval when the GOUT(n−1) is output to pre-charge the corresponding gate line. Therefore, the GOUT(n) is kept for two scanning intervals within one scanning period.
As shown in the functional block diagram of FIG. 4: the first switch circuit 4 is a switch tube T15, and the second switch circuit 5 is a switch tube T16. A chip select (CS) STV is externally provided by the circuit to control clock signals (CLK1,CLK2,CLK3,CLK4), and the reference low-level signal Voff of the shift register unit 21. The GOUT(n), the STV(n) of the following shift register unit 21 and the GOUT(n−1) are output through the aforementioned function modules. The switch tube T1 and the switch tube T15 are pull-up units and output the GOUT(n) and GOUT(n−1), and the switch tube T4 is a carry unit and outputs STV(n+2). Switch tubes T2, T6, T7, T8, T9 and T11 are holding units, and hold the Gate out output to the required potential; switch tubes T3, T5, T12, T13 and T16 are discharge units, and pull down high potential to low potential; and a switch tube T14 is a discharge reset unit.
The current shift register unit 21 accepts the CS STV(n) of the former shift register unit 21. Only after the STV(n) is accepted, the output of the current shift register unit 21 is controlled. If the current shift register unit 21 is the first shift register unit 21, its STV(n) comes from an external enable pulse STVP. After the current shift register unit 21 is started, the level switch of the scanning signal GOUT(n) is controlled by CLK1 and CLK2, the GOUT(n−1) level switch is controlled by CLK3 and CLK4, and a reference low level is provided by Voff. Reset provides a reset signal, the high level is effective, and the data of all the shift register units are cleared. After the current shift register unit 21 drives the current gate line, a CS STV(n+2) of the following shift register unit 21 is produced; the following shift register unit 21 responds to CLK1 to CLK4 after starting; the GOUT(n+1) is fed back to the former shift register unit 21 when the current gate line is driven; the former shift register unit 21 is cleared and reset; and the former shift register unit 21 does not respond to the clock signals before the next STV(n) is produced.
This is the other embodiment of the present invention. The reliability becomes higher because the output interval of the common signal output to the other gate line is controlled by two switch circuits.
Embodiment 3: as shown in FIG. 6, the common signal is output by the common interface through a third switch circuit 6; and the control ends of the second switch circuit 5 and the third switch circuit 6 are connected to the same control signal. The embodiment can be used in the technical schemes of the aforementioned embodiment 1 and embodiment 2. To simplify description, take the application of embodiment 2 as an example to further describe the technical scheme: take the common signal as GOUT(n) for example, the GOUT(n) is output by the common interface through the third switch circuit 6. The GOUT(n) is kept for two scanning intervals, and the control end of the first switch circuit 4 is connected to the CLK3. The control ends of the second switch circuit 5 and the third switch circuit 6 are connected to the CLK4, and the first switch circuit 4 and the second switch circuit 5 are alternatively connected, and are connected for one scanning interval each time. The first switch circuit 4 is connected when a high-level signal is output by the GOUT(n) interface.
As shown in FIG. 7, because the control ends of the second switch circuit 5 and the third switch circuit 6 are connected to the CLK4, when the GOUT(n−1) is output, the GOUT(n) output is in an off state. When the GOUT(n−1) is disconnected, the third switch circuit 6 is connected, and the GOUT(n) is output. Therefore, the output time of either the GOUT(n−1) or the GOUT(n) is one scanning interval. The equal scanning interval benefits to guarantee display consistency, and the preferable display quality of the LCD panel 1.
Embodiment 4: to preferably increase the speed of circuit charge and discharge, a design of drive of double sides is used; an intensifier circuit 7 on the left side may be designed with the same circuit structure as that of the gate drive circuit on the right side to improve the circuit drive capability; alternatively, the intensifier circuit 7 on the left side may be only designed into a buffer circuit for charge and discharge to improve the circuit drive capability. As shown in FIG. 8, the LCD panel 1 also comprises an intensifier circuit 7. The intensifier circuit 7 is connected to the other end of the gate line, and is matched with the gate drive circuit 2 to simultaneously drive and scan the same gate line. The embodiment can be used in any one of the technical schemes of the aforementioned embodiment 1 to embodiment 3. To simplify description, take the application of embodiment 2 as an example to further describe the technical scheme:
The embodiment uses the buffer circuit solution as an example to explain; as shown in FIG. 9 and FIG. 10, the intensifier circuit 7 comprises multiple buffer units 8. Each buffer unit 8 comprises a fourth switch circuit 81 and a fifth switch circuit 82 which are in series connection. The input end of the fourth switch circuit 81 is connected with a gate line corresponding to the common signal, and the output end of the fourth switch circuit 81 is connected with a gate line corresponding to the output end of the first switch circuit 4, and is connected with a reference low-level signal VGL of the intensifier circuit 7 through the fifth switch circuit 82. A same control signal is used by the fourth switch circuit 81 and the first switch circuit 4, namely the CLK3; and a same control signal is used by the fifth switch circuit 82 and the second switch circuit 5, namely the CLK4. Thus, the intensifier circuit 7 can simultaneously drive the corresponding gate line from the other end when driving the gate line from one end, so that the scanning drive capability of the gate line is enhanced.
Through the circuit, the left side and the right side of a circuit are simultaneously charged and discharged; the response speed of the circuit is rapidly increased; and the panel image quality uniformity is improved. The conception of the present invention is not limited to the aforementioned embodiments, all the intensifier circuits which are connected to the other end of each gate line, matched with the gate drive circuit, and used for synchronously driving and scanning the same gate line should be considered to belong to the protection scope of the present invention.
A gate driving method of LCD panel which is used by the aforementioned LCD panel, comprising the following steps: selecting multiple shift register units which are used for shifting signals to sequentially drive all gate lines; connecting each shift register unit with adjacent two gate lines; and outputting GOUT(n−1) and GOUT(n)1 between which one scanning interval exists by each shift register unit to its corresponding adjacent two gate lines.
Furthermore, the GOUT(n) is kept for two scanning intervals. The GOUT(n−1) is connected with the GOUT(n) by the first switch circuit, and is connected with the reference low-level signal Voff of the shift register unit by the second switch circuit. The first switch circuit and the second switch circuit are alternatively connected, and are connected for one scanning interval each time.
The present invention is described in detail in accordance with the above contents with the specific preferred embodiments. However, this invention is not limited to the specific embodiments. For the ordinary technical personnel of the technical field of the present invention, on the premise of keeping the conception of the present invention, the technical personnel can also make simple deductions or replacements, and all of which should be considered to belong to the protection scope of the present invention.

Claims (10)

We claim:
1. A liquid crystal display (LCD) panel, comprising multiple gate lines, and a gate drive circuit connected with the gate lines; said gate drive circuit comprises multiple shift register units which are used for outputting shifting signals to sequentially drive all gate lines; each shift register unit comprises a first output interface and a second output interface which are connected with adjacent two gate lines; the first output interface outputting a first gate signal, the second output interface outputting a second gate signal; and a duration of the second gate signal is two times of a duration of the first gate signal in a scanning period; and
wherein said LCD panel also comprises a first switch circuit and a second switch circuit, and said first output interface shares a common interface with said second output interface; said common interface is used as a first output interface or second output interface to output the first or second gate signal to the corresponding gate line and is connected to the other gate line of the two adjacent gate lines via the first switch circuit; and the other gate line of the two adjacent gate lines is connected to a reference low-level signal of said shift register unit via a second switch circuit.
2. The LCD panel of claim 1, wherein when the common interface outputs the second gate signal, the second gate signal is kept for two scanning intervals within one scanning period; said first switch circuit and the second switch circuit are alternatively connected, and are connected for one scanning interval each time.
3. The LCD panel claim of 1, wherein said LCD panel also comprises an intensifier circuit; said intensifier circuit is connected to the other end of said gate lines, and is matched with said gate drive circuit to simultaneously drive and scan a same gate line.
4. The LCD panel of claim 3, wherein a structure of the intensifier circuit at the other end of said gate lines is completely the same as that of the gate drive circuit at one end of said gate lines.
5. The LCD panel of claim 1, wherein said LCD panel also comprises an intensifier circuit; said intensifier circuit is connected to the other end of said gate lines, and is matched with said gate drive circuit to simultaneously drive and scan a same gate line; said intensifier circuit is a buffer circuit, and said buffer circuit comprises multiple buffer units; each said buffer unit comprises a fourth switch circuit and a fifth switch circuit which are connected in series; an input end of said fourth switch circuit is connected with a gate line corresponding to said common signal; the output end of said fourth switch circuit is connected with a gate line corresponding to the output end of said first switch circuit, and is connected with a reference low-level signal of said intensifier circuit through the fifth switch circuit; a same control signal is used by said fourth switch circuit and said first switch circuit; a same control signal is used by said fifth switch circuit and said second switch circuit.
6. An LCD device, comprising: an LCD panel; said LCD panel comprises multiple gate lines, and a gate drive circuit connected with the gate lines; said gate drive circuit comprises multiple shift register units which are used for outputting shifting signals to sequentially drive all gate lines; each shift register unit comprises a first output interface and a second output interface which are connected with adjacent two gate lines; the first output interface outputting a first gate signal, the second output interface outputting a second gate signal; and a duration of the second gate signal is two times of a duration of the first gate signal in a scanning period; and
wherein said LCD panel also comprises a first switch circuit and a second switch circuit, and said first output interface shares a common interface with said second output interface; said common interface is used as a first output interface or second output interface to output the first or second gate signal to the corresponding gate line and is connected to the other gate line of the two adjacent gate lines via the first switch circuit; and the other gate line of the two adjacent gate lines is connected to a reference low-level signal of said shift register unit via a second switch circuit.
7. The LCD device of claim 6, wherein when the common interface outputs the second gate signal, the second gate signal is kept for two scanning intervals within one scanning period; said first switch circuit and the second switch circuit are alternatively connected, and are connected for one scanning interval each time.
8. The LCD device of claim of 6, wherein said LCD panel also comprises an intensifier circuit; said intensifier circuit is connected to the other end of said gate lines, and is matched with said gate drive circuit to simultaneously drive and scan a same gate line.
9. The LCD device of claim 8, wherein a structure of the intensifier circuit at the other end of said gate lines is completely the same as that of the gate drive circuit at one end of said gate lines.
10. The LCD device of claim 6, wherein said LCD panel also comprises an intensifier circuit; said intensifier circuit is connected to the other end of said gate lines, and is matched with said gate drive circuit to simultaneously drive and scan a same gate line; said intensifier circuit is a buffer circuit, and said buffer circuit comprises multiple buffer units; each said buffer unit comprises a fourth switch circuit and a fifth switch circuit which are connected in series; an input end of said fourth switch circuit is connected with a gate line corresponding to said common signal; the output end of said fourth switch circuit is connected with a gate line corresponding to the output end of said first switch circuit, and is connected with a reference low-level signal of said intensifier circuit through the fifth switch circuit; a same control signal is used by said fourth switch circuit and said first switch circuit; a same control signal is used by said fifth switch circuit and said second switch circuit.
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US9483993B2 (en) * 2014-12-31 2016-11-01 Shenzhen China Star Optoelectronics Technology Co., Ltd. Gate drive circuit

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