US8723323B2 - Method for fabricating solder columns for a column grid array package - Google Patents

Method for fabricating solder columns for a column grid array package Download PDF

Info

Publication number
US8723323B2
US8723323B2 US13/547,518 US201213547518A US8723323B2 US 8723323 B2 US8723323 B2 US 8723323B2 US 201213547518 A US201213547518 A US 201213547518A US 8723323 B2 US8723323 B2 US 8723323B2
Authority
US
United States
Prior art keywords
solder columns
package
tab
substrate
electronic devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US13/547,518
Other versions
US20140015098A1 (en
Inventor
Thomas J. McIntyre
Keith K. Sturcken
Christy A. Hagerty
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BAE Systems Information and Electronic Systems Integration Inc
Original Assignee
BAE Systems Information and Electronic Systems Integration Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BAE Systems Information and Electronic Systems Integration Inc filed Critical BAE Systems Information and Electronic Systems Integration Inc
Priority to US13/547,518 priority Critical patent/US8723323B2/en
Assigned to BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC. reassignment BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HAGERTY, CHRISTY A., MCINTYRE, THOMAS J., STURCKEN, KEITH K.
Publication of US20140015098A1 publication Critical patent/US20140015098A1/en
Priority to US14/224,402 priority patent/US20140206153A1/en
Application granted granted Critical
Publication of US8723323B2 publication Critical patent/US8723323B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4867—Applying pastes or inks, e.g. screen printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
    • B23K1/0016—Brazing of electronic components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to an integrated circuit device packages in general, and in particular to a method for fabricating solder columns for a column grid array package.
  • An integrated circuit (IC) device package may have an IC chip bonded to one side of a substrate and an array of metal connectors extending from the opposite side of the substrate.
  • Two well-known IC device packages are ball grid array (BGA) packages and column grid array (CGA) packages.
  • BGA packages utilize an array of solder balls as metal connectors, and are typically employed by relatively low-performance chip applications.
  • CGA packages utilize an array of solder columns as metal connectors.
  • the solder columns of CGA packages have less tin content than the solder balls in BGA packages, which provide a more compliant and flexible pin connection points that can withstand large temperature or mechanical fluctuations.
  • CGA packages are typically employed by relatively high-performance chip applications.
  • the present disclosure provides an improved method for fabricating solder columns for CGA packages.
  • a column grid array package in accordance with a preferred embodiment of the present invention, includes a substrate, an integrated circuit located on a first side of the substrate, and a set of solder columns located on a second side of the substrate.
  • the column grid array package also includes multiple two-tab electronic devices located on the second side of the substrate. The heights of the two-tab electronic devices are substantially identical to the heights of the solder columns.
  • FIG. 1 is a diagram showing a bottom view of a column grid array package, in accordance with a preferred embodiment of the present invention
  • FIG. 2 is a diagram of a side view of the column grid array package from FIG. 1 , in accordance with a preferred embodiment of the present invention
  • FIG. 3 is a diagram of a side view of the column grid array package from FIG. 1 , in accordance with an alternative embodiment of the present invention.
  • FIG. 4 is a high-level flow diagram of a method for fabricating solder columns for column grid array packages.
  • capacitors For a noise suppression standpoint, it is beneficial to place a large number of capacitors as close as possible to various integrated circuit (IC) devices located on a printed circuit board (PCB).
  • the capacitors help minimizing electrical noise from the IC devices as well as noise in power supplies and ground planes.
  • the capacitors also prevent rail collapses or voltage drops across an IC device's power supply that would cause the IC device to malfunction.
  • capacitors can be placed inside the IC device package and/or on a PCB on which the IC device package is placed.
  • these capacitors may take up a large amount of space within the IC device package and/or the PCB on which the IC device package is placed. While some of the capacitors can be placed directly across a power supply to an IC device and the ground return, such connections may introduce a significant amount of connection inductance between the power supply and the capacitors. The large amount of connection inductance can drastically reduce the effectiveness of the capacitors when the operating speeds of the IC device exceed 500 MHz.
  • a set of capacitors can be placed directly in parallel or in-line with solder columns of a column grid array (CGA) package.
  • CGA column grid array
  • a CGA package 100 includes an array of solder columns 120 arranged on one side of a substrate 101 .
  • An IC chip (not shown) can be bonded to the opposite side of substrate 101 .
  • Electrical connections to the IC chip can be formed through substrate 101 to various contact pads (not shown) on the opposite side of substrate 101 , and solder columns 120 can be attached to the contact pads.
  • Substrate 101 can be made of, for example, ceramic or silicon.
  • CGA package 100 also includes several capacitors 150 located on the same side of solder columns 120 . Basically, capacitors 150 have occupied the locations that would have been occupied by solder columns 120 on substrate 101 .
  • CGA package 100 includes an IC chip 110 located on the top side of substrate 101 , and multiple solder columns 120 located on the bottom side of substrate 101 .
  • solder columns 120 Preferably made of solder, solder columns 120 vary from 0.050 inch to 0.100 inch in height. The height provides compliancy that allow solder columns 120 to flex during thermal expansion rather than fracture as ball grid array solder balls will do when exposed to continuous temperature cycling.
  • CGA package 100 includes capacitors 150 on the bottom side of substrate 101 .
  • capacitors 150 are two-tab cylindrical capacitors that match the height of solder columns 120 .
  • capacitors 150 should be able to flex during thermal expansion when exposed to continuous temperature cycling.
  • capacitors 150 should preferably be located towards the center of CGA package 100 (instead of located around the parameter as shown in FIG. 2 ).
  • two-tab cylindrical capacitors are utilized in FIG. 2 , it is understood by those skilled in the art that other shapes of two-tab capacitors are also applicable for the present invention. While the preferred geometry of the two-tab capacitors is cylindrical having a circular cross-section, other geometries, such as a rectangular block having a rectangular (or square) cross-section, are also acceptable.
  • the height of solder columns 120 can be reduced or lengthened to match the height of the standard two-tab capacitors.
  • a reduced-height solder column can be joined to an end of a standard two-tab capacitor to provide height matching.
  • CGA package 100 includes an IC chip 110 located on the top side of substrate 101 , and multiple solder columns 120 located on the bottom side of substrate 101 .
  • Solder columns 120 vary from 0.050 inch to 0.100 inch in height.
  • CGA package 100 includes capacitors 151 on the bottom side of substrate 101 .
  • Each of capacitors 151 is connected to a reduced-height solder column 160 that is also connected to the bottom side of substrate 101 .
  • capacitors 151 are two-tab cylindrical capacitors. Although two-tab cylindrical capacitors are utilized in FIG. 3 , it is understood by those skilled in the art that other shapes of two-tab capacitors are also applicable for the present invention.
  • FIG. 4 there is illustrated a method for fabricating solder columns for CGA packages, in accordance with a preferred embodiment of the present invention.
  • two-tab capacitors are loaded using a first loading template having holes large enough to fit the two-tab capacitors, as shown in block 401 .
  • Solder paste is then applied to the top surface of the two-tab capacitors, as depicted in block 402 .
  • the solder columns are loaded, as shown in block 403 .
  • Solder is reflowed, as depicted in block 404 .
  • Solder paste is then applied to the top surface of the solder columns, as shown in block 405 .
  • a substrate or an interposer is loaded on top the two-tab capacitors and solder columns, as depicted in block 406 . Finally, the solder is reflowed to join the substrate to the two-tab capacitors and the solder columns to complete the assembly, as shown in block 407 .
  • the present invention provides an improved method for fabricating solder columns of a CGA package.
  • CGA packages of the present invention have high packaging density with minimal inductance.
  • two-tab capacitors are utilized to illustrate the present invention, it is understand that by those skilled in the art that the present invention is also applicable for any two-tab electronic device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

A method for fabricating an electronic device package having a column grid array is disclosed. A column grid array package includes a substrate, an integrated circuit located on a first side of the substrate, and a set of solder columns located on a second side of the substrate. The column grid array package also includes multiple two-tab electronic devices located on the second side of the substrate. The heights of the two-tab electronic devices are substantially identical to the heights of the solder columns.

Description

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to an integrated circuit device packages in general, and in particular to a method for fabricating solder columns for a column grid array package.
2. Description of Related Art
An integrated circuit (IC) device package may have an IC chip bonded to one side of a substrate and an array of metal connectors extending from the opposite side of the substrate. Two well-known IC device packages are ball grid array (BGA) packages and column grid array (CGA) packages.
BGA packages utilize an array of solder balls as metal connectors, and are typically employed by relatively low-performance chip applications. On the other hand, CGA packages utilize an array of solder columns as metal connectors. The solder columns of CGA packages have less tin content than the solder balls in BGA packages, which provide a more compliant and flexible pin connection points that can withstand large temperature or mechanical fluctuations. As such, CGA packages are typically employed by relatively high-performance chip applications.
The present disclosure provides an improved method for fabricating solder columns for CGA packages.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the present invention, a column grid array package includes a substrate, an integrated circuit located on a first side of the substrate, and a set of solder columns located on a second side of the substrate. The column grid array package also includes multiple two-tab electronic devices located on the second side of the substrate. The heights of the two-tab electronic devices are substantially identical to the heights of the solder columns.
All features and advantages of the present invention will become apparent in the following detailed written description.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention itself, as well as a preferred mode of use, further objects, and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
FIG. 1 is a diagram showing a bottom view of a column grid array package, in accordance with a preferred embodiment of the present invention;
FIG. 2 is a diagram of a side view of the column grid array package from FIG. 1, in accordance with a preferred embodiment of the present invention;
FIG. 3 is a diagram of a side view of the column grid array package from FIG. 1, in accordance with an alternative embodiment of the present invention; and
FIG. 4 is a high-level flow diagram of a method for fabricating solder columns for column grid array packages.
 DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT
For a noise suppression standpoint, it is beneficial to place a large number of capacitors as close as possible to various integrated circuit (IC) devices located on a printed circuit board (PCB). The capacitors help minimizing electrical noise from the IC devices as well as noise in power supplies and ground planes. The capacitors also prevent rail collapses or voltage drops across an IC device's power supply that would cause the IC device to malfunction.
In order to maintain an optimized electrical environment for an IC device having a large number of electrical connectors, capacitors can be placed inside the IC device package and/or on a PCB on which the IC device package is placed. However, these capacitors may take up a large amount of space within the IC device package and/or the PCB on which the IC device package is placed. While some of the capacitors can be placed directly across a power supply to an IC device and the ground return, such connections may introduce a significant amount of connection inductance between the power supply and the capacitors. The large amount of connection inductance can drastically reduce the effectiveness of the capacitors when the operating speeds of the IC device exceed 500 MHz.
In order to provide noise reduction while without increasing package density and connection inductance, in accordance with a preferred embodiment of the present invention, a set of capacitors can be placed directly in parallel or in-line with solder columns of a column grid array (CGA) package. Each capacitor should have approximately the equivalent cross-sectional area of a solder column of the CGA package.
Referring now to the drawings and in particular to FIG. 1, there is illustrated a bottom view of a CGA package, in accordance with a preferred embodiment of the present invention. As shown, a CGA package 100 includes an array of solder columns 120 arranged on one side of a substrate 101. An IC chip (not shown) can be bonded to the opposite side of substrate 101. Electrical connections to the IC chip can be formed through substrate 101 to various contact pads (not shown) on the opposite side of substrate 101, and solder columns 120 can be attached to the contact pads. Substrate 101 can be made of, for example, ceramic or silicon.
CGA package 100 also includes several capacitors 150 located on the same side of solder columns 120. Basically, capacitors 150 have occupied the locations that would have been occupied by solder columns 120 on substrate 101.
With reference now to FIG. 2, there is illustrated a side view of CGA package 100, in accordance with a preferred embodiment of the present invention. As shown, CGA package 100 includes an IC chip 110 located on the top side of substrate 101, and multiple solder columns 120 located on the bottom side of substrate 101. Preferably made of solder, solder columns 120 vary from 0.050 inch to 0.100 inch in height. The height provides compliancy that allow solder columns 120 to flex during thermal expansion rather than fracture as ball grid array solder balls will do when exposed to continuous temperature cycling.
In addition, CGA package 100 includes capacitors 150 on the bottom side of substrate 101. Preferably, capacitors 150 are two-tab cylindrical capacitors that match the height of solder columns 120. Like solder columns 120, capacitors 150 should be able to flex during thermal expansion when exposed to continuous temperature cycling. For better compliancy, capacitors 150 should preferably be located towards the center of CGA package 100 (instead of located around the parameter as shown in FIG. 2). Although two-tab cylindrical capacitors are utilized in FIG. 2, it is understood by those skilled in the art that other shapes of two-tab capacitors are also applicable for the present invention. While the preferred geometry of the two-tab capacitors is cylindrical having a circular cross-section, other geometries, such as a rectangular block having a rectangular (or square) cross-section, are also acceptable.
When standard two-tab capacitors that match the height of solder columns 120 cannot be found, the height of solder columns 120 can be reduced or lengthened to match the height of the standard two-tab capacitors. However, when the height differential between standard two-tab capacitors and solder columns 120 are too high, or it is simply not advantageous to modify the height of solder columns 120, a reduced-height solder column can be joined to an end of a standard two-tab capacitor to provide height matching.
Referring now to FIG. 3, there is illustrated a side view of CGA package 100, in accordance with an alternative embodiment of the present invention. As shown, CGA package 100 includes an IC chip 110 located on the top side of substrate 101, and multiple solder columns 120 located on the bottom side of substrate 101. Solder columns 120 vary from 0.050 inch to 0.100 inch in height.
In addition, CGA package 100 includes capacitors 151 on the bottom side of substrate 101. Each of capacitors 151 is connected to a reduced-height solder column 160 that is also connected to the bottom side of substrate 101. Preferably, capacitors 151 are two-tab cylindrical capacitors. Although two-tab cylindrical capacitors are utilized in FIG. 3, it is understood by those skilled in the art that other shapes of two-tab capacitors are also applicable for the present invention.
With reference now to FIG. 4, there is illustrated a method for fabricating solder columns for CGA packages, in accordance with a preferred embodiment of the present invention. Initially, two-tab capacitors are loaded using a first loading template having holes large enough to fit the two-tab capacitors, as shown in block 401. Solder paste is then applied to the top surface of the two-tab capacitors, as depicted in block 402. Next, the solder columns are loaded, as shown in block 403. Solder is reflowed, as depicted in block 404. Solder paste is then applied to the top surface of the solder columns, as shown in block 405. A substrate or an interposer is loaded on top the two-tab capacitors and solder columns, as depicted in block 406. Finally, the solder is reflowed to join the substrate to the two-tab capacitors and the solder columns to complete the assembly, as shown in block 407.
As has been described, the present invention provides an improved method for fabricating solder columns of a CGA package. CGA packages of the present invention have high packaging density with minimal inductance. Although two-tab capacitors are utilized to illustrate the present invention, it is understand that by those skilled in the art that the present invention is also applicable for any two-tab electronic device.
While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.

Claims (16)

What is claimed is:
1. A column grid array (CGA) package comprising:
a substrate;
an integrated circuit located on a first side of said substrate;
a plurality of solder columns each having a longitudinal axis, wherein each of said plurality of solder columns is connected to a second side of said substrate at one end of its longitudinal axis; and
a plurality of two-tab electronic devices each having a longitudinal axis, wherein each of said plurality of two-tab electronic devices is connected to said second side of said substrate at one end of its longitudinal axis such that the longitudinal axes of said plurality of two-tab electronic devices are parallel with the longitudinal axes of said solder columns, wherein heights of said two-tab electronic devices are substantially identical to heights of said solder columns.
2. The CGA package of claim 1, wherein the heights of said solder columns range from 0.05 inch to 0.10 inch.
3. The CGA package of claim 1, wherein said two-tab electronic devices are two-tab capacitors.
4. The CGA package of claim 1, wherein a cross-section of one of said two-tab electronic devices has a circular shape.
5. The CGA package of claim 1, wherein a cross-section of one of said two-tab electronic devices has a rectangular shape.
6. A column grid array (CGA) package comprising:
a substrate;
an integrated circuit located on a first side of said substrate;
a plurality of solder columns each having a longitudinal axis, wherein each of said plurality of solder columns is connected to a second side of said substrate at one end of its longitudinal axis;
a plurality of reduced-height solder columns each having a longitudinal axis, wherein each of said plurality of reduced-height solder columns is connected to a second side of said substrate at a first end of its longitudinal axis; and
a plurality of two-tab electronic devices each connected to a respective one of said reduced-height solder columns at a second end of its longitudinal axis, wherein a combined height of one of said two-tab electronic devices and one of said reduced-height solder columns is substantially identical to a height of one of said solder columns.
7. The CGA package of claim 6, wherein the heights of said solder columns range from 0.05 inch to 0.10 inch.
8. The CGA package of claim 6, wherein said two-tab electronic devices are two-tab capacitors.
9. The CGA package of claim 6, wherein a cross-section of one of said two-tab electronic devices has a circular shape.
10. The CGA package of claim 6, wherein a cross-section of one of said two-tab electronic devices has a rectangular shape.
11. The CGA package of claim 6, wherein each of said plurality of solder columns' longitudinal axis is along its height.
12. The CGA package of claim 11, wherein each of said plurality of reduced-height solder columns' longitudinal axis is along its height.
13. The CGA package of claim 12, wherein each of said plurality of two-tab electronic devices has a longitudinal axis that is located along its height.
14. The CGA package of claim 12, wherein each of said plurality of two-tab electronic devices is connected to a respective one of said reduced-height solder columns along their longitudinal axes.
15. The CGA package of claim 1, wherein each of said plurality of solder columns' longitudinal axis is along its height.
16. The CGA package of claim 13, wherein each of said plurality of two-tab electronic devices' longitudinal axis is along its height.
US13/547,518 2012-07-12 2012-07-12 Method for fabricating solder columns for a column grid array package Active US8723323B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US13/547,518 US8723323B2 (en) 2012-07-12 2012-07-12 Method for fabricating solder columns for a column grid array package
US14/224,402 US20140206153A1 (en) 2012-07-12 2014-03-25 Method for fabricating solder columns for a column grid array package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/547,518 US8723323B2 (en) 2012-07-12 2012-07-12 Method for fabricating solder columns for a column grid array package

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US14/224,402 Division US20140206153A1 (en) 2012-07-12 2014-03-25 Method for fabricating solder columns for a column grid array package

Publications (2)

Publication Number Publication Date
US20140015098A1 US20140015098A1 (en) 2014-01-16
US8723323B2 true US8723323B2 (en) 2014-05-13

Family

ID=49913286

Family Applications (2)

Application Number Title Priority Date Filing Date
US13/547,518 Active US8723323B2 (en) 2012-07-12 2012-07-12 Method for fabricating solder columns for a column grid array package
US14/224,402 Abandoned US20140206153A1 (en) 2012-07-12 2014-03-25 Method for fabricating solder columns for a column grid array package

Family Applications After (1)

Application Number Title Priority Date Filing Date
US14/224,402 Abandoned US20140206153A1 (en) 2012-07-12 2014-03-25 Method for fabricating solder columns for a column grid array package

Country Status (1)

Country Link
US (2) US8723323B2 (en)

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3898541A (en) * 1973-12-17 1975-08-05 Vitramon Inc Capacitors and method of adjustment
US4734818A (en) * 1985-01-22 1988-03-29 Rogers Corporation Decoupling capacitor for surface mounted leadless chip carriers, surface mounted leaded chip carriers and Pin Grid Array packages
US5132806A (en) * 1989-06-19 1992-07-21 Hitachi, Ltd. Semiconductor integrated circuit device
US5404265A (en) * 1992-08-28 1995-04-04 Fujitsu Limited Interconnect capacitors
US6145735A (en) * 1998-09-10 2000-11-14 Lockheed Martin Corporation Thin film solder paste deposition method and tools
US6320249B1 (en) * 1999-11-30 2001-11-20 Glotech, Inc. Multiple line grids incorporating therein circuit elements
US20020179573A1 (en) * 2001-06-01 2002-12-05 Gianchandani Yogesh B. Micro-electro-discharge machining method and apparatus
US6917113B2 (en) * 2003-04-24 2005-07-12 International Business Machines Corporatiion Lead-free alloys for column/ball grid arrays, organic interposers and passive component assembly
US20070034989A1 (en) * 2004-07-15 2007-02-15 Fujitsu Limited Capacitive element, method of manufacture of the same, and semiconductor device
US7348661B2 (en) * 2004-09-24 2008-03-25 Intel Corporation Array capacitor apparatuses to filter input/output signal
US7553696B2 (en) * 2006-08-29 2009-06-30 International Business Machines Corporation Method for implementing component placement suspended within grid array packages for enhanced electrical performance
US7944028B2 (en) * 2002-02-11 2011-05-17 Don Saunders TFCC (TM) and SWCC (TM) thermal flex contact carriers
US8395902B2 (en) * 2008-05-21 2013-03-12 International Business Machines Corporation Modular chip stack and packaging technology with voltage segmentation, regulation, integrated decoupling capacitance and cooling structure and process

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200414858A (en) * 2003-01-15 2004-08-01 Senju Metal Industry Co Apparatus and method for aligning and attaching solder columns to a substrate

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3898541A (en) * 1973-12-17 1975-08-05 Vitramon Inc Capacitors and method of adjustment
US4734818A (en) * 1985-01-22 1988-03-29 Rogers Corporation Decoupling capacitor for surface mounted leadless chip carriers, surface mounted leaded chip carriers and Pin Grid Array packages
US5132806A (en) * 1989-06-19 1992-07-21 Hitachi, Ltd. Semiconductor integrated circuit device
US5404265A (en) * 1992-08-28 1995-04-04 Fujitsu Limited Interconnect capacitors
US6145735A (en) * 1998-09-10 2000-11-14 Lockheed Martin Corporation Thin film solder paste deposition method and tools
US6320249B1 (en) * 1999-11-30 2001-11-20 Glotech, Inc. Multiple line grids incorporating therein circuit elements
US20020179573A1 (en) * 2001-06-01 2002-12-05 Gianchandani Yogesh B. Micro-electro-discharge machining method and apparatus
US7944028B2 (en) * 2002-02-11 2011-05-17 Don Saunders TFCC (TM) and SWCC (TM) thermal flex contact carriers
US6917113B2 (en) * 2003-04-24 2005-07-12 International Business Machines Corporatiion Lead-free alloys for column/ball grid arrays, organic interposers and passive component assembly
US20070034989A1 (en) * 2004-07-15 2007-02-15 Fujitsu Limited Capacitive element, method of manufacture of the same, and semiconductor device
US7348661B2 (en) * 2004-09-24 2008-03-25 Intel Corporation Array capacitor apparatuses to filter input/output signal
US7553696B2 (en) * 2006-08-29 2009-06-30 International Business Machines Corporation Method for implementing component placement suspended within grid array packages for enhanced electrical performance
US8395902B2 (en) * 2008-05-21 2013-03-12 International Business Machines Corporation Modular chip stack and packaging technology with voltage segmentation, regulation, integrated decoupling capacitance and cooling structure and process

Also Published As

Publication number Publication date
US20140206153A1 (en) 2014-07-24
US20140015098A1 (en) 2014-01-16

Similar Documents

Publication Publication Date Title
US20190182958A1 (en) Mainboard assembly including a package overlying a die directly attached to the mainboard
KR100616384B1 (en) Electronic assembly with vertically connected capacitors and manufacturing method
US7259453B2 (en) Hexagonal array structure for ball grid array packages
US7663232B2 (en) Elongated fasteners for securing together electronic components and substrates, semiconductor device assemblies including such fasteners, and accompanying systems
US9673148B2 (en) System in package
TWI581397B (en) Chip package, computer system and electronic device
US8379391B2 (en) Memory module with vertically accessed interposer assemblies
KR101731691B1 (en) Three dimensional passive multi-component structures
US20150022985A1 (en) Device-embedded package substrate and semiconductor package including the same
US20110090662A1 (en) Method and apparatus for improving power noise of ball grid array package
US20140110831A1 (en) Multi-chip package and method of manufacturing the same
US20080205011A1 (en) In-grid decoupling for ball grid array (BGA) devices
US9337137B1 (en) Method and system for solder shielding of ball grid arrays
US8674505B2 (en) Integrated circuit packaging with ball grid array having differential pitch to enhance thermal performance
TWI533425B (en) Ball grid array and land grid array having modified footprint
US9565762B1 (en) Power delivery network in a printed circuit board structure
US8723323B2 (en) Method for fabricating solder columns for a column grid array package
KR20120096754A (en) Three-dimensional stack structure of wafer chip using interposer
US9844135B2 (en) Decoupling capacitive arrangement to manage power integrity
JP4627323B2 (en) Semiconductor device
US20090268422A1 (en) Scalable electronic package assembly for memory devices and other terminated bus structures
JP2007129046A (en) Mounting structure of capacitor array
CN112492752A (en) Chip pin extension device
US20120168937A1 (en) Flip chip package and method of manufacturing the same
US20130341806A1 (en) Substrate structure and semiconductor package using the same

Legal Events

Date Code Title Description
AS Assignment

Owner name: BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INT

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MCINTYRE, THOMAS J.;STURCKEN, KEITH K.;HAGERTY, CHRISTY A.;REEL/FRAME:028542/0878

Effective date: 20120703

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551)

Year of fee payment: 4

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 8