US8576897B2 - Receiver - Google Patents
Receiver Download PDFInfo
- Publication number
- US8576897B2 US8576897B2 US13/625,116 US201213625116A US8576897B2 US 8576897 B2 US8576897 B2 US 8576897B2 US 201213625116 A US201213625116 A US 201213625116A US 8576897 B2 US8576897 B2 US 8576897B2
- Authority
- US
- United States
- Prior art keywords
- conversion rate
- maximum conversion
- determined
- analog
- temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
- H04B1/50—Circuits using different frequencies for the two directions of communication
- H04B1/52—Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa
- H04B1/525—Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa with means for reducing leakage of transmitter signal into the receiver
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/0003—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain
- H04B1/0028—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain wherein the AD/DA conversion occurs at baseband stage
- H04B1/0046—Decimation, i.e. data rate reduction techniques
Definitions
- the present invention relates to wireless receivers that support cellular standards such as LTE, triple-carrier WCDMA. More particularly, but not exclusively, the invention relates to the operation of an analog-to-digital converter comprised in such a receiver.
- FIG. 1 shows a transceiver 100 that transmits and receives radio frequency signals through one or more connected antennas 102 and connects via digital interfaces to a modulator/demodulator (modem) 140 .
- Transceiver 100 and modem 140 may be integrated together with display 182 , keypad 184 , loudspeaker 186 , microphone 188 and chipset 180 into a mobile wireless device 189 such as a mobile phone.
- Other applications of radio frequency transceivers include use in base stations or machine-to-machine communications such as vending machines or cash registers, for example.
- Transceiver 100 comprises a transmitter and a receiver.
- the receiver processes a received radio frequency signal that is picked up by antenna 102 and converts it to a down-sampled received signal 138 .
- the received radio frequency signal comprises a wanted signal component, for example encoded speech data in a voice call that is decoded and sent to loudspeaker 186 .
- the transmitter converts a digital data stream 145 that may for example encode voice data from microphone 188 to a radio frequency signal that is transmitted by antenna 102 .
- a radio frequency input signal from antenna 102 is coupled to duplex filter 108 , where only a predetermined receive band frequency range passes through to receive path signal 110 .
- Receive path signal 110 is amplified by low-noise amplifier 112 and down-converted into baseband signal 126 by receive path mixer 114 using receiver local oscillator signal 116 .
- Receiver local oscillator signal 116 is generated at a received channel frequency by receiver synthesizer 118 based on a reference clock 120 , and may comprise an in-phase component and a quadrature component.
- Receive path mixer 114 may implement quadrature down-conversion using a pair of mixers, providing an in-phase and a quadrature component of baseband signal 126 .
- Baseband signal 126 is filtered by analog baseband filter 128 , and the resulting filtered baseband signal 130 is sampled by analog-to-digital converter (ADC) 132 using an ADC sampling clock signal 170 that is provided by ADC sampling clock generator 172 at an ADC conversion rate, resulting in sampled received signal 134 .
- Analog baseband filter 128 may comprise an in-phase branch and a quadrature branch.
- ADC 132 may comprise an in-phase branch and a quadrature branch.
- a first sample-rate converter 136 converts sampled received signal 134 into down-sampled received signal 138 at a lower sampling rate. Down-sampled received signal 138 is provided to modem 140 .
- digital transmit signal 145 is provided by modem 140 to transceiver 100 , where it is converted to a higher sample rate in second sample-rate converter 146 , converted to an analog signal in digital-to-analog converter (DAC) 148 using a DAC sampling clock signal that is provided by DAC sampling clock generator 162 , low-pass filtered by transmit baseband filter 150 into transmit baseband signal 152 , up-converted to radio frequency by transmit mixer 154 using a transmitter local oscillator signal, and amplified by transmit amplifier 158 resulting in transmit signal 106 .
- Transmit signal 106 is coupled by the duplex filter 108 to antenna 102 .
- the transmitter local oscillator signal is generated at a transmitted channel frequency by transmit synthesizer 156 from reference clock 120 and may comprise an in-phase and a quadrature component.
- Reference clock 120 may be generated by a reference crystal oscillator 122 .
- Reference crystal oscillator 122 may be connected to a temperature compensation unit 124 .
- Temperature compensation unit 124 may comprise a temperature sensor that can be queried through bus interface 190 a , and offset circuitry for reference crystal oscillator 122 that can be controlled through bus interface 190 a , for example by CPU 192 .
- Temperature compensation unit 124 may also autonomously measure the temperature and apply offset correction to reference crystal oscillator 122 .
- the transmit signal 106 is generated at a sufficiently high power level for transmission, for example 24 dBm at the antenna 102 .
- a part of transmit signal 106 leaks into the receive path signal 110 due to unwanted coupling mechanism 160 , resulting in an unwanted signal component known as “transmit leakage”.
- Unwanted coupling mechanism 160 may be caused by finite attenuation of duplex filter 108 or parasitic coupling between lines on a printed wiring board, for example.
- the transmit leakage is processed by the receive path, appearing at the input of analog-to-digital converter 132 at a frequency offset relative to the wanted signal component. Depending on the frequency offset and the ADC conversion rate, the transmit leakage may result in an alias component created by ADC 132 .
- FIG. 2 a shows a spectrum of signals at the input of analog baseband filter 128 in FIG. 1 on a frequency axis.
- a wanted signal component 200 falls into a pass-band 202 of a frequency response 204 of analog baseband filter 128 in FIG. 1 .
- a transmit leakage component 206 is attenuated by a stop-band gain 208 of frequency response 204 .
- FIG. 2 b shows the output of analog baseband filter 128 which appears as input signal to ADC 132 .
- the attenuated transmit leakage component 210 still carries considerably higher power than wanted signal component 200 and substantially overlaps alias response 212 around a conversion rate 216 .
- Alias response 21 is caused b sampling within ADC 132 , causing signal components near the Nyquist frequency to fold back and appear as replicas in the sampled signal.
- the resulting alias component 214 overwhelms the weak wanted signal component 200 and disrupts reception.
- FIG. 2 c shows a first solution, where analog baseband filter 128 implements a higher order frequency response 204 ′ with an increased stop-band attenuation 208 ′.
- the attenuated transmit leakage component 210 ′ appears at such a low power level due to the increased stop-band attenuation 208 ′ that its alias component 214 ′ in FIG. 2 d does not significantly deteriorate reception.
- Disadvantages to using a higher order frequency response are an increased current consumption of analog baseband filter 128 and an increased sensitivity of a higher order analog baseband filter to process and temperature variations that may lead to a general reduction in the received signal quality at modem 140 .
- FIGS. 2 e and 2 f illustrate a second solution, where the conversion rate 216 ′′ has been increased to more the alias response 212 ′′ towards higher frequencies, avoiding substantial overlap with attenuated transmit leakage component 210 .
- the resulting alias component 214 ′′ occupies a different frequency range than the wanted signal component 200 and can be separated by a later processing stage using digital filtering, for example.
- alias component 214 ′′ and wanted signal component 220 are substantially non-overlapping.
- a disadvantage of the solution is that it is difficult or impossible to guarantee correct operation of the ADC at the increased conversion rate 216 ′′ under all conditions, as FIG. 2 g illustrates in the following.
- FIG. 2 g shows the achievable maximum sampling rate of an ADC, such as ADC 132 in FIG. 1 , depending on variations of the semiconductor process and temperature.
- Transceiver 100 in FIG. 1 may be integrated partly or in whole in a radio frequency integrated circuit (RFIC) on a semiconductor process such as a 32 nm CMOS (complementary metal-oxide-semiconductor) process.
- RFIC radio frequency integrated circuit
- CMOS complementary metal-oxide-semiconductor
- duplex filter 108 and transmit amplifier 158 may be connected as external components to the RFIC.
- the parameters of the semiconductor process may vary considerably as a result of many contributing factors, for example the production batch, operating temperature, circuit aging and even the location of each RFIC die on a CMOS production wafer. Coping with the expected parameter variations is a significant challenge in RFIC circuit design, where the goal is to design circuitry that works reliably for the widest possible range of parameter variations.
- ADC 132 is among the most challenging circuit blocks to design, and it may be impossible to achieve a sufficiently high conversion rate (also known as sampling rate) over all parameter variations.
- Trace 250 in FIG. 2 g illustrates the guaranteed conversion rate of an ADC, which is near 52 MHz.
- the “nominal” performance in trace 252 that can be reached by the majority of manufactured ADCs is over 58 MHz at room temperature, which is a 10% increase over guaranteed performance. Since the ADC is among the most difficult components to design, a 10% increase in performance is valuable and may notably improve the performance of the receiver.
- An “outstanding” manufactured ADC achieves the 58 MHz conversion rate over the whole temperature range, according to trace 254 and is capable of even higher rates at room temperature.
- radio transceivers are designed for the guaranteed minimum performance of the components, for example based on trace 250 in FIG. 2 g . Since the majority of manufactured ADCs will be able to perform better under most circumstances (room temperature), this is inefficient.
- the present invention generally introduces a method of mitigating effects of alias responses in a transceiver comprising a transmitter and a receiver, the receiver comprising an analog-to-digital converter.
- the present invention provides a method of operating an analog-to-digital converter of a transceiver including a transmitter and a receiver, the receiver including said analog-to-digital converter, the method including: determining a maximum conversion rate of the analog-to-digital converter, wherein determining said maximum conversion rate comprises determining a temperature of the analog-to-digital converter; and selecting a conversion rate of the analog-to-digital converter, based on the determined maximum conversion rate and a frequency of an unwanted signal component of the receiver, such that the selected conversion rate places an alias response of the unwanted signal component to a frequency range which is substantially non-overlapping with a wanted signal component of the receiver.
- the present invention provides an apparatus including: a processing unit, at least one memory for storing a computer program, a transmitter and a receiver.
- the receiver includes an analog-to-digital converter.
- the at least one memory with the computer program being configured with the processing unit to cause the progressing unit to: determine a maximum conversion rate of the analog-to-digital converter, wherein determining said maximum conversion rate comprises determining a temperature of the analog-to-digital converter; and select a conversion rate of the analog-to-digital converter based on the determined maximum conversion rate and a frequency of an unwanted signal component of the receiver, such that the selected conversion rate places an alias response of the unwanted signal component to a frequency range which is substantially non-overlapping with a wanted signal component of the receiver.
- the present invention provides a non-transient program storage device readable by a processing unit, tangibly embodying a program of instructions executable by the processing unit, which, when executed by a processing unit of an apparatus which includes the processing unit, a transmitter and a receiver, where the receiver includes an analog-to-digital converter, causes the processing unit to determine a maximum conversion rate of the analog-to-digital converter, wherein determining said maximum conversion rate comprises determining a temperature of the analog-to-digital converter, and to select a conversion rate of the analog-to-digital converter based on the determined maximum conversion rate and a frequency of an unwanted signal component of the receiver, such that the selected conversion rate places an alias response of the unwanted signal component to a frequency range which is substantially non-overlapping with a wanted signal component of the receiver.
- FIG. 1 is a block diagram that illustrates a general structure of a radio frequency transceiver, comprising a transmitter and a receiver, the receiver comprising an analog-to-digital converter;
- FIGS. 2 a - 2 f are frequency domain graphs that illustrate aliasing processes in an analog-to-digital converter
- FIG. 2 g is a graph that illustrates the achievable maximum sampling rate of an ADC depending on variations of the semiconductor process and temperature;
- FIG. 3 is a flowchart of a method for selecting a conversion rate of an ADC as an embodiment of the invention
- FIG. 4 is a detailed flowchart of a method for selecting the conversion rate
- FIG. 5 is a flowchart of a method for determining the maximum conversion rate based on temperature
- FIG. 6 is a flowchart of a method to determine a maximum conversion rate
- FIGS. 7 a is a flowchart of a method to determine correctness of a conversion result
- FIGS. 7 b and 7 c are timing diagrams that illustrate internal processes of an analog-to-digital converter.
- FIG. 8 is a datable table showing linking temperatures with maximum conversion rates of the analog-to-digital converter.
- Embodiments of the present invention relate to a method, an apparatus and a computer program product for selecting a conversion rate for an analog-to-digital converter.
- the conversion rate selection is performed to operate the analog-to-digital converter at an advantageous conversion rate that is below a maximum conversion rate, which may change over time.
- Embodiments of the invention operate to mitigate effects of alias responses in a transceiver comprising a transmitter and a receiver, the receiver comprising such an analog-to-digital converter.
- FIG. 3 illustrates a flow chart of a method according to an embodiment of the invention.
- the method is applied by CPU 192 in radio transceiver 100 of FIG. 1
- CPU 192 may initiate the method as a response to a change in radio resource allocation that is signalled by modern 140 via digital has interface 190 d to CPU 192 .
- the change in radio resource allocation may comprise a change in a transmission or reception bandwidth allocation, a change in transmission or reception radio channel, or a change in a transmission or reception band, for example.
- An example of transmission and reception bands is WCDMA band “I”, where the transmission band extends from 1920 MHz to 1980 MHz and the reception band extends from 2110 MHz to 2170 MHz.
- CPU 192 initiates method 300 when a change in a measured temperature exceeds a hysteresis threshold relative to an earlier measured temperature.
- a maximum conversion rate of an analog-to-digital converter is determined. In one example embodiment, a maximum conversion rate of ADC 132 in transceiver 100 of FIG. 1 is determined.
- a frequency of an unwanted signal component is determined. In an example embodiment, the unwanted signal component is transmit leakage from transmit signal 106 in transceiver 100 of FIG. 1 , and the frequency of the unwanted signal component is a difference between a transmitted channel frequency and a received channel frequency that are utilized by the transceiver 100 .
- such a conversion rate is selected which does not exceed the determined maximum conversion rate, so that an alias response of the unwanted signal component does not substantially overlap with the wanted signal component regarding their frequency bands.
- FIG. 4 shows a flowchart of a method 400 for selecting a conversion rate.
- method 400 implements operation 330 of FIG. 3 .
- an operating band of the transceiver is determined.
- the operating band may be band VIII in WCDMA/HSDPA operation, according to technical specification 3GPP TS 25.101.
- a minimum alias-free conversion rate is determined.
- both BW Rx + and BW Tx + may be set to 2 MHz, and
- a usable rate r u is searched which is greater than or equal to the minimum alias-free conversion rate, while not exceeding the maximum conversion rate. Searching a usable rate may also exclude rates that are known to result in unwanted spurious tones, for example caused by a harmonic of the rate falling into a receive channel bandwidth.
- the execution of the example procedure is divided between two branches, depending on whether or not a usable rate r u is found. If a usable rate is found, the usable rate is configured at operation 412 as the conversion rate for the clock of an analog-to-digital converter. In one embodiment of the invention, the usable rate is configured to ADC sampling clock generator 172 in transceiver 100 of FIG. 1 . Execution continues at operation 414 , where an analog filter is configured to realize a low-order frequency response. In one embodiment of the invention, analog baseband filter 128 in transceiver 100 of FIG. 1 is configured as a 3 rd order response and the process ends.
- a maximum alias-free conversion rate r max,alias is determined.
- BW Tx ⁇ is a one-sided bandwidth of the transmitted signal which is located in frequency on the side facing away from the received channel frequency
- BW Rx ⁇ is a one-sided bandwidth of the received signal which is located in frequency facing away from the transmitted channel frequency.
- BW Rx ⁇ and BW Tx ⁇ may be set to 2 MHz
- f Duplex may be set to 45 MHz.
- the maximum alias-free conversion rate is compared against a required rate r req .
- the required rate may be a predetermined constant which depends on the operating band. In one example embodiment, the required rate is 38 MHz for WCDMA band VIII operation. If the determined maximum alias-free conversion rate is greater than or equal to the required rate, the maximum alias-free conversion rate is configured as a conversion rate to an analog-to-digital converter and execution continues at operation 414 . If, on the other hand, the determined maximum alias-free conversion rate is below the required rate, execution continues at operation 422 , where the required rate is configured as the conversion rate to the analog-to-digital converter.
- the analog filter is configured to realize a higher-order frequency response and the process ends. In one example embodiment, analog baseband filter 128 in transceiver 100 of FIG. 1 is configured to a 5 th order response.
- FIG. 5 illustrates a method 500 for determining a maximum conversion rate.
- method 500 implements operation 310 in FIG. 3 .
- a temperature T of the ADC is determined in operation 510 .
- the ADC occupies a finite area on a semiconductor substrate, and a temperature gradient will be present in all three dimensions. Therefore, any temperature measurement can reflect the physical reality only to a limited degree of accuracy. For example, temperature can be measured with high accuracy using a sensor located on the semiconductor die near the ADC, or with somewhat lower accuracy using a sensor located close to the RFIC component on a printed wiring board (PWB). Thus, it may be stated that a temperature of the ADC can be determined by measuring a temperature at a location close to the ADC.
- the temperature of the ADC is measured using a temperature sensor that forms part of temperature compensation unit 124 for reference crystal oscillator 122 of transceiver 100 in FIG. 1 .
- CPU 192 may request a temperature reading via bus interfaces 190 e and 190 a from temperature compensation unit 124 .
- temperature may be measured b a sensor which is located on a RFIC or requested from chipset 180 , for example.
- the maximum conversion rate is determined based on the temperature T.
- the maximum conversion rate may be determined by interpolating in temperature using interpolation coefficients.
- the RFIC classifies its process parameters, for example by measuring a RC time constant, or determining the frequency of a test oscillator into one of the three categories “outstanding”, “nominal” or “guaranteed performance”, and looks up the interpolation coefficients based on the classification of the process parameters. This is already illustrated in FIG. 2 g .
- the maximum conversion rate is determined as a predetermined constant if temperature exceeds a threshold.
- FIG. 6 illustrates another method 600 to determine a maximum conversion rate of an ADC.
- Method 600 may implement operation 310 of FIG. 3 as an embodiment of the invention.
- a maximum conversion rate estimate is initialized, for example to a worst-case conversion rate which is guaranteed by the manufacturer of the ADC.
- a loop iterates over a set of possible operation rates.
- the set of possible rates may be rates that can be divided from a high frequency clock using integer division factors. Rates may be iterated in an increasing order.
- the iterated rate is configured as conversion rate to an ADC.
- the correctness of a conversion result from the ADC is tested.
- the correctness of the conversion result is determined by operating the receiver on a known test signal (for example generated by the transmitter in “loop-back testing”).
- the correctness of the conversion result is determined by comparing a signal quality indicator of the down-sampled received signal 138 in FIG. 1 against a predetermined threshold.
- the signal quality indicator may be a bit error rate (BER) provided by modem 140 , and determining the correctness of the conversion result returns a positive test result if the bit error is below a predetermined threshold, or otherwise, a negative test result.
- BER bit error rate
- the signal quality indicator may be an error vector magnitude (EVM) provided by modem 140 , and determining correctness of the conversion result may return a positive test result if the EVM in units of dB is below a predetermined threshold or, otherwise, a negative test result is returned.
- EVM error vector magnitude
- the maximum conversion rate estimate is updated to the iterated rate if the conversion result was found correct.
- FIG. 7 a illustrates a flowchart of a method 700 according to an embodiment of the invention.
- Method 700 may implement operation 630 in method 600 of FIG. 6 .
- the successful completion of an approximation step in an analog-to-digital converter is tested.
- the analog-to-digital converter may be a successive-approximation (SAR) ADC.
- the tested approximation step may be the final approximation step of a series of approximation steps. If successful completion is determined, operation continues at operation 720 , where a positive test result is returned, indicating correctness of the conversion result. If successful completion is not determined, operation continues instead at operation 730 , where a negative test result is returned, further indicating failure to convert correctly.
- FIG. 7 b shows a series of successive approximation steps in a SAR ADC.
- ADC sampling clock signal 170 initiates a new conversion cycle at each leading edge and triggers a sequence of conversion steps 702 , 704 , 706 leading to the final step 708 .
- step 704 is triggered using asynchronous logic. The time for each step to converge depends on the temperature of the ADC, therefore an ADC may be able to achieve only a lower maximum conversion rate when temperature increases.
- FIG. 7 c shows the conversion process at an elevated temperature.
- the sequence of conversion steps 702 . . . 708 succeeds at room temperature in FIG. 7 b , since conversion step 708 concludes before the start of the next conversion cycle 710 .
- the longer duration of conversion steps 702 ′, 704 ′, 706 ′, . . . , 708 ′ at the elevated temperature causes the conversion process to exceed the cycle length of ADC sampling clock signal 170 . Thus, conversion fails and returns an incorrect conversion result.
- the ADC determines an estimate of the maximum conversion rate by measuring a remaining time 750 in FIG. 7 b between the end of an approximation step in a SAR ADC and the end of a conversion cycle.
- the maximum con version rate may be estimated by scaling the current conversion rate with the ratio of remaining time 750 to conversion cycle length 752 .
- a data table may be used, such as shown in FIG. 8 in which sample maximum conversion rates MCR 1 -MCR 7 are correlated to temperatures T 1 -T 7 .
- the inventive idea comprises a computer program product which is adapted to perform applicable operations when executed in a data-processing device such as a processing unit or a CPU of the system, for instance.
- a processor may thus be the processing unit of the transceiver itself or control logic available internally in the system or remotely in the network.
- the computer program product may be embodied in a computer-readable medium.
- the advantage of the invention is that the alias response effect on the received signal is clearly mitigated and such an effect is achieved with notably low power consumption.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Transceivers (AREA)
Abstract
Description
Claims (18)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/625,116 US8576897B2 (en) | 2011-09-16 | 2012-09-24 | Receiver |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB1116090.0A GB2494695B (en) | 2011-09-16 | 2011-09-16 | Receiver |
US13/234,393 US8553748B2 (en) | 2011-09-16 | 2011-09-16 | ADC clock selection based on determined maximum conversion rate |
GB1116090.0 | 2011-09-16 | ||
US13/625,116 US8576897B2 (en) | 2011-09-16 | 2012-09-24 | Receiver |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/234,393 Continuation US8553748B2 (en) | 2011-09-16 | 2011-09-16 | ADC clock selection based on determined maximum conversion rate |
Publications (2)
Publication Number | Publication Date |
---|---|
US20130070818A1 US20130070818A1 (en) | 2013-03-21 |
US8576897B2 true US8576897B2 (en) | 2013-11-05 |
Family
ID=47880642
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/234,393 Active 2031-12-05 US8553748B2 (en) | 2011-09-16 | 2011-09-16 | ADC clock selection based on determined maximum conversion rate |
US13/625,116 Active US8576897B2 (en) | 2011-09-16 | 2012-09-24 | Receiver |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/234,393 Active 2031-12-05 US8553748B2 (en) | 2011-09-16 | 2011-09-16 | ADC clock selection based on determined maximum conversion rate |
Country Status (1)
Country | Link |
---|---|
US (2) | US8553748B2 (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4604699A (en) * | 1984-01-25 | 1986-08-05 | The United States Of America As Represented By The Secretary Of The Interior | General earthquake observation system |
US5612975A (en) * | 1993-05-28 | 1997-03-18 | Tv/Com Technologies, Inc. | Digital receiver for variable data rate communications |
US20100316098A1 (en) | 2009-06-11 | 2010-12-16 | Qualcomm Incorporated | Apparatus and method for dynamic scaling of adc sampling rate to avoid receiver interference |
US8149896B2 (en) * | 2006-01-04 | 2012-04-03 | Qualcomm, Incorporated | Spur suppression for a receiver in a wireless communication system |
-
2011
- 2011-09-16 US US13/234,393 patent/US8553748B2/en active Active
-
2012
- 2012-09-24 US US13/625,116 patent/US8576897B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4604699A (en) * | 1984-01-25 | 1986-08-05 | The United States Of America As Represented By The Secretary Of The Interior | General earthquake observation system |
US5612975A (en) * | 1993-05-28 | 1997-03-18 | Tv/Com Technologies, Inc. | Digital receiver for variable data rate communications |
US8149896B2 (en) * | 2006-01-04 | 2012-04-03 | Qualcomm, Incorporated | Spur suppression for a receiver in a wireless communication system |
US20100316098A1 (en) | 2009-06-11 | 2010-12-16 | Qualcomm Incorporated | Apparatus and method for dynamic scaling of adc sampling rate to avoid receiver interference |
Non-Patent Citations (1)
Title |
---|
UK IPO Combined Search and Examination Report under Section 17 and 18(3) dated Jan. 16, 2012 issued in a related British Application No. GB1116090.0 (6 pages). |
Also Published As
Publication number | Publication date |
---|---|
US20130070818A1 (en) | 2013-03-21 |
US8553748B2 (en) | 2013-10-08 |
US20130070815A1 (en) | 2013-03-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP3285404B1 (en) | Digital-centric full-duplex architecture | |
US9712312B2 (en) | Systems and methods for near band interference cancellation | |
EP2947781B1 (en) | System and method for tuning an antenna in a wireless communication device | |
US8521090B2 (en) | Systems, methods, and apparatuses for reducing interference at the front-end of a communications receiving device | |
US7130589B2 (en) | Self-calibrating apparatus and method in a mobile transceiver | |
US10432243B2 (en) | Receiver nonlinearity estimation and cancellation | |
US8417204B2 (en) | Method and system for on-demand signal notching in a receiver | |
EP2474099B1 (en) | Radio environment scanner | |
US9160356B1 (en) | Analog to digital convertor and a method of calibrating same | |
US9118285B2 (en) | Compensation of a transmitter distortion | |
US8428526B2 (en) | System and method for tuning baseband filters in wireless transceivers | |
US10122477B2 (en) | Transmitter performance calibration systems and methods | |
US8532225B2 (en) | DC compensation for VLIF signals | |
US8576897B2 (en) | Receiver | |
CN109286407B (en) | Interference signal suppression device and method for suppressing strong interference signal | |
GB2489337A (en) | A transceiver which adapts the sampling rate of a receiver ADC to avoid interference between a wanted signal and an aliased transmit leakage component | |
US10142041B2 (en) | Homodyne receiver calibration | |
Deeying et al. | Feedback Receivers: Specification and State-of-the-Art Review | |
JP2011182149A (en) | Semiconductor integrated circuit, and information processing device with semiconductor integrated circuit | |
CN117675489A (en) | Signal correction method and device | |
KR20080104666A (en) | Method for calibration to remove local oscillator leakage power for wibro terminal |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: RENESAS MOBILE CORPORATION, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NENTWIG, MARKUS;REEL/FRAME:029011/0718 Effective date: 20120920 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: BROADCOM INTERNATIONAL LIMITED, CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:RENESAS MOBILE CORPORATION;REEL/FRAME:032422/0716 Effective date: 20130930 |
|
AS | Assignment |
Owner name: BROADCOM CORPORATION, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BROADCOM INTERNATIONAL LIMITED;REEL/FRAME:032447/0748 Effective date: 20131009 |
|
AS | Assignment |
Owner name: BANK OF AMERICA, N.A., AS COLLATERAL AGENT, NORTH CAROLINA Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:BROADCOM CORPORATION;REEL/FRAME:037806/0001 Effective date: 20160201 Owner name: BANK OF AMERICA, N.A., AS COLLATERAL AGENT, NORTH Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:BROADCOM CORPORATION;REEL/FRAME:037806/0001 Effective date: 20160201 |
|
AS | Assignment |
Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD., SINGAPORE Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BROADCOM CORPORATION;REEL/FRAME:041706/0001 Effective date: 20170120 Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BROADCOM CORPORATION;REEL/FRAME:041706/0001 Effective date: 20170120 |
|
AS | Assignment |
Owner name: BROADCOM CORPORATION, CALIFORNIA Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS;ASSIGNOR:BANK OF AMERICA, N.A., AS COLLATERAL AGENT;REEL/FRAME:041712/0001 Effective date: 20170119 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITE Free format text: MERGER;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:047230/0910 Effective date: 20180509 |
|
AS | Assignment |
Owner name: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITE Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF THE MERGER PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0910. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:047351/0384 Effective date: 20180905 |
|
AS | Assignment |
Owner name: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITE Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER IN THE INCORRECT US PATENT NO. 8,876,094 PREVIOUSLY RECORDED ON REEL 047351 FRAME 0384. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:049248/0558 Effective date: 20180905 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |