GB2489337A

GB2489337A - A transceiver which adapts the sampling rate of a receiver ADC to avoid interference between a wanted signal and an aliased transmit leakage component

Info

Publication number: GB2489337A
Application number: GB1207522.2A
Authority: GB
Inventors: Markus Nentwig
Original assignee: Renesas Mobile Corp
Current assignee: Renesas Electronics Corp
Priority date: 2011-09-16
Filing date: 2011-09-16
Publication date: 2012-09-26
Anticipated expiration: 2031-09-16
Also published as: GB201116090D0; GB2489337B; GB2494695B; GB201207522D0; GB2494695A

Abstract

The present invention mitigates effects of alias responses in a transceiver by selecting a sampling rate 216â of an analogue-to-digital converter (ADC) to place an alias response 214â of an unwanted signal component 210 to a frequency range which is substantially non-overlapping with a wanted signal component 200 of the receiver. The unwanted signal component may be introduced by transmit leakage. Crucially, the selection of the sampling rate takes into account the maximum sampling rate of the ADC (step 408, Fig. 4). The maximum sampling rate is determined by the transceiver based on the determination of the degree of correctness of a conversion result of the ADC at a current conversion rate. The degree of correctness may be indicated by the successful completion of a successive approximation step within and ADC conversion cycle, or by a signal quality indicator associated with the conversion result.

Description

Receiver

Technical Field

The present invention broadly relates to wireless receivers that support cellular standards such as LTE, triple-carrier WCDMA, for instance. More particularly, but not exclusively, the invention relates to the operation of an analog-to-digital convertor comprised in such a receiver.

Background

Full duplex radio frequency (RF) transceivers are capable of transmitting and receiving radio signals simultaneously at different frequencies. Figure 1 shows a transceiver 100 that transmits and receives radio frequency signals through one or more connected antennas 102 and connects via digital interfaces to a modulator / demodulator (modem) 140. Transceiver 100 and modem 140 may be integrated together with display 182, keypad 184, loudspeaker 186, microphone 188 and chipset into a mobile wireless device 189 such as a mobile phone. Other applications of radio frequency transceivers include use in base stations or machine-to-machine communications such as vending machines or cash registers, for example.

Transceiver 100 comprises a transmitter and a receiver. The receiver processes a received radio frequency signal that is picked up by antenna 102 and converts it to a down-sampled received signal 138. The received radio frequency signal comprises a wanted signal component, for example encoded speech data in a voice call that is decoded and sent to loudspeaker 186. The transmitter converts a digital data stream that may for example encode voice data from microphone 188 to a radio frequency signal that is transmitted by antenna 102.

In the receiver, a radio frequency input signal from antenna 102 is coupled to duplex filter 108, where only a predetermined receive band frequency range passes through to receive path signal 110. Receive path signal 110 is amplified by low-noise amplifier 112 and down-converted into baseband signal 126 by receive path mixer 114 using receiver local oscillator signal 116.

Receiver local oscillator signal 116 is generated at a received channel frequency by receiver synthesizer 118 based on a reference clock 120, and may comprise an in-phase component and a quadrature component.

Receive path mixer 114 may implement quadrature down-conversion using a pair of mixers, providing an in-phase and a quadrature component of baseband signal 126.

Baseband signal 126 is filtered by analog baseband filter 128, and the resulting filtered baseband signal 130 is sampled by analog-to-digital converter (ADC) 132 using an ADC sampling clock signal 170 that is provided by ADC sampling clock generator 172 at an ADC conversion rate, resulting in sampled received signal 134.

Analog baseband filter 128 may comprise an in-phase branch and a quadrature branch. Also ADC 132 may comprise an in-phase branch and a quadrature branch.

A first sample-rate converter 136 converts sampled received signal 134 into down-sampled received signal 138 at a lower sampling rate. Down-sampled received signal 138 is provided to modem 140.

In the transmitter, digital transmit signal 145 is provided by modem 140 to transceiver 100, where it is converted to a higher sample rate in second sample-rate converter 146, converted to an analog signal in digital-to-analog converter (DAC) 148 using a DAC sampling clock signal that is provided by DAC sampling clock generator 162, low-pass filtered by transmit baseband filter 150 into transmit baseband signal 152, up-converted to radio frequency by transmit mixer 154 using a transmitter local oscillator signal, and amplified by transmit amplifier 158 resulting in transmit signal 106. Transmit signal 106 is coupled by the duplex fiher 108 to antenna 102.

The transmitter local oscillator signal is generated at a transmitted channel frequency by transmit synthesizer 156 from reference clock 120 and may comprise an in-phase and a quadrature component.

Reference clock 120 may be generated by a reference crystal oscillator 122.

Reference crystal oscillator 122 may be connected to a temperature compensation unit 124. Temperature compensation unit 124 may comprise a temperature sensor that can be queried through bus interface 190a, and offset circuitry for reference crystal oscillator 122 that can be controlled through bus interface 1 90a, for example by CPU 192. Temperature compensation unit 124 may also autonomously measure the temperature and apply offset correction to reference crystal oscillator 122.

The transmit signal 106 is generated at a sufficiently high power level for transmission, for example 24 dBm at the antenna 102. A part of transmit signal 106 S leaks into the receive path signal 110 due to unwanted coupling mechanism 160, resulting in an unwanted signal component known as "transmit leakage". Unwanted coupling mechanism 160 may be caused by finite attenuation of duplex filter 108 or parasitic coupling between lines on a printed wiring board, for example. The transmit leakage is processed by the receive path, appearing at the input of analog-to-digital converter 132 at a frequency offset relative to the wanted signal component.

Depending on the frequency offset and the ADC conversion rate, the transmit leakage may result in an alias component created by ADC 132.

Figure 2a shows a spectrum of signals at the input of analog baseband filter 128 in Figure 1 on a frequency axis. A wanted signal component 200 falls into a pass-band 202 of a frequency response 204 of analog baseband filter 128 in Figure 1. A transmit leakage component 206 is attenuated by a stop-band gain 208 of frequency response 204.

Figure 2b shows the output of analog baseband filter 128 which appears as input signal to ADC 132. Even after attenuation by analog baseband filter 128, the attenuated transmit leakage component 210 still carries considerably higher power than wanted signal component 200 and substantially overlaps alias response 212 around a conversion rate 216. Alias response 212 is caused by sampling within ADC 132, causing signal components near the Nyquist frequency to fold back and appear as replicas in the sampled signal. The resulting alias component 214 overwhelms the weak wanted signal component 200 and disrupts reception.

Figure 2c shows a first solution, where analog baseband filter 128 implements a higher order frequency response 204' with an increased stop-band attenuation 208'.

In Figure 2d, the attenuated transmit leakage component 210' appears at such a low power level due to the increased stop-band attenuation 208' that its alias component 214' in Figure 2d does not significantly deteriorate reception. Disadvantages to using a higher order frequency response are an increased current consumption of analog baseband filter 128 and an increased sensitivity of a higher order analog baseband filter to process and temperature variations that may lead to a general reduction in the received signal quality at modem 140.

Figure 2e and 2f illustrate a second solution, where the conversion rate 216" has been increased to move the alias response 212" towards higher frequencies, avoiding substantial overlap with attenuated transmit leakage component 210. The resulting alias component 214" occupies a different frequency range than the wanted signal component 200 and can be separated by a later processing stage using digital filtering, for example. In Figure 2f, alias component 214" and wanted signal component 200 are substantially non-overlapping. A disadvantage of the solution is that it is difficult or impossible to guarantee correct operation of the ADC at the increased conversion rate 216" under all conditions, as Figure 2g illustrates in the following.

Figure 2g shows the achievable maximum sampling rate of an ADC, such as ADC 132 in Figure 1, depending on variations of the semiconductor process and temperature.

Transceiver 100 in Figure 1 may be integrated partly or in whole in a radio frequency integrated circuit (RFIC) on a semiconductor process such as a 32 nm CMOS (complementary metal-oxide-semiconductor) process. Typically, duplex filter 108 and transmit amplifier 158, also known as "power amplifier", may be connected as external components to the RFTC.

The parameters of the semiconductor process may vary considerably as a result of many contributing factors, for example the production batch, operating temperature, circuit aging and even the location of each RFIC die on a CMOS production wafer. Coping with the expected parameter variations is a significant challenge in RFIC circuit design, where the goal is to design circuitry that works reliably for the widest possible range of parameter variations. ADC 132 is among the most challenging circuit blocks to design, and it may be impossible to achieve a sufficiently high conversion rate (also known as sampling rate) over all parameter variations. The statistic distribution of parameter variations tends to result in a bell-shaped, long-tailed probability curve for circuit performance that forces designers to rely on a rather low guaranteed conversion rate, while the maximum conversion rate that can be achieved with ADC 132 in the vast majority of cases is markedly higher.

Trace 250 in Fig. 2g illustrates the guaranteed conversion rate of an ADC, which is near 52 MHz. In comparison, the "nominal" performance in trace 252 that can be reached by the majority of manufactured ADCs, is over 58 MHz at room temperature, which is a 10 % increase over guaranteed performance. Since the ADC is among the most difficult components to design, a 10% increase in performance is valuable and may notably improve the performance of the receiver. An "outstanding" manufactured ADC achieves the 58 MHz conversion rate over the whole temperature range, according to trace 254 and is capable of even higher rates at room temperature.

Conventionally, radio transceivers are designed for the guaranteed minimum performance of the components, for example based on trace 250 in Fig. 2g. Since the majority of manufactured ADCs will be able to perform better under most circumstances (room temperature), this is inefficient.

Summary

The present invention generally introduces a method of mitigating effects of alias responses in a transceiver comprising a transmitter and a receiver, the receiver comprising an analog-to-digital converter.

According to a first aspect, the present invention provides a method of operating an analog-to-digital converter of a transceiver comprising a transmitter and a receiver, the receiver comprising said analog-to-digital converter (132), the method comprising: determining a maximum conversion rate of the analog-to-digital converter, wherein determining a maximum conversion rate comprises determining the correctness of a conversion result of the analog-to-digital converter (132) at a current conversion rate; and selecting a conversion rate of the analog-to-digital converter, based on the determined maximum conversion rate and a frequency of an unwanted signal component of the receiver, such that the selected conversion rate places an alias response of the unwanted signal component to a frequency range which is substantially non-overlapping with a wanted signal component of the receiver.

According to another aspect, the present invention provides an apparatus comprising: a processing unit, a transmitter and a receiver, the receiver comprising an analog-to-digital converter and the processing unit being configured to: determine a maximum conversion rate of the analog-to-digital converter, wherein determining a maximum conversion rate comprises determining the correctness of a conversion result of the analog-to-digital converter (132) at a current conversion rate; and select a conversion rate of the analog-to-digital converter (132) based on the determined maximum conversion rate and a frequency of an unwanted signal component of the receiver, such that the selected conversion rate places an alias response of the unwanted signal component to a frequency range which is substantially non-overlapping with a wanted signal component of the receiver.

According to yet another aspect of the invention, the present invention provides a computer program product comprising program code means arranged, when executed by a processing unit of an apparatus comprising the processing unit, a transmitter and a receiver, the receiver comprising an analog-to-digital convertor, to: determine a maximum conversion rate of the analog-to-digital converter, wherein determining a maximum conversion rate comprises determining the correctness of a conversion result of the analog-to-digital converter (132) at a current conversion rate; and select a conversion rate of the analog-to-digital converter based on the determined maximum conversion rate and a frequency of an unwanted signal component of the receiver, such that the selected conversion rate places an alias response of the unwanted signal component to a frequency range which is substantially non-overlapping with a wanted signal component of the receiver.

Brief Description of the Drawings

Fig. 1 is a block diagram that illustrates a general structure of a radio frequency transceiver, comprising a transmitter and a receiver, the receiver comprising an analog-to-digital converter; Figs. 2a-2f are frequency domain graphs that illustrate aliasing processes in an analog-to-digital converter; Fig. 2g is a graph that illustrates the achievable maximum sampling rate of an ADC depending on variations of the semiconductor process and temperature; Fig. 3 is a flowchart of a method for selecting a conversion rate of an ADC as an embodiment of the invention; Fig. 4 is a detailed flowchart of a method for selecting the conversion rate; Fig. 5 is a flowchart of a method for determining the maximum conversion rate based on temperature; Fig. 6 is a flowchart of a method to determine a maximum conversion rate; and Figs. 7a is a flowchart of a method to determine correctness of a conversion result and Figs. 7b and 7c are timing diagrams that illustrate internal processes of an analog-to-digital converter.

Detailed Description

Reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings.

Embodiments of the present invention relate to a method, an apparatus and a computer program product for selecting a conversion rate for an analog-to-digital converter. The conversion rate selection is performed to operate the analog-to-digital converter at an advantageous conversion rate that is below a maximum conversion rate, which may change over time. Embodiments of the invention operate to mitigate effects of alias responses in a transceiver comprising a transmitter and a receiver, the receiver comprising such an analog-to-digital converter.

Figure 3 illustrates a flow chart of a method according to an embodiment of the invention. In one example embodiment, the method is applied by CPU 192 in radio transceiver 100 of Figure 1. CPU 192 may initiate the method as a response to a change in radio resource allocation that is signalled by modem 140 via digital bus interface 190d to CPU 192. The change in radio resource allocation may comprise a change in a transmission or reception bandwidth allocation, a change in transmission or reception radio channel, or a change in a transmission or reception band, for example. An example of transmission and reception bands is WCDMA band "I", where the transmission band extends from 1920 MHz to 1980 MHz and the reception band extends from 2110 IVIHz to 2170 MHz. In one example embodiment, CPU 192 initiates method 300 when a change in a measured temperature exceeds a hysteresis threshold relative to an earlier measured temperature.

At operation 310, a maximum conversion rate of an analog-to-digital converter is determined. In one example embodiment, a maximum conversion rate of ADC 132 in transceiver 100 of Figure 1 is determined. At operation 320, a frequency of an unwanted signal component is determined. In an example embodiment, the unwanted signal component is transmit leakage from transmit signal 106 in transceiver 100 of Figure 1, and the frequency of the unwanted signal component is a difference between a transmitted channel frequency and a received channel frequency that are utilized by the transceiver 100. At operation 330, such a conversion rate is selected which does not exceed the determined maximum conversion rate, so that an alias response of the unwanted signal component does not substantially overlap with the wanted signal component regarding their frequency bands.

Figure 4 shows a flowchart of a method 400 for selecting a conversion rate. In one example embodiment, method 400 implements operation 330 of Figure 3.

At operation 402, an operating band of the transceiver is determined. For example, the operating band may be band VIII in WCDMA/HSDPA operation, according to technical specification 3GPP TS 25.101. Thereafter, at operation 406, a minimum alias-free conversion rate is determined. In one embodiment of the invention, the minimum alias-free conversion rate is determined as rmjp alias = + BWJ + BWJ, where fDuplex is an absolute value of a duplex spacing, BW is a one-sided bandwidth of the transmitted signal that is located in frequency on the side that is facing towards the received channel frequency, and BWJ is a one-sided bandwidth of the received signal that is located in frequency facing towards the transmitted channel frequency. For example, in WCDMA band VIII, both BWJ and BWJ may be set to 2 MHz, and fDlei may be set to 45 MHz.

In operation 408, a usable rate r is searched which is greater or equal than the minimum alias-free conversion rate, while not exceeding the maximum conversion rate. Searching a usable rate may also exclude rates that are known to result in unwanted spurious tones, for example caused by a harmonic of the rate falling into a receive channel bandwidth.

At operation 410, the execution of the example procedure is divided between two branches, depending on whether or not a usable rate r is found. If a usable rate is found, the usable rate is configured at operation 412 as the conversion rate for the clock of an analog-to-digital converter. In one embodiment of the invention, the usable rate is configured to ADC sampling clock generator 172 in transceiver 100 of Figure 1. Execution continues at operation 414, where an analog filter is configured to realize a low-order frequency response. In one embodiment of the invention, analog baseband filter 128 in transceiver 100 of Figure 1 is configured as a 3I order response and the process ends.

If, on the other hand, a usable rate r is not found, execution branches from operation 410 to operation 416 instead. At operation 416, a maximum alias-free conversion rate rmax,aljas is determined. In an example embodiment, the maximum alias-free conversion rate is determined as rm = fDuplex + BW7ç + BWJ, where BWJç is a one-sided bandwidth of the transmitted signal which is located in frequency on the side facing away from the received channel frequency, and B W is a one-sided bandwidth of the received signal which is located in frequency facing away from the transmitted channel frequency. For example, in WCDMA band VIII, both BWJ and BWç may be set to 2 MHz, and fDup/ex may be set to 45 MHz.

In operation 418, the maximum alias-free conversion rate is compared against a required rate rreq. The required rate may be a predetermined constant which depends on the operating band. In one example embodiment, the required rate is 38 MHz for WCDMA band VIII operation. If the determined maximum alias-free conversion rate is greater than or equal to the required rate, the maximum alias-free conversion rate is configured as a conversion rate to an analog-to-digital converter and execution continues at operation 414. If, on the other hand, the determined maximum alias-free conversion rate is below the required rate, execution continues at operation 422, where the required rate is configured as the conversion rate to the analog-to-digital converter. In operation 424, the analog filter is configured to realize a higher-order frequency response and the process ends. In one example embodiment, analog baseband filter 128 in transceiver 100 of Figure 1 is configured to a 5th order response.

Figure 5 illustrates a method 500 for determining a maximum conversion rate.

In one example embodiment, method 500 implements operation 310 in Figure 3.

At first in the method of 500, a temperature T of the ADC is determined in operation 510. The ADC occupies a finite area on a semiconductor substrate, and a temperature gradient will be present in all three dimensions. Therefore, any temperature measurement can reflect the physical reality only to a limited degree of accuracy. For example, temperature can be measured with high accuracy using a sensor located on the semiconductor die near the ADC, or with somewhat lower accuracy using a sensor located close to the RFIC component on a printed wiring board (PWB). Thus, it may be stated that a temperature of the ADC can be determined by measuring a temperature at a location close to the ADC. In an example embodiment, the temperature of the ADC is measured using a temperature sensor that forms part of temperature compensation unit 124 for reference crystal oscillator 122 of transceiver 100 in Figure 1. CPU 192 may request a temperature reading via bus interfaces 190e and 190a from temperature compensation unit 124. Also, temperature may be measured by a sensor which is located on a RFIC or requested from chipset

180, for example.

In operation 520, the maximum conversion rate is determined based on the temperature T. The maximum conversion rate may be determined by interpolating in temperature using interpolation coefficients. In one example embodiment, the RFIC classifies its process parameters, for example by measuring a RC time constant, or determining the frequency of a test oscillator into one of the three categories "outstanding", "nominal", or "guaranteed performance", and looks up the interpolation coefficients based on the classification of the process parameters. This is already illustrated in Figure 2g. In one example embodiment of the invention, the maximum conversion rate is determined as a predetermined constant if temperature exceeds a threshold.

Figure 6 illustrates another method 600 to determine a maximum conversion rate of an ADC. Method 600 may implement operation 310 of Figure 3 as an embodiment of the invention.

At operation 610 of the method, a maximum conversion rate estimate is initialized, for example to a worst-case conversion rate which is guaranteed by the manufacturer of the ADC. At operation 620, a loop iterates over a set of possible operation rates. The set of possible rates may be rates that can be divided from a high frequency clock using integer division factors. Rates may be iterated in an increasing order. At operation 630, the iterated rate is configured as conversion rate to an ADC.

Thereafter, in operation 640, the correctness of a conversion result from the ADC is tested. In one example embodiment, the correctness of the conversion result is determined by operating the receiver on a known test signal (for example generated by the transmitter in "loop-back testing"). In one example embodiment of the invention, the correctness of the conversion resuh is determined by comparing a signal quality indicator of the down-sampled received signal 138 in Figure 1 against a predetermined threshold. The signal quality indicator may be a bit error rate (BER) provided by modem 140, and determining the correctness of the conversion result returns a positive test resuh if the bit error is below a predetermined threshold, or otherwise, a negative test result. The signal quality indicator may be an error vector magnitude (EVM) provided by modem 140, and determining correctness of the conversion result may return a positive test result if the EVM in units of dB is below a predetermined threshold or, otherwise, a negative test result is returned. In operation 650, the maximum conversion rate estimate is updated to the iterated rate if the conversion result was found correct.

Fig. 7a illustrates a flowchart of a method 700 according to an embodiment of the invention. Method 700 may implement operation 630 in method 600 of Figure 6.

At operation 710 of the method 700, the successifil completion of an approximation step in an analog-to-digital converter is tested. The analog-to-digital converter may be a successive-approximation (SAR) ADC. The tested approximation step may be the final approximation step of a series of approximation steps. If successful completion is determined, operation continues at operation 720, where a positive test result is returned, indicating correctness of the conversion result. If successful completion is not determined, operation continues instead at operation 730, where a negative test result is returned, further indicating failure to convert correctly.

For illustration, Fig. 7b shows a series of successive approximation steps in a SAR ADC. ADC sampling clock signal 170 initiates a new conversion cycle at each leading edge and triggers a sequence of conversion steps 702, 704, 706 leading to the final step 708. Upon completion of step 702, step 704 is triggered using asynchronous logic. The time for each step to converge depends on the temperature of the ADC, therefore an ADC may be able to achieve only a lower maximum conversion rate when temperature increases.

Fig. 7c shows the conversion process at an elevated temperature. The sequence of conversion steps 702... 708 succeeds at room temperature in Fig. 7b, since conversion step 708 concludes before the start of the next conversion cycle 710. In Fig. 7c, the longer duration of conversion steps 702', 704', 706', ..., 708' at the elevated temperature causes the conversion process to exceed the cycle length of ADC sampling clock signal 170. Thus, conversion fails and returns an incorrect conversion result.

In one example embodiment of the invention, the ADC determines an estimate of the maximum conversion rate by measuring a remaining time 750 in Fig. 7b between the end of an approximation step in a SAR ADC and the end of a conversion cycle. The maximum conversion rate may be estimated by scaling the current conversion rate with the ratio of remaining time 750 to conversion cycle length 752.

The inventive idea comprises a computer program product which is adapted to perform applicable operations when executed in a data-processing device such as a processing unit or a CPU of the system, for instance. Such a processor may thus be the processing unit of the transceiver itself or control logic available internally in the system or remotely in the network. The computer program product may be embodied in a computer-readable medium.

The advantage of the invention is that the alias response effect on the received signal is clearly mitigated and such an effect is achieved with notably low power consumption.

It will be obvious to a person skilled in the art that with the advancement of technology, the basic idea of the invention may be implemented in various ways. The invention and its embodiments are thus not limited to the examples described above; instead they may vary within the scope of the claims.

Claims

Claims 1. A method of operating an analog-to-digital converter (132) of a transceiver (100) comprising a transmitter and a receiver, the receiver comprising said analog-to-digital converter (132), the method comprising: determining a maximum conversion rate of the analog-to-digital converter (132), wherein determining a maximum conversion rate comprises determining the correctness of a conversion result of the analog-to-digital converter (132) at a current conversion rate; and selecting a conversion rate of the analog-to-digital converter (132), based on the determined maximum conversion rate and a frequency of an unwanted signal component (210, 210') of the receiver, such that the selected conversion rate (216') places an alias response (214) of the unwanted signal component to a frequency range which is substantially non-overlapping with a wanted signal component (200) of the receiver.
2. The method according to claim 1, wherein determining the correctness of the conversion result comprises determining successful completion of a successive approximation step (708, 708') within an analog-to-digital conversion cycle (752).
3. The method according to claim 1, wherein determining the correctness of the conversion result comprises determining a signal quality indicator of the conversion result.
4. The method according to claim 1, further comprising configuring an analog filter (128) of the receiver as a filter having a lower order frequency response.
5. The method according to claim 1, wherein the unwanted signal component (210, 210') at a known frequency comprises transmit leakage from the transmitter.
6. An apparatus comprising: a processing unit (192), a transmitter and a receiver, the receiver comprising an analog-to-digital converter (132) and the processing unit (192) being configured to: determine a maximum conversion rate of the analog-to-digital converter (132), wherein determining a maximum conversion rate comprises determining the S correctness of a conversion result of the analog-to-digital converter (132) at a current conversion rate; and select a conversion rate of the analog-to-digital converter (132) based on the determined maximum conversion rate and a frequency of an unwanted signal component (210, 210') of the receiver, such that the selected conversion rate (216') places an alias response (214) of the unwanted signal component to a frequency range which is substantially non-overlapping with a wanted signal component (200) of the receiver.
7. The apparatus according to claim 6, wherein the processing unit (192) is configured to determine the correctness of the conversion result by determining successful completion of a successive approximation step (708, 708') within an analog-to-digital conversion cycle (752).
8. The apparatus according to claim 6, wherein the processing unit (192) is configured to determine the correctness of the conversion result by determining a signal quality indicator of the conversion result.
9. The apparatus according to claim 6, further comprising an analog filter (128) of the receiver configured as a filter having a lower order frequency response.
10. The apparatus according to claim 6, wherein the unwanted signal component (210, 210') at a known frequency comprises transmit leakage from the transmitter.
11. A computer program product comprising program code means arranged, when executed by a processing unit of an apparatus comprising the processing unit, a transmitter and a receiver, the receiver comprising an analog-to-digital convertor, to: determine a maximum conversion rate of the analog-to-digital converter (132), wherein determining a maximum conversion rate comprises determining the correctness of a conversion result of the analog-to-digital converter (132) at a current conversion rate; and select a conversion rate of the analog-to-digital converter (132) based on the determined maximum conversion rate and a frequency of an unwanted signal component (210, 210') of the receiver, such that the selected conversion rate (216') places an alias response (214) of the unwanted signal component to a frequency range which is substantially non-overlapping with a wanted signal component (200) of the receiver.
12. The computer program product according to claim 11, wherein the computer program product is stored on a computer readable medium (194).