US8541252B2 - Abbreviated epitaxial growth mode (AGM) method for reducing cost and improving quality of LEDs and lasers - Google Patents

Abbreviated epitaxial growth mode (AGM) method for reducing cost and improving quality of LEDs and lasers Download PDF

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US8541252B2
US8541252B2 US12/972,418 US97241810A US8541252B2 US 8541252 B2 US8541252 B2 US 8541252B2 US 97241810 A US97241810 A US 97241810A US 8541252 B2 US8541252 B2 US 8541252B2
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sapphire
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Nelson Tansu
Helen M. Chan
Richard P. Vinci
Yik-Khoon Ee
Jeffrey Biser
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Lehigh University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
    • C30B25/183—Epitaxial-layer growth characterised by the substrate being provided with a buffer layer, e.g. a lattice matching layer
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • C30B29/406—Gallium nitride
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02428—Structure
    • H01L21/0243—Surface structure
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate

Definitions

  • LED lighting sources have huge advantages over conventional sources in terms of cost of use and impact on energy production, but high fabrication cost and limited brightness have limited adoption of solid state lighting outside certain niche applications such as traffic lights.
  • Sapphire is most commonly used as the substrate for nitride light emitting diodes (LEDs) in solid state lighting due to its physical robustness and high-temperature stability.
  • a low-dislocation density GaN semiconductor template on sapphire is important for high-efficiency and reliable nitride light-emitting diodes (LEDs) in solid state lighting applications.
  • MOVPE metalorganic vapor phase epitaxy
  • the low temperature GaN buffer layer is etched-back by employing H2 at high temperature to form micron-sized GaN islands.
  • the use of intentional delay of the nucleation island coalescence (recovery) reduces threading dislocation density.
  • the etch-back and recovery process employed in conventional MOVPE of GaN on sapphire substrate adds 30 to 45 minutes in the GaN growth time, which increases the cost of epitaxy process.
  • the threading dislocation density of conventional MOVPE grown GaN template is still relatively high in the range of 10 8 -10 10 cm ⁇ 2 .
  • Several techniques have been utilized to reduce the threading dislocation density in MOVPE grown GaN template, such as lateral epitaxial overgrowth (LEO), pendeo epitaxy, and cantilever epitaxy. These approaches have led to reduction in the dislocation density of GaN template down to 10 6 -10 7 cm ⁇ 2 , however the high quality material is limited in the narrow 2-3 ⁇ m stripe regions.
  • a GaN template of MOVPE is grown on a nano-patterned AGOG c-plane sapphire substrate by employing a novel process referred to as an abbreviated GaN growth mode (AGGM).
  • AGGM abbreviated GaN growth mode
  • Nucleation growth evolution studies of GaN using AGGM on nano-patterned AGOG sapphire were performed.
  • the growths of InGaN-based LEDs on both AGGM-based GaN/patterned sapphire and conventional GaN/planar sapphire templates were carried out.
  • the device characteristics of III-Nitride LEDs grown on both templates were compared and analyzed.
  • Cross-sectional transmission electron microscopy (CS-TEM) measurements were performed on both samples.
  • the invention involves first fabricating or acquiring a sapphire substrate with an array of surface dots that are sub-micrometer in scale, and have a dot-to-dot pitch that is also sub-micrometer in scale. Second, the AGGM growth sequence on the patterned surface consists of deposition of a thin low-temperature GaN layer followed immediately by deposition of a thick high-temperature GaN layer.
  • FIG. 1 is a schematic of the fabrication process of nano-patterned AGOG sapphire of an embodiment of the invention
  • FIG. 2 are scanning electron micrographs of (a) aluminum nano-structure array after lift-off, and (b) aluminum nano-structure array conversion to single crystal Al 2 O 3 after two-stage anneal;
  • FIG. 3 are SEM images of (a) nano-patterned and planar sapphire regions with 15 nm GaN buffer layer, and (b) the nano-patterned sapphire region with 15 nm GaN buffer layer (higher magnification);
  • FIG. 4 are SEM images of (a) nano-patterned and planar sapphire regions with 15 nm GaN buffer layer and 3 min growth of high-temperature GaN, and (b) the nano-patterned sapphire with 15 nm GaN buffer layer and 3 min growth of high-temperature GaN (higher magnification);
  • FIG. 5 are SEM images of (a) nano-patterned and planar sapphire regions with 15 nm GaN buffer layer and 0.1 ⁇ m thick high-temperature GaN, and (b) nano-patterned and planar sapphire regions with 15 nm GaN buffer layer and 0.25 ⁇ m thick high-temperature GaN;
  • FIG. 6 is a graph showing room temperature CW light output power as a function of injection current of In 0.15 Ga 0.85 N QW LEDs grown on three comparison templates (LEDs #1, #2, and #3); and
  • the nano-patterning of a sapphire substrate was fabricated by using a novel AGOG process which converts metallic aluminum (Al) into single crystal sapphire via a two stage annealing process.
  • the acronym “AGOG” is coined from the process of converting Al into crystalline Al 2 O 3 nanostructures: Deposition of Aluminum, Growth of Oxide, and Grain growth.
  • the process schematics of an embodiment of the AGOG sapphire nano-patterning are shown in FIG.
  • PMMA polymethyl methacrylate
  • FIGS. 2( a ) and 2 ( b ) The scanning electron microscopy (SEM) micrographs of the aluminum nanostructures before and after the two annealing stages in the AGOG conversion process are shown in FIGS. 2( a ) and 2 ( b ), respectively. As shown in FIGS. 2( a ) and 2 ( b ), good shape retention is achieved in the nanostructures after the two annealing processes.
  • EBSD electron backscatter diffraction
  • the growth of a conventional GaN template on c-plane planar sapphire substrate was performed as a control sample.
  • the control sample consists of n-doped GaN template grown on planar c-plane sapphire by employing the conventional method.
  • the abbreviated GaN growth mode was carried out on nano-patterned AGOG sapphire substrate.
  • the details of the growth precursors used and the molar flow rate of precursors can be found in Y. K. Ee, J. M. Bider, W. Cao, H. M. Chan, R. P. Vinci, N. Tansu, IEEE J. Sel. Top. Quantum Electron , 15 (2009) 1066-1072.
  • the LEDs active region and p-doped GaN were grown on the conventional GaN template, and the AGOG GaN template in the same epitaxy run.
  • the InGaN-based LEDs active region comprises of four periods of In 0.15 Ga 0.85 N/GaN (2.5 nm/12 nm) quantum wells (QWs).
  • T g 740° C.
  • the growth temperature was ramped up to 970° C. for the growth of p-doped GaN.
  • the n-doping level and p-doping level of GaN was measured as 4.0 ⁇ 10 18 cm ⁇ 3 and 5.0 ⁇ 10 17 cm ⁇ 3 , respectively.
  • T g 535° C.
  • the low temperature GaN nucleated uniformly across the entire region.
  • the nucleation process on the nano-patterned AGOG sapphire region is very different from that observed on planar sapphire.
  • the low temperature GaN preferentially nucleates around the base of the AGOG nano-patterns.
  • the AGOG nano-patterns on sapphire altered the surface energy, which may have caused low temperature GaN buffer layer to replicate the nano-patterns by preferentially growing surrounding the existing AGOG nano-patterns.
  • FIG. 4( a ) The SEM image of the GaN materials grown on the nano-patterned AGOG region and planar sapphire region is shown in FIG. 4( a ).
  • FIG. 4( a ) high-temperature GaN islands preferentially grow on the patterned AGOG sapphire due to the higher density of the low-temperature GaN nucleated on the nano-patterned AGOG region. Thus, this result in higher density of high temperature GaN islands grown on the nano-patterned AGOG region.
  • FIG. 5( a ) The growths of 0.1 ⁇ m thick ( FIG. 5( a )) and 0.25 ⁇ m thick ( FIG. 5( b )) high temperature GaN (by abbreviated growth mode) were conducted on nano-patterned AGOG and planar sapphire samples.
  • FIG. 5( a ) the preferential growth of high temperature GaN on nano-patterned AGOG region was evident as the GaN has started to coalesce at much earlier stage, as compared to the coalescence for GaN grown on the planar sapphire. From FIG.
  • FIG. 6 shows the light output power as a function of injection current for the 445 nm emitting InGaN QWs LEDs grown on different GaN templates as follows: GaN template grown by the abbreviated growth mode on nano-patterned AGOG sapphire (LED-1), GaN template grown by a conventional technique on planar sapphire (LED-2), and GaN template grown by the abbreviated growth mode on planar sapphire (LED-3).
  • the LED devices with an area of 1.25 ⁇ 10 ⁇ 3 cm 2 were measured under continuous wave (CW) conditions at room temperature.
  • the output power and efficiency of LED-1 employing AGGM growth on patterned sapphire
  • For the LED-3 (without the etch-back and recovery process during the GaN template growth on planar sapphire), its output power was measured as 28% lower than that of the conventional LED-2.
  • FIGS. 7( a ) and 7 ( b ) The cross-sectional TEM micrographs of the LED samples grown on nano-patterned AGOG substrate with the abbreviated growth mode (LED-1) and conventional GaN template (LED-2) are shown in FIGS. 7( a ) and 7 ( b ), respectively.
  • Measurements indicate that the threading dislocation density of the GaN grown on nano-patterned AGOG sapphire and GaN grown on planar sapphire was 3 ⁇ 10 7 cm ⁇ 2 and 1 ⁇ 10 9 cm ⁇ 2 , respectively.
  • the threading dislocation density was approximately two orders of magnitude lower than conventional GaN template.
  • the improvement observed in the output power of LED-1 can be attributed to the enhanced radiative efficiency of the InGaN QWs LEDs, due to a reduction in threading dislocation density in the GaN template grown on nano-patterned AGOG sapphire substrate.
  • GaN abbreviated growth mode on nano-patterned AGOG sapphire substrate lead to reduction in the threading dislocation density in the GaN template.
  • the use of GaN abbreviated growth mode also reduces epitaxy time and cost as this process bypasses the conventional etch-back and recovery process necessary in the growth of conventional GaN on planar sapphire substrates.
  • electron beam patterning of the substrate is impractical as a production tool, other large-scale and low-cost lithography processes such as holography or sol-gel lithography approaches can be used to nano-pattern large batches of substrates.
  • the thermal processing of the substrates can be performed as a batch process at relatively low cost.
  • nano-patterning of the sapphire substrate was conducted by using a novel AGOG process.
  • the abbreviated growth mode comprises of a thin 15 nm low temperature GaN buffer, followed by high temperature GaN growth without the etch-back and recovery process.
  • the GaN growth nucleation studies by employing the abbreviated growth mode were carried out. Our studies indicated that low-temperature GaN buffer layers were preferentially nucleating on the nano-patterned AGOG region, and the growth of high-temperature GaN also showed preferential coalescence at a much earlier stage compared to the high temperature GaN in the planar sapphire region.

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Abstract

The use of an abbreviated GaN growth mode on nano-patterned AGOG sapphire substrates, which utilizes a process of using 15 nm low temperature GaN buffer and bypassing etch-back and recovery processes during epitaxy, enables the growth of high-quality GaN template on nano-patterned AGOG sapphire. The GaN template grown on nano-patterned AGOG sapphire by employing abbreviated growth mode has two orders of magnitude lower threading dislocation density than that of conventional GaN template grown on planar sapphire. The use of abbreviated growth mode also leads to significant reduction in cost of the epitaxy. The growths and characteristics of InGaN quantum wells (QWs) light emitting diodes (LEDs) on both templates were compared. The InGaN QWs LEDs grown on the nano-patterned AGOG sapphire demonstrated at least a 24% enhancement of output power enhancement over that of LEDs grown on conventional GaN templates.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of priority under 35 U.S.C. §119(e) of U.S. Provisional Patent Application No. 61/287,353, filed Dec. 17, 2009, the entire disclosure of which is hereby incorporated herein by reference.
STATEMENT OF GOVERNMENT INTEREST
This invention was made with government support under U.S. Department of Energy (DE-FC26-08NT01581) and US National Science Foundation (ECCS #0701421, and DMR #0705299). The government has certain rights in the invention.
BACKGROUND OF THE INVENTION
A large fraction of the electricity use in the United States is associated with lighting. LED lighting sources have huge advantages over conventional sources in terms of cost of use and impact on energy production, but high fabrication cost and limited brightness have limited adoption of solid state lighting outside certain niche applications such as traffic lights.
Sapphire is most commonly used as the substrate for nitride light emitting diodes (LEDs) in solid state lighting due to its physical robustness and high-temperature stability. A low-dislocation density GaN semiconductor template on sapphire is important for high-efficiency and reliable nitride light-emitting diodes (LEDs) in solid state lighting applications. In conventional metalorganic vapor phase epitaxy (MOVPE) of GaN on a sapphire substrate, the low temperature GaN buffer layer is etched-back by employing H2 at high temperature to form micron-sized GaN islands. The use of intentional delay of the nucleation island coalescence (recovery) reduces threading dislocation density. The etch-back and recovery process employed in conventional MOVPE of GaN on sapphire substrate adds 30 to 45 minutes in the GaN growth time, which increases the cost of epitaxy process.
The threading dislocation density of conventional MOVPE grown GaN template is still relatively high in the range of 108-1010 cm−2. Several techniques have been utilized to reduce the threading dislocation density in MOVPE grown GaN template, such as lateral epitaxial overgrowth (LEO), pendeo epitaxy, and cantilever epitaxy. These approaches have led to reduction in the dislocation density of GaN template down to 106-107 cm−2, however the high quality material is limited in the narrow 2-3 μm stripe regions.
SUMMARY OF THE INVENTION
In this invention, a GaN template of MOVPE is grown on a nano-patterned AGOG c-plane sapphire substrate by employing a novel process referred to as an abbreviated GaN growth mode (AGGM). Nucleation growth evolution studies of GaN using AGGM on nano-patterned AGOG sapphire were performed. The growths of InGaN-based LEDs on both AGGM-based GaN/patterned sapphire and conventional GaN/planar sapphire templates were carried out. The device characteristics of III-Nitride LEDs grown on both templates were compared and analyzed. Cross-sectional transmission electron microscopy (CS-TEM) measurements were performed on both samples. The comparison studies indicated that the use of the abbreviated GaN growth mode leads to at least a two-order reduction in dislocation densities and improved efficiency in LED devices.
The invention involves first fabricating or acquiring a sapphire substrate with an array of surface dots that are sub-micrometer in scale, and have a dot-to-dot pitch that is also sub-micrometer in scale. Second, the AGGM growth sequence on the patterned surface consists of deposition of a thin low-temperature GaN layer followed immediately by deposition of a thick high-temperature GaN layer.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1. is a schematic of the fabrication process of nano-patterned AGOG sapphire of an embodiment of the invention;
FIG. 2. are scanning electron micrographs of (a) aluminum nano-structure array after lift-off, and (b) aluminum nano-structure array conversion to single crystal Al2O3 after two-stage anneal;
FIG. 3. are SEM images of (a) nano-patterned and planar sapphire regions with 15 nm GaN buffer layer, and (b) the nano-patterned sapphire region with 15 nm GaN buffer layer (higher magnification);
FIG. 4. are SEM images of (a) nano-patterned and planar sapphire regions with 15 nm GaN buffer layer and 3 min growth of high-temperature GaN, and (b) the nano-patterned sapphire with 15 nm GaN buffer layer and 3 min growth of high-temperature GaN (higher magnification);
FIG. 5. are SEM images of (a) nano-patterned and planar sapphire regions with 15 nm GaN buffer layer and 0.1 μm thick high-temperature GaN, and (b) nano-patterned and planar sapphire regions with 15 nm GaN buffer layer and 0.25 μm thick high-temperature GaN;
FIG. 6. is a graph showing room temperature CW light output power as a function of injection current of In0.15Ga0.85N QW LEDs grown on three comparison templates (LEDs #1, #2, and #3); and
FIG. 7. shows cross-sectional TEM images taken at g=(0002) for (a) LED sample grown on nano-patterned sapphire with abbreviated growth mode, and (b) LED sample grown on planar sapphire using conventional growth.
 I. NANO-PATTERNING OF AGOG SAPPHIRE SUBSTRATE
The nano-patterning of a sapphire substrate was fabricated by using a novel AGOG process which converts metallic aluminum (Al) into single crystal sapphire via a two stage annealing process. The acronym “AGOG” is coined from the process of converting Al into crystalline Al2O3 nanostructures: Deposition of Aluminum, Growth of Oxide, and Grain growth. The process schematics of an embodiment of the AGOG sapphire nano-patterning are shown in FIG. 1, as follows: (1) Electron-beam patterning of nanostructures on polymethyl methacrylate (PMMA), (2) deposition of 100 nm thick aluminum, (3) aluminum lift-off process leaving behind aluminum nanostructures comprising of an array of hexagons approximately 200 nm wide with center-to-center spacing of 400 nm (in a proof-of-concept experiment, the size of the patterned AGOG region was limited to 1 mm×1 mm; however, the size need not be limited to this experimental value), (4) first stage anneal at 450° C. in air to convert metallic aluminum into polycrystalline oxide, and (5) second stage anneal at 1200° C. in air to induce grain growth of the underlying sapphire single crystal to consume the oxide layer. The scanning electron microscopy (SEM) micrographs of the aluminum nanostructures before and after the two annealing stages in the AGOG conversion process are shown in FIGS. 2( a) and 2(b), respectively. As shown in FIGS. 2( a) and 2(b), good shape retention is achieved in the nanostructures after the two annealing processes. To verify that the converted Al nanostructures were crystalline sapphire, electron backscatter diffraction (EBSD) was conducted. Indexing of the patterns confirmed that the patterned AGOG nanostructures consisted of sapphire with the same orientation as the c-plane (0001) substrate.
II. ABBREVIATED GROWTH MODE ON PATTERNED AGOG SAPPHIRE
The growth of a conventional GaN template on c-plane planar sapphire substrate was performed as a control sample. The control sample consists of n-doped GaN template grown on planar c-plane sapphire by employing the conventional method. A 30 nm thick low temperature (Tg=535° C.) GaN was grown as a buffer layer, which is followed by the H2 etch-back and recovery process. The growth of a high temperature (Tg=1080° C.) n-GaN (thickness=0.28 nm) growth was carried out after the etch-back and recovery process.
The abbreviated GaN growth mode (AGGM) was carried out on nano-patterned AGOG sapphire substrate. In this embodiment of the claimed invention, a 15 nm thick low temperature GaN buffer is grown (Tg=535° C.), followed by the growth of high temperature GaN without the intermediate etch-back and recovery process. The thickness of the high-temperature (Tg=1080° C.) n-GaN layer is 2.8 μm. The details of the growth precursors used and the molar flow rate of precursors can be found in Y. K. Ee, J. M. Bider, W. Cao, H. M. Chan, R. P. Vinci, N. Tansu, IEEE J. Sel. Top. Quantum Electron, 15 (2009) 1066-1072.
To compare the LEDs device performance of different GaN templates, the LEDs active region and p-doped GaN were grown on the conventional GaN template, and the AGOG GaN template in the same epitaxy run. The InGaN-based LEDs active region comprises of four periods of In0.15Ga0.85N/GaN (2.5 nm/12 nm) quantum wells (QWs). After the growth of the active region (Tg=740° C.), the growth temperature was ramped up to 970° C. for the growth of p-doped GaN. The n-doping level and p-doping level of GaN was measured as 4.0×1018 cm−3 and 5.0×1017 cm−3, respectively.
III. NUCLEATION GROWTH EXPERIMENTS
Growth evolution studies of the GaN nucleation on planar and nano-patterned AGOG sapphire substrates were conducted. FIG. 3( a) shows the SEM image of the nano-patterned AGOG region and planar sapphire region after the growth of 15 nm low temperature GaN buffer layer (Tg=535° C.). For the case of planar sapphire, the low temperature GaN nucleated uniformly across the entire region. However, the nucleation process on the nano-patterned AGOG sapphire region is very different from that observed on planar sapphire. Studies indicated that the low-temperature GaN preferentially nucleates on the patterned region with higher density. From FIG. 3( b), it was clear that the low temperature GaN preferentially nucleates around the base of the AGOG nano-patterns. The AGOG nano-patterns on sapphire altered the surface energy, which may have caused low temperature GaN buffer layer to replicate the nano-patterns by preferentially growing surrounding the existing AGOG nano-patterns.
After 3 minutes of high temperature (Tg=1080° C.) GaN growth via abbreviated GaN growth mode, the GaN growth was interrupted. The SEM image of the GaN materials grown on the nano-patterned AGOG region and planar sapphire region is shown in FIG. 4( a). As shown in FIG. 4( a), high-temperature GaN islands preferentially grow on the patterned AGOG sapphire due to the higher density of the low-temperature GaN nucleated on the nano-patterned AGOG region. Thus, this result in higher density of high temperature GaN islands grown on the nano-patterned AGOG region. As shown in FIG. 4( b), studies indicated that the larger single crystal high temperature GaN islands preferentially grow in the valley region of the AGOG nanopatterns during the initial growth stage. The growth of high temperature GaN initiate from the low temperature GaN islands, indicating that the low temperature GaN in the AGOG nano-patterened region could have re-arranged its position from surrounding the AGOG nano-patterns to the regions between nano-patterns during the high temperature ramp up for the GaN growth. The re-arrangement of low temperature GaN during high temperature ramp up was also observed in high temperature TEM experiments.
Previous works have indicated that the threading dislocation bent when the micron-sized GaN island coalesced. Note that the nano-scale GaN islands formed in the initial growth of high-temperature GaN on patterned sapphire (FIG. 4( b)) preferentially nucleate on the nano-patterned AGOG region, thereby providing more GaN islands for coalescence. The increased interfaces for GaN island coalescence enhance the probability for the threading dislocations to bend, improving the GaN material quality.
The growths of 0.1 μm thick (FIG. 5( a)) and 0.25 μm thick (FIG. 5( b)) high temperature GaN (by abbreviated growth mode) were conducted on nano-patterned AGOG and planar sapphire samples. The surface morphologies of the GaN material grown on these two regions were very different. In FIG. 5( a), the preferential growth of high temperature GaN on nano-patterned AGOG region was evident as the GaN has started to coalesce at much earlier stage, as compared to the coalescence for GaN grown on the planar sapphire. From FIG. 5( b), it can be observed that at 0.25 μm the high temperature GaN has completely coalesced forming a smooth film on the nano-patterned sapphire, but not on the planar region. The use of the abbreviated growth mode on nano-patterned sapphire provides significant advantage over the conventional approach, as this approach leads to significant cost reduction and epitaxy time.
IV. LEDS CHARACTERISTICS AND TEM RESULTS
FIG. 6 shows the light output power as a function of injection current for the 445 nm emitting InGaN QWs LEDs grown on different GaN templates as follows: GaN template grown by the abbreviated growth mode on nano-patterned AGOG sapphire (LED-1), GaN template grown by a conventional technique on planar sapphire (LED-2), and GaN template grown by the abbreviated growth mode on planar sapphire (LED-3). The LED devices with an area of 1.25×10−3 cm2 were measured under continuous wave (CW) conditions at room temperature. The output power and efficiency of LED-1 (employing AGGM growth on patterned sapphire) exhibited enhancement by 24% in comparison to those of the conventional LED-2. For the LED-3 (without the etch-back and recovery process during the GaN template growth on planar sapphire), its output power was measured as 28% lower than that of the conventional LED-2.
The cross-sectional TEM micrographs of the LED samples grown on nano-patterned AGOG substrate with the abbreviated growth mode (LED-1) and conventional GaN template (LED-2) are shown in FIGS. 7( a) and 7(b), respectively. Measurements indicate that the threading dislocation density of the GaN grown on nano-patterned AGOG sapphire and GaN grown on planar sapphire was 3×107 cm−2 and 1×109 cm−2, respectively. Using nano-patterned AGOG sapphire and abbreviated GaN growth mode, the threading dislocation density was approximately two orders of magnitude lower than conventional GaN template. The improvement observed in the output power of LED-1 can be attributed to the enhanced radiative efficiency of the InGaN QWs LEDs, due to a reduction in threading dislocation density in the GaN template grown on nano-patterned AGOG sapphire substrate.
The above-described experiments show that GaN abbreviated growth mode on nano-patterned AGOG sapphire substrate lead to reduction in the threading dislocation density in the GaN template. The use of GaN abbreviated growth mode also reduces epitaxy time and cost as this process bypasses the conventional etch-back and recovery process necessary in the growth of conventional GaN on planar sapphire substrates. Although electron beam patterning of the substrate is impractical as a production tool, other large-scale and low-cost lithography processes such as holography or sol-gel lithography approaches can be used to nano-pattern large batches of substrates. Once the large scale nano-patterning can be implemented, the thermal processing of the substrates can be performed as a batch process at relatively low cost. By employing the nano-patterned AGOG sapphire, large area (millimeter to wafer size) of high quality GaN template with lower threading dislocation density can be achieved. The use of high quality GaN template leads to improved internal quantum efficiency and reliability of LEDs.
In conclusion, nano-patterning of the sapphire substrate was conducted by using a novel AGOG process. By employing the nano-patterned AGOG sapphire, the use of GaN abbreviated growth mode could be conducted thereby reducing epitaxy cost and time. The abbreviated growth mode comprises of a thin 15 nm low temperature GaN buffer, followed by high temperature GaN growth without the etch-back and recovery process. The GaN growth nucleation studies by employing the abbreviated growth mode were carried out. Our studies indicated that low-temperature GaN buffer layers were preferentially nucleating on the nano-patterned AGOG region, and the growth of high-temperature GaN also showed preferential coalescence at a much earlier stage compared to the high temperature GaN in the planar sapphire region.
Comparison studies were also conducted on 445 nm emitting InGaN QWs LEDs grown on both patterned and planar sapphire substrates. The LEDs grown on the GaN template on nano-patterned AGOG sapphire with GaN abbreviated growth mode demonstrated 24% improvement in the output power over the LEDs grown on conventional GaN template. The improvement observed in the LEDs devices grown on patterned sapphire substrates can be attributed to the two orders of magnitude reduction in the threading dislocation density observed from the TEM measurements. The use of abbreviated growth mode enables the epitaxy of low-dislocation density GaN on patterned AGOG sapphire substrate, without the need of etch-back and recovery process.
While there has been described herein the principles of the invention, it is to be understood by those skilled in the art that this description is made only by way of example and not as a limitation to the scope of the invention. Accordingly, it is intended by the appended claims, to cover all modifications of the invention which fall within the true spirit and scope of the invention.

Claims (14)

We claim:
1. A method of growing a GaN template on a substrate, comprising:
performing an abbreviated GaN growth mode (AGGM) on a patterned sapphire substrate, said AGGM including:
growing a thin low-temperature GaN layer on said substrate; and
growing a thick high-temperature GaN layer on said thin layer.
2. The method of claim 1, wherein said growing of said thick high-temperature GaN layer is performed immediately following the growing of said thin low-temperature GaN layer.
3. The method of claim 2, wherein said thin low-temperature GaN layer has a thickness in the range of about 10-20 nm.
4. The method of claim 3, wherein said thick high-temperature GaN layer has a thickness in the range of about 0.10-0.30 μm.
5. The method of claim 3, wherein said thick high-temperature GaN layer has a thickness of about 0.25 μm.
6. The method of claim 5, wherein said low-temperature GaN layer is grown at a temperature in the range of about 525-545° C.
7. The method of claim 6, wherein said high-temperature GaN layer is grown at a temperature in the range of about 1070-1090° C.
8. The method of claim 6, wherein said high-temperature GaN layer is grown at a temperature of about 1080° C.
9. The method of claim 6, wherein said patterned sapphire comprises nano-patterned sapphire etched using an AGOG process.
10. The method of claim 5, wherein said low-temperature GaN layer is grown at a temperature of about 535° C.
11. The method of claim 2, wherein said thin low-temperature GaN layer has a thickness of about 15 nm.
12. The method of claim 1, wherein said patterned sapphire comprises nano-patterned sapphire.
13. An LED formed using the following steps:
growing a GaN template on a substrate, comprising:
performing an abbreviated GaN growth mode (AGGM) on a patterned sapphire substrate, said AGGM including:
growing a thin low-temperature GaN layer on said substrate; and
growing a thick high-temperature GaN layer on said thin layer; and
growing an InGaN QWs LED on said GaN template.
14. The method of claim 13, wherein said patterned sapphire comprises nano-patterned sapphire.
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