US8214812B2 - Method of interpreting method bytecode and system operated by the same - Google Patents

Method of interpreting method bytecode and system operated by the same Download PDF

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Publication number
US8214812B2
US8214812B2 US11/582,360 US58236006A US8214812B2 US 8214812 B2 US8214812 B2 US 8214812B2 US 58236006 A US58236006 A US 58236006A US 8214812 B2 US8214812 B2 US 8214812B2
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called
interpreter loop
bytecode
called method
interpreter
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US20070089101A1 (en
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Alexey Romanovskiy
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45504—Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
    • G06F9/45508—Runtime interpretation or emulation, e g. emulator loops, bytecode interpretation

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  • Methods, systems, and computer-readable mediums consistent with the present invention relate to a virtual machine. More particularly, the present invention relates to interpreting a method bytecode in operation of a virtual machine.
  • JAVA is an object-oriented programming language developed by Sun Microsystems, Inc. and is defined by the JAVA language standard.
  • the JAVA virtual machine standard defines a model that can independently execute a JAVA program expressed through an instruction set called bytecode, in a platform.
  • Bytecode can be generated by a JAVA language compiler that converts a program expressed by a JAVA language.
  • a JAVA virtual machine executes a predetermined operation by interpreting the bytecode. Such execution of the JAVA virtual machine consumes a small-space resource such as a memory due to the compactness of the bytecode.
  • the current trend for improving the performance of the JAVA virtual machine is to provide a compiler that converts a JAVA bytecode into a native code to reduce overhead caused by interpretation of bytecode.
  • the interpreter has a loop type structure such as “while” statement.
  • U.S. Patent Publication No. 2004-0088703 discloses a method of generating an interpreter having hierarchical loops, as shown in FIG. 1 .
  • bytecodes frequently executed are identified (S 110 ), and bytecodes not frequently executed are identified (S 120 ).
  • a first interpreter loop is generated to process the bytecodes that are simple to execute and that are frequently executed (S 140 ), and a second interpreter loop is generated to process the other bytecodes (S 150 ).
  • Exemplary embodiments of the present invention may overcome the above disadvantages and other disadvantages not described above.
  • the exemplary embodiments of the present invention are not necessarily required to overcome any of the disadvantages described above, and the exemplary embodiments of the present invention may not overcome any of the problems described above.
  • the appended claims should be consulted to ascertain the true scope of the invention.
  • the present invention provides a method and system which can improve the performance of a bytecode interpretation by analyzing a bytecode of a method frequently called, through a separate loop.
  • a method of interpreting a method bytecode which includes determining whether a called method is a bottleneck method, generating an interpreter loop for the called method if the called method is the bottleneck method, and interpreting a bytecode of the called method using the generated interpreter loop.
  • a method of interpreting a method bytecode which includes determining whether a called method is a bottleneck method, providing an associated interpreter loop for the called method if the called method is the bottleneck method, and interpreting a bytecode of the called method using the provided interpreter loop.
  • a system for interpreting a method bytecode which includes an operating system, an application, and a virtual machine, which is based on the operating system, provides an interface for the application, and interprets a bytecode of a method called from the application so as to convert the interpreted bytecode into a code that can be recognized by the operating system, wherein the virtual machine interprets the bytecode of the called method using an interpreter loop associated with the called method if the called method is a bottleneck method.
  • a computer-readable medium storing instructions for interpreting a method bytecode, the instructions comprising determining whether a called method is a bottleneck method, generating an interpreter loop for the called method if the called method is the bottleneck method, and interpreting a bytecode of the called method using the generated interpreter loop.
  • FIG. 1 is a flowchart illustrating a process of generating an interpreter loop according to the related art
  • FIG. 2 is a view illustrating an example of a pseudo-code that executes bytecodes according to the related art
  • FIG. 3 is a block diagram illustrating the configuration of a system according to an exemplary embodiment of the present invention.
  • FIG. 4 is a block diagram illustrating the construction of an interpreter engine according to an exemplary embodiment of the present invention
  • FIG. 5 is an exemplary view illustrating relationship between a method and an interpreter loop according to an exemplary embodiment of the present invention.
  • FIG. 6 is a flowchart illustrating a process of interpreting a method according to an exemplary embodiment of the present invention.
  • These computer program instructions may also be stored in a computer usable or computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer usable or computer-readable memory produce an article of manufacture including instruction means that implement the function specified in the flowchart block or blocks.
  • the computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operations to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions that are executed on the computer or other programmable apparatus provide operations for implementing the functions specified in the flowchart block or blocks.
  • each block of the flowchart illustrations may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the blocks may occur out of the order. For example, two blocks shown in succession may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved.
  • the term “unit”, that is, “module” or “table”, as used herein, means, but is not limited to, a software or hardware component, such as a Field Programmable Gate Array (FPGA) or Application Specific Integrated Circuit (ASIC), which performs certain tasks.
  • a module may advantageously be configured to reside on the addressable storage medium and configured to be executed on one or more processors.
  • a module may include, by way of example, components, such as software components, object-oriented software components, class components and task components, processes, functions, attributes, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuitry, data, databases, data structures, tables, arrays, and variables.
  • the functionality provided for in the components and modules may be combined into fewer components and modules or further separated into additional components and modules.
  • the components and modules may be implemented so as to execute one or more CPUs in a device.
  • FIG. 3 is a block diagram illustrating configuration of a system according to an exemplary embodiment of the present invention.
  • the system 300 includes an operating system 330 , a virtual machine 320 , and an application 310 .
  • the operating system 330 manages the operation of the whole system such as UNIX and WINDOWS and processes information.
  • the operating system 330 manages the operation of the whole system such as UNIX and WINDOWS and processes information.
  • One of ordinary skill in the art would readily understand that the present invention is not limited to a specified operating system and other known or future developed operation systems are within the scope of the present invention.
  • the virtual machine 320 is operated based on the operating system, and provides an application program interface (API) based on the virtual machine to allow a developer to develop a program using the API without considering the type of the operating system 330 .
  • API application program interface
  • the virtual machine 320 interprets a bytecode to convert the bytecode into a native code that can be recognized by the operating system 330 .
  • the virtual machine 320 forms an interpreter loop for interpreting the bytecode in accordance with characteristics of a method.
  • the virtual machine 320 includes an interpreter engine 325 .
  • a JAVA virtual machine is described as an example of the virtual machine according to an exemplary embodiment of the present invention.
  • One of ordinary skill in the art would readily understand that the present invention is not limited to a JAVA virtual machine and other known or future developed technologies are within the scope of the present invention.
  • the application 310 is a program module that executes a specified operation, wherein the developer can prepare the application 310 using the API provided by the virtual machine 320 .
  • a JAVA application will be described as an example of the application according to an exemplary embodiment of the present invention.
  • One of ordinary skill in the art would readily understand that the present invention is not limited to a JAVA application and other known or future developed applications are within the scope of the present invention.
  • FIG. 4 is a block diagram illustrating a structure of the interpreter engine according to an exemplary embodiment of the present invention.
  • the interpreter engine 400 includes a first interpreter loop generation module 410 , an operation (OP) code set generation module 420 , a second interpreter loop generation module 430 , and a memory management module 440 .
  • the first interpreter loop generation module 410 generates a primary interpreter loop.
  • the primary interpreter loop can interpret any method whatever the method is i.e., regardless of the type of the method.
  • the primary interpreted loop determines whether the method is a bottleneck method.
  • the bottleneck method is a method frequently used and may also be called a “hot method”.
  • the primary interpreter loop includes logic that determines and predicts what method is a bottleneck method.
  • the first interpreter loop generation module 410 provides a function of selecting a bottleneck method.
  • the logic may also include the number of times the method is called.
  • the number of times the method is called stored in each method data structure, is increased or decreased. Then, if a value corresponding to the number of times the method is called reaches a threshold value, the corresponding method may be regarded as a bottleneck method. In this case, the number of times the method is called is used to determine whether the corresponding method is the bottleneck method.
  • the number of times the method is called is used to determine if the method is a bottleneck method.
  • the interpreter engine 400 allows each interpreted method to associate with its interpretation loop routine. Such association may be executed by a callback mechanism. Each method initially associates with a routine of the primary interpreter loop.
  • the OP code set generation module 420 generates an OP code set for a method bytecode. At this time, it is preferable that the bytecode is for a bottleneck method.
  • an empty OP code set is generated.
  • the empty OP code set is filled with an OP code found in the given bytecode for a bottleneck method.
  • the data structure of the OP code set may be optimized by executing binary comparison operation to determine whether the OP code set is included in another OP code set or executing binary comparison operation to identify the difference between two OP code sets.
  • the second interpreter loop generation module 430 generates an interpreter loop for a given OP code set.
  • “interpreter loop” will mean the interpreter loop generated by the second interpreter loop generation module 430 if no specific description is made. In this case, the interpreter loop may be generated by two modes.
  • the first mode is to generate an interpreter loop for all the OP codes of the given OP code set while the second mode is to generate an OP code handler and update the generated interpreter loop using the OP code handler.
  • the memory management module 440 manages memory blocks that include codes for the interpreter loop generated by the second interpreter loop generation module 430 .
  • the memory blocks assigned by the memory management module 440 have the same size as one another to be optimized by a processor code cache.
  • the memory management module 440 determines how many memory spaces are occupied by the generated OP code. At this time, the memory management module 440 is operated along with the second interpreter loop generation module 430 .
  • the memory management module 440 If the memory management module 440 is required to vacate one memory block, it selects one among memory blocks in which the generated interpreter loop codes are written. At this time, the standard of selecting the memory block is to select the memory block that minimizes performance overhead caused by use of the primary interpreter loop instead of the interpreter loop generated by the second interpreter loop generation module 430 .
  • the memory management module 440 arranges the codes of the interpreter loop generated in the selected memory block, and again associates all the dependent methods with either the primary interpreter loop or one of previously generated interpreter loops. At this time, the memory management module 440 can again associate all the dependent methods with one of previously generated interpreter loops when the generated interpreter loops have the same OP code set or the arranged OP code set of the interpreter loop has a lower level than an OP code set of another interpreter loop.
  • FIG. 5 is an exemplary view illustrating relationship between the method and the interpreter loop according to an exemplary embodiment of the present invention.
  • a non-bottleneck method associates with the primary interpreter loop while the bottleneck method associates with the interpreter loop generated by the second interpreter loop generation module 430 .
  • a single interpreter loop can associate with a plurality of bottleneck methods.
  • FIG. 6 is a flowchart illustrating a process of interpreting the method according to an exemplary embodiment of the present invention.
  • the interpreter engine 400 determines whether a currently called method is a bottleneck method (S 610 ). If the currently called method is not the bottleneck method, the interpreter engine 400 interprets the bytecode using the primary interpreter loop (S 640 ).
  • the interpreter engine 400 generates the interpreter loop corresponding to the called method S 620 and associates the generated interpreter loop with the called method (S 630 ).
  • the interpreter engine 400 interprets the bytecode of the called method using the generated interpreter loop (S 640 ).
  • the interpreter engine 400 may interpret the bytecode using the associated interpreter loop.

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  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Devices For Executing Special Programs (AREA)
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KR1020050098159A KR100678912B1 (ko) 2005-10-18 2005-10-18 메소드 바이트코드 해석 방법 및 상기 방법에 의해동작하는 시스템
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120203972A1 (en) * 2011-02-09 2012-08-09 International Business Machines Corporation Memory management for object oriented applications during runtime
US20200065077A1 (en) * 2018-08-21 2020-02-27 International Business Machines Corporation Identifying software and hardware bottlenecks

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101024707B1 (ko) 2010-02-12 2011-03-25 서울대학교산학협력단 바이트코드-투-씨 어헤드-오브-타임 컴파일러를 위한 해석기 호출 방법
KR101970717B1 (ko) 2017-05-18 2019-04-22 뱅크웨어글로벌 주식회사 바이트 코드 기반 자바 메서드 버전 관리 방법, 이를 이용한 자바 소프트웨어 개발 시스템 및 방법
US10853109B2 (en) 2018-12-18 2020-12-01 Red Hat, Inc. Application deployment using reduced overhead bytecode
US11243803B2 (en) * 2019-04-30 2022-02-08 Automation Anywhere, Inc. Platform agnostic robotic process automation
US11113095B2 (en) 2019-04-30 2021-09-07 Automation Anywhere, Inc. Robotic process automation system with separate platform, bot and command class loaders
US11481304B1 (en) 2019-12-22 2022-10-25 Automation Anywhere, Inc. User action generated process discovery
US11182178B1 (en) 2020-02-21 2021-11-23 Automation Anywhere, Inc. Detection of user interface controls via invariance guided sub-control learning
US11968182B2 (en) 2021-07-29 2024-04-23 Automation Anywhere, Inc. Authentication of software robots with gateway proxy for access to cloud-based services

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6014519A (en) * 1996-08-19 2000-01-11 Nec Corporation Language processing unit and a language processing method to translate a source program and generate an object module file
WO2000034844A2 (en) 1998-12-08 2000-06-15 Jedi Technologies, Inc. Java virtual machine hardware for risc and cisc processors
JP2001056764A (ja) 1999-08-18 2001-02-27 Access:Kk 仮想計算機の実行方法および装置
US6256784B1 (en) * 1998-08-14 2001-07-03 Ati International Srl Interpreter with reduced memory access and improved jump-through-register handling
US6295643B1 (en) * 1998-12-10 2001-09-25 International Business Machines Corporation Method and apparatus for improving java virtual machine performance using persistent execution information
US20020104076A1 (en) * 1998-06-30 2002-08-01 Nik Shaylor Code generation for a bytecode compiler
US6546550B1 (en) * 1999-01-28 2003-04-08 International Business Machines Corporation Method to determine dynamic compilation time and to select bytecode execution mode
US20040088703A1 (en) * 2002-11-05 2004-05-06 Nedim Fresko Mechanism for implementing an interpreter with hierarchical execution loops
KR20040076048A (ko) 2003-02-24 2004-08-31 삼성전자주식회사 자바 프로그램에서 바이트 코드의 컴파일 시간 단축시스템 및 방법
US20050028132A1 (en) * 2003-07-31 2005-02-03 Srinivasamurthy Venugopal K. Application specific optimization of interpreters for embedded systems
US20050160415A1 (en) * 2004-01-17 2005-07-21 Samsung Electronics Co., Ltd. Method and system for improving performance of Java virtual machine
US6988261B2 (en) * 2001-08-24 2006-01-17 Sun Microsystems, Inc. Frameworks for generation of Java macro instructions in Java computing environments

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000034854A2 (en) * 1998-12-08 2000-06-15 Koninklijke Philips Electronics N.V. Method of executing an interpreter program
WO2001022213A2 (en) * 1999-09-21 2001-03-29 Koninklijke Philips Electronics N.V. Optimized bytecode interpreter of virtual machine instructions
US6857063B2 (en) * 2001-02-09 2005-02-15 Freescale Semiconductor, Inc. Data processor and method of operation
KR100597413B1 (ko) * 2004-09-24 2006-07-05 삼성전자주식회사 자바 바이트코드 변환 방법 및 상기 변환을 수행하는 자바인터프리터
KR100763177B1 (ko) * 2005-04-21 2007-10-04 삼성전자주식회사 자바 가상 머신의 명령어 수행 방법 및 그 장치

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6014519A (en) * 1996-08-19 2000-01-11 Nec Corporation Language processing unit and a language processing method to translate a source program and generate an object module file
US20020104076A1 (en) * 1998-06-30 2002-08-01 Nik Shaylor Code generation for a bytecode compiler
US6256784B1 (en) * 1998-08-14 2001-07-03 Ati International Srl Interpreter with reduced memory access and improved jump-through-register handling
WO2000034844A2 (en) 1998-12-08 2000-06-15 Jedi Technologies, Inc. Java virtual machine hardware for risc and cisc processors
US6295643B1 (en) * 1998-12-10 2001-09-25 International Business Machines Corporation Method and apparatus for improving java virtual machine performance using persistent execution information
US6546550B1 (en) * 1999-01-28 2003-04-08 International Business Machines Corporation Method to determine dynamic compilation time and to select bytecode execution mode
JP2001056764A (ja) 1999-08-18 2001-02-27 Access:Kk 仮想計算機の実行方法および装置
US6988261B2 (en) * 2001-08-24 2006-01-17 Sun Microsystems, Inc. Frameworks for generation of Java macro instructions in Java computing environments
US20040088703A1 (en) * 2002-11-05 2004-05-06 Nedim Fresko Mechanism for implementing an interpreter with hierarchical execution loops
KR20040076048A (ko) 2003-02-24 2004-08-31 삼성전자주식회사 자바 프로그램에서 바이트 코드의 컴파일 시간 단축시스템 및 방법
US20050028132A1 (en) * 2003-07-31 2005-02-03 Srinivasamurthy Venugopal K. Application specific optimization of interpreters for embedded systems
US20050160415A1 (en) * 2004-01-17 2005-07-21 Samsung Electronics Co., Ltd. Method and system for improving performance of Java virtual machine

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120203972A1 (en) * 2011-02-09 2012-08-09 International Business Machines Corporation Memory management for object oriented applications during runtime
US8453130B2 (en) * 2011-02-09 2013-05-28 International Business Machines Corporation Memory management for object oriented applications during runtime
US20200065077A1 (en) * 2018-08-21 2020-02-27 International Business Machines Corporation Identifying software and hardware bottlenecks
US10970055B2 (en) * 2018-08-21 2021-04-06 International Business Machines Corporation Identifying software and hardware bottlenecks

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