US8115282B2 - Memory cell device and method of manufacture - Google Patents

Memory cell device and method of manufacture Download PDF

Info

Publication number
US8115282B2
US8115282B2 US11/492,305 US49230506A US8115282B2 US 8115282 B2 US8115282 B2 US 8115282B2 US 49230506 A US49230506 A US 49230506A US 8115282 B2 US8115282 B2 US 8115282B2
Authority
US
United States
Prior art keywords
material
comprises
metal species
memory cell
intercalating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US11/492,305
Other versions
US20080023798A1 (en
Inventor
Sandra Mege
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Altis Semiconductor
Adesto Technologies Corp
Original Assignee
Altis Semiconductor
Adesto Technologies Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US11/492,305 priority Critical patent/US8115282B2/en
Application filed by Altis Semiconductor, Adesto Technologies Corp filed Critical Altis Semiconductor
Assigned to INFINEON TECHNOLOGIES AG, ALTIS SEMICONDUCTOR reassignment INFINEON TECHNOLOGIES AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MEGE, SANDRA
Publication of US20080023798A1 publication Critical patent/US20080023798A1/en
Assigned to QIMONDA AG reassignment QIMONDA AG CONTRIBUTION AGREEMENT (RELEVANT PARTS; ENGLISH TRANSLATION) Assignors: INFINEON TECHNOLOGIES AG
Assigned to ADESTO TECHNOLOGY CORPORATION reassignment ADESTO TECHNOLOGY CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: QIMONDA AG
Assigned to INFINEON TECHNOLOGIES AG, ALTIS SEMICONDUCTOR reassignment INFINEON TECHNOLOGIES AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MEGE, SANDRA
Assigned to QIMONDA AG, ALTIS SEMICONDUCTOR reassignment QIMONDA AG CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEES ERRONEOUSLY NAMED AS INFINEON TECHNOLOGIES AG AND ALTIS SEMICONDUCTOR PREVIOUSLY RECORDED ON REEL 018368 FRAME 0413. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECT ASSIGNEES TO BE QIMONDA AG AND ALTIS SEMICONDUCTOR. Assignors: MEGE, SANDRA
Publication of US8115282B2 publication Critical patent/US8115282B2/en
Application granted granted Critical
Assigned to OPUS BANK reassignment OPUS BANK SECURITY AGREEMENT Assignors: Adesto Technologies Corporation, ARTEMIS ACQUISITION LLC
Assigned to BRIDGE BANK, NATIONAL ASSOCIATION reassignment BRIDGE BANK, NATIONAL ASSOCIATION SECURITY AGREEMENT Assignors: Adesto Technologies Corporation, ARTEMIS ACQUISITION LLC
Assigned to Adesto Technologies Corporation, ARTEMIS ACQUISITION LLC reassignment Adesto Technologies Corporation RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: OPUS BANK
Assigned to OPUS BANK reassignment OPUS BANK SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: Adesto Technologies Corporation, ARTEMIS ACQUISITION LLC
Assigned to Adesto Technologies Corporation, ARTEMIS ACQUISITION LLC reassignment Adesto Technologies Corporation RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: WESTERN ALLIANCE BANK
Assigned to OBSIDIAN AGENCY SERVICES, INC., AS COLLATERAL AGENT reassignment OBSIDIAN AGENCY SERVICES, INC., AS COLLATERAL AGENT SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: Adesto Technologies Corporation, ARTEMIS ACQUISITION LLC
Assigned to Adesto Technologies Corporation, ARTEMIS ACQUISITION LLC reassignment Adesto Technologies Corporation RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: OPUS BANK
Application status is Active legal-status Critical
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/12Details
    • H01L45/1253Electrodes
    • H01L45/1266Electrodes adapted for supplying ionic species
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0009RRAM elements whose operation depends upon chemical change
    • G11C13/0011RRAM elements whose operation depends upon chemical change comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/24Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying or switching without a potential-jump barrier or surface barrier, e.g. resistance switching non-volatile memory structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/08Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H01L45/085Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/12Details
    • H01L45/122Device geometry
    • H01L45/1233Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/14Selection of switching materials
    • H01L45/141Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/14Selection of switching materials
    • H01L45/141Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H01L45/142Sulfides, e.g. CuS
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/14Selection of switching materials
    • H01L45/141Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H01L45/143Selenides, e.g. GeSe
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/14Selection of switching materials
    • H01L45/141Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H01L45/144Tellurides, e.g. GeSbTe
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/16Manufacturing
    • H01L45/1608Formation of the switching material, e.g. layer deposition
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/16Manufacturing
    • H01L45/1608Formation of the switching material, e.g. layer deposition
    • H01L45/1625Formation of the switching material, e.g. layer deposition by physical vapor deposition, e.g. sputtering
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/16Manufacturing
    • H01L45/1641Modification of the switching material, e.g. post-treatment, doping
    • H01L45/1658Modification of the switching material, e.g. post-treatment, doping by diffusion, e.g. photo-dissolution

Abstract

According to one embodiment of the present invention, a solid state electrolyte memory cell includes a cathode, an anode and a solid state electrolyte. The anode includes an intercalating material and first metal species dispersed in the intercalating material.

Description

TECHNICAL FIELD

The invention relates to a semiconductor memory with resistively switching memory cells and to a method for manufacturing a semiconductor memory device with non-volatile, resistively switching memory cells.

BACKGROUND

The development of semiconductor memory technology is essentially driven by the requirement for increasing the performance of the semiconductor memories in conjunction with miniaturization of the feature sizes. However, further miniaturization of the semiconductor memory concepts based on storage capacitors may be difficult due to the large quantity of charge that is required for writing to and reading from the storage capacitors, which leads to a high current demand. Therefore, thought is increasingly being given to new cell concepts that are distinguished by a significantly lower quantity of charge for the writing and reading operation. Semiconductor memories having a resistance memory element that exhibits a bipolar switching behavior are one such new promising circuit architecture.

In order to provide maximum density of memory units, it is desirable to provide a cell field consisting of a plurality of memory cells, which are conventionally arranged in a matrix consisting of column and row supply lines, called also word and bit lines, respectively. The actual memory cell is usually positioned at the crosspoints of the supply lines that are made of electrically conductive material. The word and bit lines are each electrically connected with the memory cell via an upper or top electrode and a lower or bottom electrode. To perform a change of the information content in a particular memory cell at the addressed crosspoint, or to recall the content of the memory cell, the corresponding word and bit lines are selected either with a write current or with a read current. To this end, the word and bit lines are controlled by appropriate control means.

There are several memory cells that are able to fit into such memory cell arrangement.

For example, RAM (Random Access Memory) comprises a plurality of memory cells that are each equipped with a capacitor that is connected with a so-called selection transistor. By selectively applying a voltage at the corresponding selection transistor via the word and bit lines, it is possible to store electric charge as an information unit (bit) in the capacitor during a write process and to recall it again during a read process via the selection transistor. A RAM memory device is a memory with random access, i.e., data can be stored under any particular address and can be read out again under this address later.

Another kind of semiconductor memory is DRAM (Dynamic Random Access Memory), which comprises in general only one single, correspondingly controlled capacitive element, e.g., a trench capacitor, with the capacitance of which one bit each can be stored as charge. This charge, however, remains for a relatively short time only in a DRAM memory cell, so that a so-called “refresh” must be performed regularly, wherein the information content is written in the memory cell again.

Since it is intended to accommodate as many memory cells as possible in a RAM memory device, one has been trying to realize them as simple as possible and on the smallest possible space, i.e., to scale them. The previously employed memory concepts (floating gate memories such as flash and DRAM) will, due to their functioning that is based on the storing of charges, presumably meet with physical scaling limits within foreseeable time. Furthermore, in the case of the flash memory concept, the high switching voltages and the limited number of read and write cycles, and in the case of the DRAM memory concept the limited duration of the storage of the charge state, constitute additional problems.

The CBRAM (conductive bridging RAM) memory cell, also known as a programmable metallization cell (“PMC”), may be switched between different electric resistance values by bipolar electric pulsing. In the simplest embodiment, such an element may be switched between a very high (off resistance) and a distinctly lower (on resistance) resistance value by applying short current or voltage pulses. The switching rates may be less than a microsecond. Very high ratios of the off resistance (R(off)) to the on resistance (R(on)) are achieved in the case of the CBRAM cells, due to the very high-resistance state of the solid electrolyte material in the non-programmed state. Typical values are R(off)/R(on)>106 given R(off)>1010′Ω and an active cell area <1 μm2. At the same time, this technology is usually characterized by low switching voltages of less than 100 mV for initiating the erase operation and less than 300 mV for the write operation.

In structural terms, a CBRAM cell is a resistance memory element comprising an inert cathode electrode, a reactive anode electrode and a solid state electrolyte arranged between the cathode and anode. The term “solid state electrolyte,” as referred to herein, includes all solid state materials in which at least some ions can move under the influence of an electric field.

The surfaces of the chalcogenide material, usually provided in a CBRAM cell are deposited by means of sputtering methods, have an amorphous structure and frequently contain superfluous chalcogenides that are poorly bound so that these weakly bound chalcogenide atoms are conglomerated like clusters and cannot be removed, which leads to the formation of Ag-chalcogenide conglomerates or protrusion defects in the Ag doping and electrode layer, which usually is made of Ag. In addition, the etch process of noble metals is difficult as no etch chemistry exists for etching silver, for example. It is, thus, difficult to obtain a homogeneous, planar anode for the CBRAM cells using silver. Current approach is to simultaneously deposit silver together with the other metallic material in a co-sputtering process. However, the planarization and the structuring of the anode has to be done using a physical process.

SUMMARY OF THE INVENTION

The present invention provides a novel CBRAM cell and a method for manufacturing a CBRAM cell according to the invention.

In accordance with one embodiment of the present invention, there is provided a CBRAM memory cell, comprising an anode comprising metal species in an intercalation material.

BRIEF DESCRIPTION OF THE DRAWINGS

In the following, the invention will be explained in more detail with reference to the exemplary embodiments and drawing, in which:

FIGS. 1 a-1 d show the manufacturing steps for a CBRAM memory cell according to one embodiment of the invention; and

FIG. 2 shows a process for manufacturing a CBRAM memory cell according to one embodiment of the invention.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

“Intercalation material” in the context of the description may be understood as any material with a property that a guest species, such as silver or copper, can be inserted therein and extracted therefrom with little or no structural modification of the intercalation material. By using metal atoms intercalated within the intercalation material in accordance with one embodiment of the invention, it is possible to obtain a homogeneous surface of the anode in a CBRAM cell without having any conglomerates of the metal, e.g., of the silver, which could lead to the protrusion defects and inhomogeneous surface of the anode. A further advantage of one embodiment of the present invention is that the intercalation material can be etched much easier than a solid silver layer.

In one embodiment of the invention, the intercalation material is a carbon material, and the metal species intercalated within carbon material are silver atoms. There are several forms of carbon materials that can be used as the intercalation material. Some examples of the carbon material are graphite, graphite sphere, petroleum coke, needle coke, carbon fiber, hard carbon, etc.

In another embodiment of the invention, the intercalation material is selected from the group consisting of silicon, inorganic materials and organic polymeric materials. The examples for the inorganic materials are MoS2, MnO2, MnOx, CoOx, CoMnOx, TiS2, NbSe3, VOx, V2O5, CuCl2, etc. The examples for the organic polymeric materials are polyacetylene, polypyrrole, polyanilene or polythiothene. In a further embodiment of the invention the inorganic materials for the intercalation material are MnOx, CoOx, CoMnOx

The CBRAM (conductive bridging RAM) memory cell used in one embodiment of the invention, also known as a programmable metallization cell (“PMC”), may be switched between different electric resistance values by bipolar electric pulsing. In the simplest embodiment, such an element may be switched between a very high (off resistance) and a distinctly lower (on resistance) resistance value by applying short current or voltage pulses. The switching rates may be less than a microsecond. Very high ratios of the off resistance (R(off)) to the on resistance (R(on)) are achieved in the case of the CBRAM cells, due to the very high-resistance state of the solid electrolyte material in the non-programmed state. Typical values are R(off)/R(on)>106 given R(off)>1010′Ω and an active cell area <1 μm2. At the same time, this technology is usually characterized by low switching voltages of less than 100 mV for initiating the erase operation and less than 300 mV for the write operation.

In structural terms, a CBRAM cell is a resistance memory element comprising an inert cathode electrode, a reactive anode electrode and a solid state electrolyte arranged between the cathode and an anode. The term “solid state electrolyte,” as referred to herein, includes all solid state materials in which at least some ions can move under the influence of an electric field.

The solid state electrolyte used in the CBRAM cells is typically a chalcogenide-metal compound (also referred to as chalcogenide material) comprising ions of an electrically conducting material, which is usually silver. Chalcogenide materials that can be used are compositions of sulfur, selenium and/or tellurium with metals such as arsenic, germanium, bismuth, nickel, and zinc. The chalcogenide material/silver ion composition may be obtained by photodissolution of a silver layer, by co-depositing chalcogenide material and silver (or other materials), by sputtering using a source comprising the chalcogenide and the metal, or by other methods, such as doping, thermal dissolution, etc.

In order to obtain a solid state electrolyte for the CBRAM cell starting from chalcogenide materials, metal ions have to be introduced into the chalcogenide network. Silver is usually introduced into chalcogenide material by illuminating a thin silver film deposited onto the chalcogenide material typically with light of wavelength less than 500 nanometers. If sufficient silver is present, the process results in the saturation of the chalcogenide material with silver through the formation of a silver compound with the chalcogenide material. Such silver compounds may or may not have defined stoichiometry. In some cases the silver content in the chalcogenide material may be below the saturation level, but in other instances it is desirable to fully saturate the chalcogenide material with silver or other metal ions. The content of the metal ions in the chalcogenide material can be controlled by the thickness of the silver layer, which is subjected to photodissolution.

Through application of an electric field between the two electrodes, it is possible to produce a conductive path (clearly a conductive filament) through the carrier material and to clear it away again. Depending on the polarity of the electrical pulses applied between anode electrode and cathode electrode, the reactive anode electrode can be dissolved electrochemically and the metal-rich deposits on the carrier material are intensified, which then leads to an electrically conductive connection between the electrodes. By reversing the electrical pulse the electrically conductive connection is resolved and the metal ions are deposited from the carrier material on the anode electrode.

As the reactive anode electrode is dissolved electrochemically to form the metal-rich deposits in the solid state electrolyte the typically used anode is made of silver or comprises silver, in the case the silver ions are also present in the chalcogenide material. The cathode used in a CBRAM cell can be made of any conducting material since the cathode is inert and does not participate in the electrochemical processes. Typical materials for the cathode are, for example, W, TiN, TiW, TiAlW, even though any conductive material can be used.

The surfaces of the chalcogenide material that are deposited by means of sputtering methods have an amorphous structure and frequently contain superfluous chalcogenides that are poorly bound so that these weakly bound chalcogenide atoms are conglomerated like clusters and cannot be removed, which leads to the formation of Ag-chalcogenide conglomerates or protrusion defects in the Ag doping and electrode layer. In addition, the etch process of noble metals is difficult as no etch chemistry exists for etching silver for example. It is, thus, difficult to obtain a homogeneous, planar anode for the CBRAM cells using silver.

One embodiment of the present invention is directed toward CBRAM cells with an anode comprising an intercalation layer comprising metal atoms. Many specific details of the invention are described below with reference to the methods of manufacturing such CBRAM cells. A person skilled in the art will, however, understand that the present invention may have additional embodiments, be used in connection with materials not described therein or that the invention may be practiced without several of the details described below.

In accordance with one embodiment of the present invention, there is provided a CBRAM memory cell, comprising an anode that comprises metal species in an intercalation material. “Intercalation material” is any material with a property that a guest species such as silver or copper can be inserted therein and extracted therefrom with little or no structural modification of the intercalation material.

FIG. 1 a shows the schematic structure of a CBRAM memory cell comprising a layer stack constructed on a substrate 1 after several process steps. For example in accordance with FIG. 1 a, the metallization for the cathode 2 is deposited on a substrate 1 and patterned using lithographic techniques. By way of example, tungsten, TiN, TiW, TiAlN or others may be used as an electrode material for the cathode 2. After patterning the cathode the chalcogenide material 3 is deposited and patterned. The deposition of the chalcogenide material 3 is done using, for example, reactive sputtering techniques with targets selected from, for example, S, Se and/or Te on the one hand and germanium, bismuth, nickel, and/or zinc on the other hand. The layer thickness of the chalcogenide material is approximately 50 nm-100 nm in this particular example. The size of the cell can be approximately 1 μm×1 μm, but both larger and smaller cells can also be prepared using the method described herein.

Next (not shown), metal, e.g., silver is introduced into the chalcogenide material in order to form a solid state electrolyte 4. The introduction of silver can take place either by illuminating a thin silver film deposited onto the chalcogenide material with light of wavelength less than 500 nanometers or in a sputter process by using an Ag sputter target.

Then, as shown in FIG. 1 b, an intercalation layer 5 is deposited onto the solid electrolyte 4. The typical thickness of the intercalation layer is in a range of about 30 nm to about 100 nm. In one embodiment of the invention the intercalation layer 5 comprises a carbon material. The advantage of using carbon material for the intercalation layer 5 is that many carbon materials are industrially available having versatile electrical and physical characteristics. A further advantage of using carbon for the intercalating layer 5 is that carbon can be etched chemically in a very simple manner by using for example CF4. The basic building block of graphite-type carbon materials is a sheet of carbon atoms arranged in a hexagonal array and stacked in a specific fashion. Between two neighboring carbon sheets, metal atoms or ions can be intercalated. Depending on the method of preparation of the intercalation layer the properties of the anode can be varied.

The intercalation layer comprising carbon can be prepared starting from various precursors that can be in the vapor, liquid or in a solid phase. By choosing the precursors in the liquid phase artificial graphite, petroleum coke or coal tar coke can be produced for example. By choosing vapor phase precursors vapor grown carbon fiber or acetylene black can be obtained for example. Further, from the solid phase precursors, carbon materials such as resin pyrolytic graphite can be obtained. By choosing the appropriate conditions several forms of carbon materials that can be used as the intercalation material, for example, graphite sphere, petroleum coke, needle coke, carbon fiber, hard carbon, etc., can be obtained.

The intercalation layer 5 can be prepared in situ starting from the carbon precursors or in a sputtering process with a carbon target. The surface area of the material building the intercalation layer is usually in the range of 0.8 to 40 m2/g, wherein the range of 0.5 to 5 m2/g is advantageous for some applications. As the surface area correlates with the particle size and particle size distribution, carbon materials having an average particle size approximately 30-50 μm may be used.

In another embodiment of the invention the intercalation layer 5 includes silicon as there are a plurality of techniques known that can be used to deposit all kinds of silicon layers. Typical techniques to deposit a silicon layer is atmospheric pressure (AP), low pressure (LP), plasma enhanced (PE) chemical vapor deposition (CVD) techniques. Furthermore, silicon can be easily doped with silver atoms and readily both wet and dry etches using, for example, HF for wet etching or CF4 for the dry etching.

In an alternative embodiment of the invention, the intercalation layer 5 includes a material selected from the group consisting of inorganic materials. Generally all metal oxides can be used but transition metal oxides may also be used as intercalating materials. In one embodiment of the invention, metal oxides such as MoS2, MnOx, CoOx, CoMnOx, TiS2, NbSe3, VOx, V2O5, CuCl2 may be used. In these compounds, a guest species such as silver atoms can be inserted interstitially into the host lattice of the intercalating materials as described below and subsequently extracted with little or no structural modification of the intercalating material. An advantage of the inorganic salts is the easiness of preparation using for example sputtering processes.

In a further embodiment of the invention, organic polymeric materials can be used as intercalating materials for the intercalation layer 5. All organic polymers that exhibit some electrical conductivity when doped with silver atoms can be used as intercalating materials. Typical polymeric materials for the purposes of the invention are polyacetylene, polypyrrole, polyaniline and polythiophene.

As described above, it is possible to produce a conductive path such as a conductive filament through the solid state electrolyte 4 and to clear it away again by applying an electric field between the two cathode and the anode. Depending on the polarity of the electrical pulses applied between anode electrode and cathode electrode, the reactive anode electrode is dissolved electrochemically and the metal-rich deposits on the carrier material are intensified, which then leads to an electrically conductive connection between the electrodes.

Therefore, the anode includes a reservoir of the metal atoms that can be dissolved into the solid electrolyte, when an electrical pulse is applied. As shown in FIG. 1 c, a metal layer 6 including material used for the reactive anode is deposited onto the intercalation layer 5. After a subsequent dissolution, for example by annealing, the metal atoms are inserted interstitially into the host lattice of the intercalation layer 5 to build an anode 7 of the CBRAM cell as shown in FIG. 1 d. The intercalating material and metal can be also co-sputtered to immediately obtain the anode 7. In an alternative embodiment of the invention, the metal atoms are implanted into the intercalation material using ion implantation. In one embodiment of the invention, the anode 7 includes intercalating material and silver atoms.

Lithographic techniques and wet or dry etching can then be used to obtain a CBRAM cell according to one embodiment of the present invention.

In one embodiment of the invention a CBRAM cell is prepared according to a process as shown in a flow diagram 20 in FIG. 2. According to this embodiment a CBRAM cell is manufactured by depositing cathode material, such as tungsten, TiN, TiW, TiAlN or some other material that can be used to manufacture a cathode (process 22). After the deposition of the cathode material, such material can be patterned to form the cathode if necessary.

After the formation of the cathode, the chalcogenide material is deposited thereafter and if necessary patterned (process 24). The chalcogenide material can extend over the surface of the cathode or cover only partially cover the surface of the cathode depending on the desired architecture of the CBRAM cell.

In a next process (process 26), a layer of the second metal species, such as silver may be deposited onto the chalcogenide material. When illuminating the layer of the second metal species with light (process 28), a photo dissolution takes place forming thereby a solution of the second metal species in the chalcogenide material. Alternatively, the second metal species can be introduced into the chalcogenide material by sputtering or ion implantation for example. The sputtering can take place by a simultaneous deposition of the chalcogenide material and the second metal species, for example, by co-sputtering, or by depositing the chalcogenide material first and introducing the second metal species in a further step.

After forming a solid state electrolyte from the chalcogenide material and the second metal species, an intercalating material may be deposited thereon (process 30). The intercalation material may be carbon-containing material, silicon, inorganic materials such as inorganic oxide(s) and organic polymers. The typical thickness of the intercalation layer is approximately in a range of 30 to 100 nm.

Then the intercalating material may be treated with the first metal species to obtain an anode comprising an intercalated material and the first metal species dispersed therein (process 32).

A CBRAM cell in accordance with one embodiment of the present invention can be part of an arrangement comprising a plurality of memory cells arranged for example on the crosspoint between the word and the bit lines. The cells can further be equipped with a capacitor, which is connected with a so-called selection transistor. By selectively applying a voltage at the corresponding selection transistor via the word and bit lines, it is possible to store electric charge as an information unit (bit) in the capacitor during a write process and to recall it again during a read process via the selection transistor.

From the foregoing it will be appreciated that specific embodiments of the invention have been described herein for the purposes of illustration, but that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.

Claims (44)

What is claimed is:
1. An integrated circuit device comprising a cathode, an anode and a solid state electrolyte arranged between the cathode and the anode, the anode comprising an intercalating material and first metal species dispersed in the intercalating material, wherein the solid state electrolyte comprises chalcogenide material and a second metal species, wherein a homogeneous surface of the anode is formed.
2. The integrated circuit device according to claim 1, wherein the first metal species comprises silver atoms.
3. The integrated circuit device according to claim 1, wherein the first metal species comprises silver ions.
4. The integrated circuit device according to claim 1, wherein the intercalating material comprises carbon.
5. The integrated circuit device according to claim 4, wherein the intercalating material comprises a material selected from the group consisting of artificial graphite, petroleum coke, coal tar, coke, carbon fiber, acetylene, resin pyrolytic graphite, graphite sphere, petroleum coke, needle coke, carbon fiber and hard carbon.
6. The integrated circuit device according to claim 1, wherein the intercalating material comprises silicon.
7. The integrated circuit device according to claim 1, wherein the intercalating material comprises an inorganic material.
8. The integrated circuit device according to claim 7, wherein the intercalating material comprises an inorganic material selected from the group consisting of MoS2, CoOx, MnO2, CoMnOx, TiS2, NbSe3, VOx, V2O5 and CuCl2.
9. The integrated circuit device according to claim 1, wherein the intercalating material comprises an organic polymer.
10. The integrated circuit device according to claim 9, wherein the organic polymer is conductive.
11. The integrated circuit device according to claim 9, wherein the organic polymer comprises a material selected from the group consisting of polyacetylene, polypyrrole, polyaniline and polythiophene.
12. The integrated circuit device according to claim 1, wherein the solid electrolyte comprises a sulfur, selenium or tellurium compound and wherein the second metal species comprises a metal selected from the group consisting of germanium, bismuth, nickel, and zinc.
13. The integrated circuit device according to claim 1, wherein the solid electrolyte comprises a sulfur, selenium and tellurium compound and wherein the second metal species comprises a metal selected from the group consisting of germanium, bismuth, nickel, and zinc.
14. The integrated circuit device according to claim 1, wherein the second metal species comprises silver ions.
15. A memory cell comprising:
an anode, the anode comprising an intercalating material and first metal species intercalated in the intercalating material;
a cathode; and
a chalcogenide material arranged in an electrical contact between the cathode and the anode, the chalcogenide material comprising a second metal species, wherein a homogenous surface of the anode is formed.
16. The memory cell according to claim 15, wherein the first metal species comprises silver atoms.
17. The memory cell according to claim 15, wherein the first metal species comprises silver ions.
18. The memory cell according to claim 15, wherein the intercalating material comprises carbon.
19. The memory cell according to claim 18, wherein the intercalating material comprises a material selected from the group consisting of artificial graphite, petroleum coke, coal tar, coke, carbon fiber, acetylene, resin pyrolytic graphite, graphite sphere, petroleum coke, needle coke, carbon fiber and hard carbon.
20. The memory cell according to claim 15, wherein the intercalating material comprises silicon.
21. The memory cell according to claim 15, wherein the intercalating material comprises an inorganic material.
22. The memory cell according to claim 21, wherein the inorganic material comprises a material selected from the group consisting of MoS2, MnO2, CoOx, CoMnOx, TiS2, NbSe3, VOx, V2O5 and CuCl2.
23. The memory cell according to claim 15, wherein the intercalating material comprises an organic polymer.
24. The memory cell according to claim 23, wherein the organic polymer is conductive.
25. The memory cell according to claim 23, wherein the organic polymer comprises a material selected from the group consisting of polyacetylene, polypyrrole, polyaniline and polythiophene.
26. The memory cell according to claim 15, wherein the chalcogenide material comprises a sulfur, selenium or tellurium compound and the second metal species comprises a metal selected from the group consisting of germanium, bismuth, nickel, and zinc.
27. The memory cell according to claim 15, wherein the chalcogenide material comprises a sulfur, selenium and tellurium compound and the second metal species comprises a metal selected from the group consisting of germanium, bismuth, nickel, and zinc.
28. The memory cell according to claim 15, wherein the second metal species comprises silver ions.
29. A memory arrangement comprising:
a word line;
a bit line; and
a memory cell in an electrical contact with the word line and the bit line, the memory cell comprising an anode, a cathode and a chalcogenide material arranged in electrical contact between the anode and the cathode, the chalcogenide material comprising a second metal species and the anode comprising an intercalating material and a first metal species intercalated in the intercalating material, wherein a homogeneous surface of the anode is formed.
30. The memory arrangement according to claim 29, wherein the word line and the bit line are arranged substantially perpendicular to each other.
31. The memory arrangement according to claim 30, wherein the memory cell is arranged at a cross point of the word line and the bit line.
32. The memory arrangement according to claim 29, wherein the first metal species comprises silver atoms.
33. The memory arrangement according to claim 29, wherein the first metal species comprises silver ions.
34. The memory arrangement according to claim 29, wherein the intercalating material comprises carbon.
35. The memory arrangement according to claim 29, wherein the intercalating material comprises a material selected from the group consisting of artificial graphite, petroleum coke, coal tar, coke, carbon fiber, acetylene, resin pyrolytic graphite, graphite sphere, petroleum coke, needle coke, carbon fiber and hard carbon.
36. The memory arrangement according to claim 29, wherein the intercalating material comprises silicon.
37. The memory arrangement according to claim 29, wherein the intercalating material comprises an inorganic material.
38. The memory arrangement according to claim 37, wherein the inorganic material comprises a material selected from the group consisting of MoS2, MnO2, TiS2, CoOx, CoMnOx, NbSe3, VOx, V2O5 and CuCl2.
39. The memory arrangement according to claim 29, wherein the intercalating material comprises an organic polymer.
40. The memory arrangement according to claim 39, wherein the organic polymer is conductive.
41. The memory arrangement according to claim 40, wherein the organic polymer comprises a material selected from the group consisting of polyacetylene, polypyrrole, polyaniline and polythiophene.
42. The memory arrangement according to claim 29, wherein the chalcogenide material comprises a sulfur, selenium or tellurium compound and wherein the second metal species comprises a metal selected from the group consisting of germanium, bismuth, nickel, and zinc.
43. The memory arrangement according to claim 29, wherein the chalcogenide material comprises a sulfur, selenium and tellurium compound and wherein the second metal species comprises a metal selected from the group consisting of germanium, bismuth, nickel, and zinc.
44. The memory arrangement according to claim 29, wherein the second metal species comprises silver ions.
US11/492,305 2006-07-25 2006-07-25 Memory cell device and method of manufacture Active 2029-04-20 US8115282B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/492,305 US8115282B2 (en) 2006-07-25 2006-07-25 Memory cell device and method of manufacture

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/492,305 US8115282B2 (en) 2006-07-25 2006-07-25 Memory cell device and method of manufacture
DE200610038077 DE102006038077A1 (en) 2006-07-25 2006-08-16 Solid electrolyte storage cell comprises cathode, anode and solid electrolytes, where anode has intercalation material and metal species, which are unfixed in intercalation material
US13/346,749 US8420481B2 (en) 2006-07-25 2012-01-10 Memory cell device and method of manufacture
US13/832,761 US8952493B2 (en) 2006-07-25 2013-03-15 Memory cell device and method of manufacture

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US13/346,749 Division US8420481B2 (en) 2006-07-25 2012-01-10 Memory cell device and method of manufacture

Publications (2)

Publication Number Publication Date
US20080023798A1 US20080023798A1 (en) 2008-01-31
US8115282B2 true US8115282B2 (en) 2012-02-14

Family

ID=38859504

Family Applications (3)

Application Number Title Priority Date Filing Date
US11/492,305 Active 2029-04-20 US8115282B2 (en) 2006-07-25 2006-07-25 Memory cell device and method of manufacture
US13/346,749 Active 2026-08-01 US8420481B2 (en) 2006-07-25 2012-01-10 Memory cell device and method of manufacture
US13/832,761 Expired - Fee Related US8952493B2 (en) 2006-07-25 2013-03-15 Memory cell device and method of manufacture

Family Applications After (2)

Application Number Title Priority Date Filing Date
US13/346,749 Active 2026-08-01 US8420481B2 (en) 2006-07-25 2012-01-10 Memory cell device and method of manufacture
US13/832,761 Expired - Fee Related US8952493B2 (en) 2006-07-25 2013-03-15 Memory cell device and method of manufacture

Country Status (2)

Country Link
US (3) US8115282B2 (en)
DE (1) DE102006038077A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130285004A1 (en) * 2012-03-26 2013-10-31 Adesto Technologies Corporation Solid electrolyte memory elements with electrode interface for improved performance
US8981334B1 (en) * 2013-11-01 2015-03-17 Micron Technology, Inc. Memory cells having regions containing one or both of carbon and boron
US9178142B2 (en) 2013-03-04 2015-11-03 Intermolecular, Inc. Doped electrodes used to inhibit oxygen loss in ReRAM device

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080112207A1 (en) * 2006-11-10 2008-05-15 Cay-Uwe Pinnow Solid electrolyte memory device
FR2973554B1 (en) 2011-04-04 2013-04-12 Commissariat Energie Atomique "Electronic device selector type"
US8962460B2 (en) 2011-04-26 2015-02-24 Micron Technology, Inc. Methods of selectively forming metal-doped chalcogenide materials, methods of selectively doping chalcogenide materials, and methods of forming semiconductor device structures including same
DE102014113030A1 (en) * 2014-09-10 2016-03-10 Infineon Technologies Ag Memory circuits, and a method of forming a memory circuit

Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2736995A1 (en) 1977-01-18 1978-07-20 Exxon Research Engineering Co electrolyte composition and solid containing them, electrical-yielding element
DE2817702A1 (en) 1977-04-25 1978-10-26 Mallory & Co Inc P R Positive electrode for festkoerperelektrolyten
US4224390A (en) 1978-08-21 1980-09-23 Haering Rudolph R Lithium molybdenum disulphide battery cathode
DE2933738C2 (en) 1978-08-21 1984-05-24 Rudolph Roland Haering
US6218053B1 (en) 1997-05-21 2001-04-17 Kawabi & Associates Thin aprotic electrolyte films, immobilized liquid membrane conductors, and batteries
US20010032666A1 (en) * 2000-03-24 2001-10-25 Inegrated Power Solutions Inc. Integrated capacitor-like battery and associated method
WO2002061864A1 (en) 2001-01-31 2002-08-08 Korea Institute Of Science And Technology A lithium electrode comprising surface-treated lithium particles, its fabrication method and lithium battery comprising the same
US20020168574A1 (en) 1997-06-27 2002-11-14 Soon-Ho Ahn Lithium ion secondary battery and manufacturing method of the same
US20030052330A1 (en) * 2001-09-20 2003-03-20 Klein Rita J. Electro-and electroless plating of metal in the manufacture of PCRAM devices
DE69817592T2 (en) 1997-06-27 2004-07-01 Lg Chemical Ltd. Lithium ion secondary battery and process for their preparation
US20040124406A1 (en) 2001-08-29 2004-07-01 Campbell Kristy A. Method of forming non-volatile resistance variable devices, method of forming a programmable memory cell of memory circuitry, and a non-volatile resistance variable device
US20040159835A1 (en) 2001-08-13 2004-08-19 Krieger Juri Heinrich Memory device
US20050026433A1 (en) 2001-08-30 2005-02-03 Jiutao Li Integrated circuit device and fabrication using metal-doped chalcogenide materials
US6858481B2 (en) 2001-08-13 2005-02-22 Advanced Micro Devices, Inc. Memory device with active and passive layers
EP1551069A1 (en) 2003-12-12 2005-07-06 Greatbatch Technologies Advanced Research Laboratories, Inc. Medium rate and high rate batteries
US20050221169A1 (en) 2000-10-17 2005-10-06 Matsushita Electric Industrial Co., Ltd. Battery and method for generating electricity
DE102004014965A1 (en) 2004-03-26 2005-10-27 Infineon Technologies Ag Memory cell production method for a non-volatile memory cell has a solid-state electrolyte area as a memory element activated by building in a fundamental rule
DE102005018344A1 (en) 2004-04-29 2005-12-01 Infineon Technologies Ag Switching means for reconfigurable interconnect and method of making same
EP1643569A1 (en) 2004-10-01 2006-04-05 Samsung SDI Co., Ltd. Lithium rechargeable battery

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080078983A1 (en) * 2006-09-28 2008-04-03 Wolfgang Raberg Layer structures comprising chalcogenide materials

Patent Citations (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2736995A1 (en) 1977-01-18 1978-07-20 Exxon Research Engineering Co electrolyte composition and solid containing them, electrical-yielding element
DE2817702A1 (en) 1977-04-25 1978-10-26 Mallory & Co Inc P R Positive electrode for festkoerperelektrolyten
US4224390A (en) 1978-08-21 1980-09-23 Haering Rudolph R Lithium molybdenum disulphide battery cathode
DE2933738C2 (en) 1978-08-21 1984-05-24 Rudolph Roland Haering
US6218053B1 (en) 1997-05-21 2001-04-17 Kawabi & Associates Thin aprotic electrolyte films, immobilized liquid membrane conductors, and batteries
DE69827760T2 (en) 1997-05-21 2005-10-27 Tonen Chemical Corp. Proton-free thin-elektrolyefilm, immobilized liquid film conductor and batteries
US20020168574A1 (en) 1997-06-27 2002-11-14 Soon-Ho Ahn Lithium ion secondary battery and manufacturing method of the same
DE69817592T2 (en) 1997-06-27 2004-07-01 Lg Chemical Ltd. Lithium ion secondary battery and process for their preparation
US20010032666A1 (en) * 2000-03-24 2001-10-25 Inegrated Power Solutions Inc. Integrated capacitor-like battery and associated method
US20050221169A1 (en) 2000-10-17 2005-10-06 Matsushita Electric Industrial Co., Ltd. Battery and method for generating electricity
WO2002061864A1 (en) 2001-01-31 2002-08-08 Korea Institute Of Science And Technology A lithium electrode comprising surface-treated lithium particles, its fabrication method and lithium battery comprising the same
US20040159835A1 (en) 2001-08-13 2004-08-19 Krieger Juri Heinrich Memory device
US6858481B2 (en) 2001-08-13 2005-02-22 Advanced Micro Devices, Inc. Memory device with active and passive layers
US20040124406A1 (en) 2001-08-29 2004-07-01 Campbell Kristy A. Method of forming non-volatile resistance variable devices, method of forming a programmable memory cell of memory circuitry, and a non-volatile resistance variable device
US20050026433A1 (en) 2001-08-30 2005-02-03 Jiutao Li Integrated circuit device and fabrication using metal-doped chalcogenide materials
US20030052330A1 (en) * 2001-09-20 2003-03-20 Klein Rita J. Electro-and electroless plating of metal in the manufacture of PCRAM devices
EP1551069A1 (en) 2003-12-12 2005-07-06 Greatbatch Technologies Advanced Research Laboratories, Inc. Medium rate and high rate batteries
DE102004014965A1 (en) 2004-03-26 2005-10-27 Infineon Technologies Ag Memory cell production method for a non-volatile memory cell has a solid-state electrolyte area as a memory element activated by building in a fundamental rule
DE102005018344A1 (en) 2004-04-29 2005-12-01 Infineon Technologies Ag Switching means for reconfigurable interconnect and method of making same
EP1643569A1 (en) 2004-10-01 2006-04-05 Samsung SDI Co., Ltd. Lithium rechargeable battery

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130285004A1 (en) * 2012-03-26 2013-10-31 Adesto Technologies Corporation Solid electrolyte memory elements with electrode interface for improved performance
US9099633B2 (en) * 2012-03-26 2015-08-04 Adesto Technologies Corporation Solid electrolyte memory elements with electrode interface for improved performance
US9178142B2 (en) 2013-03-04 2015-11-03 Intermolecular, Inc. Doped electrodes used to inhibit oxygen loss in ReRAM device
US8981334B1 (en) * 2013-11-01 2015-03-17 Micron Technology, Inc. Memory cells having regions containing one or both of carbon and boron
US20150179936A1 (en) * 2013-11-01 2015-06-25 Micron Technology, Inc. Memory Cells and Methods of Forming Memory Cells
US20160035974A1 (en) * 2013-11-01 2016-02-04 Micron Technology, Inc. Memory Cells and Methods of Forming Memory Cells
US9257646B2 (en) * 2013-11-01 2016-02-09 Micron Technology, Inc. Methods of forming memory cells having regions containing one or both of carbon and boron
US9385317B2 (en) * 2013-11-01 2016-07-05 Micron Technology, Inc. Memory cells and methods of forming memory cells
US9496495B2 (en) * 2013-11-01 2016-11-15 Micron Technology, Inc. Memory cells and methods of forming memory cells

Also Published As

Publication number Publication date
US20080023798A1 (en) 2008-01-31
US20120104341A1 (en) 2012-05-03
US8420481B2 (en) 2013-04-16
US20130200329A1 (en) 2013-08-08
DE102006038077A1 (en) 2008-01-31
US8952493B2 (en) 2015-02-10

Similar Documents

Publication Publication Date Title
Waser et al. Nanoionics-based resistive switching memories
Pan et al. Recent progress in resistive random access memories: materials, switching mechanisms, and performance
US7292469B2 (en) Methods of programming non-volatile memory devices including transition metal oxide layer as data storage material layer and devices so operated
US9000408B2 (en) Memory device with low reset current
US8110430B2 (en) Vacuum jacket for phase change memory element
US7145794B2 (en) Programmable microelectronic devices and methods of forming and programming same
CN101685827B (en) Memory device and its manufacturing method
US7547905B2 (en) Programmable conductor memory cell structure and method therefor
US7026702B2 (en) Memory device
US9543514B2 (en) Memory component, memory device, and method of operating memory device
US7560724B2 (en) Storage device with reversible resistance change elements
US7820996B2 (en) Nonvolatile memory device made of resistance material and method of fabricating the same
US8686388B2 (en) Non-volatile resistive sense memory with improved switching
US7943920B2 (en) Resistive memory structure with buffer layer
US7983065B2 (en) Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines
CN100524879C (en) Method for fabricating a pillar-shaped phase change memory element
US8063394B2 (en) Integrated circuit
EP1947696B1 (en) Nonvolatile memory device comprising a switching device and a resistant material and method of manufacturing the same
KR101496281B1 (en) Memory element and memory device
US7935953B2 (en) Nonvolatile memory device, array of nonvolatile memory devices, and methods of making the same
US20070249083A1 (en) Multilevel phase-change memory element and operating method
US6998312B2 (en) Microelectronic programmable device and methods of forming and programming the same
CN100502029C (en) Phase change memory element and its forming method
US7101728B2 (en) Programmable structure including an oxide electrolyte and method of forming programmable structure
CN101000892B (en) Programmable resistive RAM and manufacturing method

Legal Events

Date Code Title Description
AS Assignment

Owner name: INFINEON TECHNOLOGIES AG, GERMANY

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MEGE, SANDRA;REEL/FRAME:018368/0413

Effective date: 20060920

Owner name: ALTIS SEMICONDUCTOR, FRANCE

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MEGE, SANDRA;REEL/FRAME:018368/0413

Effective date: 20060920

AS Assignment

Owner name: QIMONDA AG, GERMANY

Free format text: CONTRIBUTION AGREEMENT (RELEVANT PARTS; ENGLISH TRANSLATION);ASSIGNOR:INFINEON TECHNOLOGIES AG;REEL/FRAME:023330/0771

Effective date: 20060425

Owner name: QIMONDA AG,GERMANY

Free format text: CONTRIBUTION AGREEMENT (RELEVANT PARTS; ENGLISH TRANSLATION);ASSIGNOR:INFINEON TECHNOLOGIES AG;REEL/FRAME:023330/0771

Effective date: 20060425

AS Assignment

Owner name: INFINEON TECHNOLOGIES AG, GERMANY

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MEGE, SANDRA;REEL/FRAME:024957/0569

Effective date: 20060404

Owner name: ALTIS SEMICONDUCTOR, FRANCE

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MEGE, SANDRA;REEL/FRAME:024957/0569

Effective date: 20060404

Owner name: ADESTO TECHNOLOGY CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:QIMONDA AG;REEL/FRAME:024953/0554

Effective date: 20100614

AS Assignment

Owner name: QIMONDA AG, GERMANY

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEES ERRONEOUSLY NAMED AS INFINEON TECHNOLOGIES AG AND ALTIS SEMICONDUCTOR PREVIOUSLY RECORDED ON REEL 018368 FRAME 0413. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECT ASSIGNEES TO BE QIMONDA AG AND ALTIS SEMICONDUCTOR;ASSIGNOR:MEGE, SANDRA;REEL/FRAME:025317/0737

Effective date: 20100213

Owner name: ALTIS SEMICONDUCTOR, FRANCE

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEES ERRONEOUSLY NAMED AS INFINEON TECHNOLOGIES AG AND ALTIS SEMICONDUCTOR PREVIOUSLY RECORDED ON REEL 018368 FRAME 0413. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECT ASSIGNEES TO BE QIMONDA AG AND ALTIS SEMICONDUCTOR;ASSIGNOR:MEGE, SANDRA;REEL/FRAME:025317/0737

Effective date: 20100213

STCF Information on status: patent grant

Free format text: PATENTED CASE

AS Assignment

Owner name: OPUS BANK, CALIFORNIA

Free format text: SECURITY AGREEMENT;ASSIGNORS:ADESTO TECHNOLOGIES CORPORATION;ARTEMIS ACQUISITION LLC;REEL/FRAME:029090/0922

Effective date: 20120927

AS Assignment

Owner name: BRIDGE BANK, NATIONAL ASSOCIATION, CALIFORNIA

Free format text: SECURITY AGREEMENT;ASSIGNORS:ADESTO TECHNOLOGIES CORPORATION;ARTEMIS ACQUISITION LLC;REEL/FRAME:031371/0581

Effective date: 20131004

AS Assignment

Owner name: ADESTO TECHNOLOGIES CORPORATION, CALIFORNIA

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:OPUS BANK;REEL/FRAME:031414/0232

Effective date: 20131009

Owner name: ARTEMIS ACQUISITION LLC, CALIFORNIA

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:OPUS BANK;REEL/FRAME:031414/0232

Effective date: 20131009

AS Assignment

Owner name: OPUS BANK, CALIFORNIA

Free format text: SECURITY INTEREST;ASSIGNORS:ADESTO TECHNOLOGIES CORPORATION;ARTEMIS ACQUISITION LLC;REEL/FRAME:035754/0580

Effective date: 20150430

FPAY Fee payment

Year of fee payment: 4

AS Assignment

Owner name: ADESTO TECHNOLOGIES CORPORATION, CALIFORNIA

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WESTERN ALLIANCE BANK;REEL/FRAME:044219/0610

Effective date: 20171003

Owner name: ARTEMIS ACQUISITION LLC, CALIFORNIA

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WESTERN ALLIANCE BANK;REEL/FRAME:044219/0610

Effective date: 20171003

AS Assignment

Owner name: OBSIDIAN AGENCY SERVICES, INC., AS COLLATERAL AGEN

Free format text: SECURITY INTEREST;ASSIGNORS:ADESTO TECHNOLOGIES CORPORATION;ARTEMIS ACQUISITION LLC;REEL/FRAME:046105/0731

Effective date: 20180508

AS Assignment

Owner name: ADESTO TECHNOLOGIES CORPORATION, CALIFORNIA

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:OPUS BANK;REEL/FRAME:049125/0970

Effective date: 20160707

Owner name: ARTEMIS ACQUISITION LLC, CALIFORNIA

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:OPUS BANK;REEL/FRAME:049125/0970

Effective date: 20160707