US8112112B2 - Radio apparatus and radio receiving method - Google Patents
Radio apparatus and radio receiving method Download PDFInfo
- Publication number
- US8112112B2 US8112112B2 US12/241,681 US24168108A US8112112B2 US 8112112 B2 US8112112 B2 US 8112112B2 US 24168108 A US24168108 A US 24168108A US 8112112 B2 US8112112 B2 US 8112112B2
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- Prior art keywords
- signal
- transmission signal
- reception
- input
- transmission
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
- H04B1/50—Circuits using different frequencies for the two directions of communication
- H04B1/52—Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa
- H04B1/525—Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa with means for reducing leakage of transmitter signal into the receiver
Definitions
- Multimode radio apparatuses have been made available in recent years that are radios or radio devices that can be used in multiple modes such as multiple frequency bands.
- Japanese Patent Application Laid-Open Publication No. 2000-13274 discloses a multimode radio apparatus including CDMA (Code Division Multiplex Access) and PDC (Personal Digital Cellular System) transmission units.
- CDMA Code Division Multiplex Access
- PDC Personal Digital Cellular System
- the technique in Japanese Patent Application Laid-Open Publication No. 2000-13274 can reduce the number of components in transmission units by sharing circuits between the wideband CDMA and PDC transmission units.
- Japanese Patent Application Laid-Open Publication No. 2003-133981 discloses a reception unit of a multimode radio apparatus that receives wideband and narrowband signals.
- the technique in Japanese Patent Application Laid-Open Publication No. 2003-133981 can reduce the size of the apparatus by sharing circuits of the reception unit between the two modes.
- the reception signal intensity becomes very strong because the transmitting and receiving circuits are close to each other. Consequently, the transmission signal acts as an interference wave or noise that interferes with the target reception signal that the receiver is expected to receive.
- Japanese Patent Application Laid-Open Publication No. 2007-505591 discloses that a vector multiplier is used in a multimode radio transmission and reception unit to reduce or eliminate interference with a receiver caused by a transmitter while the transmitter is transmitting a transmission signal to an antenna and at the same time a receiver is receiving a signal in another mode from the antenna.
- the vector multiplier controls the phase and amplitude of noise that cross-talks into the receiver (that is, spurious noise).
- the configuration for adjusting the phase and amplitude as described in Japanese Patent Application Laid-Open Publication No. 2007-505591 has the drawback that the configuration increases the complexity and size of the circuitry as well as the cost.
- a radio apparatus includes: a receiver configured to receive as a reception signal a wirelessly transmitted signal; a transmitter provided in the vicinity of the receiver and configured to generate a transmission signal to be wirelessly transmitted with a frequency different from that of the reception signal; and a reception signal extracting unit provided in the receiver and configured to extract a reception signal from an input signal containing the reception signal and the transmission signal, at a timing of a zero crossing of the transmission signal in the input signal, by using phase information including a phase of the transmission signal from the transmitter.
- a radio apparatus includes: a receiver configured to receive as a reception signal a wirelessly transmitted signal; a transmitter provided in the vicinity of the receiver and configured to generate a transmission signal to be wirelessly transmitted with a frequency different from that of the reception signal; a transmission signal generating unit provided in the transmitter and configured to generate phase information of the transmission signal; and a reception signal extracting unit provided in the receiver and configured to extract a reception signal from an input signal containing the reception signal and the transmission signal, at a timing of a zero crossing of the transmission signal in the input signal, by using the phase information input from the transmission signal generating unit.
- a radio receiving method using a receiver configured to receive as a reception signal a wirelessly transmitted signal and a transmitter provided in the vicinity of the receiver and configured to generate a transmission signal to be wirelessly transmitted with a frequency different from that of the reception signal detects a timing of a zero crossing of the transmission signal in the input signal, from the input signal in the receiver containing the reception signal and the transmission signal, by using phase information including a phase of the transmission signal from the transmitter and extracts the reception signal at the detected timing.
- FIG. 1 is a diagram showing a radio system including a multimode radio apparatus according to a first embodiment of the present invention
- FIG. 2 is a block diagram showing a configuration of a reception signal extracting unit provided in a receiver constituting the multimode radio apparatus;
- FIG. 3 is a diagram illustrating a configuration and operation of a sampling circuit constituting the reception signal extracting unit
- FIGS. 4A to 4F are diagrams illustrating operations of components of the reception signal extracting unit before delay adjustment
- FIGS. 5A to 5F are diagrams illustrating operations of the components of the reception signal extracting unit after the delay adjustment
- FIG. 6 is a diagram showing an example of the result of a simulation of the operations shown in FIGS. 5A to 5F ;
- FIG. 7 is a block diagram showing a configuration of a reception signal extracting unit according to a variation of the first embodiment
- FIGS. 8A and 8B are diagrams illustrating a periodic control operation for adjusting a delay amount according to the variation
- FIG. 9 is a block diagram showing a configuration of a receiver according to a second embodiment of the present invention.
- FIG. 10 is a circuit diagram showing an exemplary configuration of a delay adjusting circuit according to a variation of the second embodiment.
- FIG. 1 shows a radio system 2 including a multimode radio apparatus 1 according to a first embodiment of the present invention.
- the radio system 2 includes the multimode radio apparatus 1 according to the first embodiment and a transceiver or a transmission base station (hereinafter referred to as a transceiver) 3 which communicates with the multimode radio apparatus 1 .
- a transceiver or a transmission base station hereinafter referred to as a transceiver
- the transmitter 4 transmits a transmission signal TX 1 generated at the transmitter 4 to the outside (of the multimode radio apparatus 1 ) through an antenna 6 a .
- the transceiver 3 receives the transmission signal TX 1 through an antenna 7 .
- the transceiver 3 transmits a transmission signal TX to the outside of the transceiver 3 through the antenna 7 .
- the receiver 5 receives the transmission signal TX transmitted from the transceiver 3 , for example, as a reception signal RX through an antenna 6 b . While separate antennas 6 a and 6 b are used for transmission and reception in the multimode radio apparatus 1 in FIG. 1 , a common antenna may be used instead.
- the target reception signal RX to be received and the transmission signal TX 1 are input in the receiver 5 as input signals (through the antenna 6 b ).
- the input signals are amplified by an amplifier 12 and then input in the reception signal extracting unit 11 .
- Symbols (fR) and (fT) suffixed to the reception and transmission signal symbols RX and TX 1 in FIG. 2 denote the frequencies of the signals. The same symbols are also used in FIGS. 4A to 4F and 5 A to 5 F described later.
- the reception signal extracting unit 11 includes a sampling circuit 13 configured to sample the reception signal RX and transmission signal TX 1 , which are input signals, a first low-pass filter (abbreviated as first LPF) 14 configured to extract a reception signal component in a predetermined frequency band from the output signal of the sampling circuits 13 , a buffer amplifier 15 , and a delay adjusting circuit 10 including a second LPF 14 b configured to extract DC component from an output signal of the sampling circuit 13 , and other components.
- the buffer amplifier 15 in FIG. 2 may be omitted from the configuration.
- the control circuit 16 performs control to adjust the amount of delay on the basis of the output signal of the second LPF 14 b so that the timing of sampling of an input signal in the sampling circuit 13 is synchronized with a zero crossing timing at which the transmission signal TX 1 crosses a zero level (zero potential).
- the control circuit 16 includes an operational amplifier (hereinafter abbreviated as op-amp) 16 a configured to output a difference signal, for example.
- op-amp operational amplifier
- the transmission signal TX 2 consists of a clock signal ⁇ o 1 generated from the transmission signal TX 1 and a clock signal ⁇ o 2 of opposite phase to the clock signal ⁇ o 1 .
- the clock signals ⁇ o 1 and ⁇ o 2 pass through the delay circuit 17 and become clock signals ⁇ 1 , ⁇ 2 acting as a sampling signal.
- the sampling circuit 13 samples an input signal by the clock signals ⁇ 1 , ⁇ 2 .
- a control loop is formed that adjusts the amount of delay (phase amount) according to the phase relation between the timing (phase) of a zero crossing of the transmission signal TX 1 and the timing (phase in which the input signal is sampled) of a trailing edge of the clock signal ⁇ 1 so that the difference between the phases decreases, as shown in FIGS. 4A to 4F , which will be described below.
- the delay adjusting circuit 10 in the present embodiment includes the control loop that automatically adjusts the phase of the sampling signal for sampling an input signal so that the phase becomes a predetermined phase on the basis of the output signal of the sampling circuit 13 .
- An output signal of the first LPF 14 a is input in a demodulation block 18 through the buffer amplifier 15 .
- the demodulation block 18 demodulates the reception signal RX.
- a reception signal RX and a transmission signal TX 1 are input in the sampling circuit 13 and the input signal is sampled by using clock signals ⁇ 1 , ⁇ 2 which constitute a transmission signal TX 2 having the same phase information as the transmission signal TX 1 .
- the output signal of the sampling circuit 13 is passed through the first LPF 14 a and second LPF 14 b thereby extracting separately a reception signal component with a frequency of
- the clock signals ⁇ 1 and ⁇ 2 have opposite phases as described below.
- a transmission signal TX 1 and a reception signal RX are input in the sampling circuit 13 as shown in FIGS. 4A and 4B .
- the first LPF output contains a noise component (the DC component of the second LPF output) larger than the reception signal RX.
- the output signal of the second LPF 14 b is input in the op-amp 16 a and a control loop functions to control the amount of delay of the delay circuit 17 so that the difference between the DC component of the second LPF output and a reference potential of zero is reduced to zero.
- the second LPF output becomes zero as shown in FIG. 5E . This means that the sampling at the timing of a zero crossing of the transmission signal TX 1 cancels the transmission signal TX 1 so that the transmission signal TX 1 does not appear in the output signal of the sampling circuit 13 .
- the present embodiment can be widely applied to cases where the frequency fT of a transmission signal differs from the frequency fR of a reception signal.
- the transmission signal component is sufficiently smaller than the reception signal component in the result of the simulation shown in FIG. 6 .
- the reception signal component varies in proportion to the input amplitude. Therefore, the reception signal component can be appropriately demodulated.
- a target reception signal to be received can be extracted in which a transmission signal TX 1 that is significant noise or interference wave interfering with the reception signal is cancelled or sufficiently reduced.
- FIG. 7 shows an exemplary configuration in which the amount of delay is adjusted in a digital fashion.
- the reception signal extracting unit 11 B shown in FIG. 7 uses a digital delay adjusting circuit 10 B which slightly differs from the delay adjusting circuit 10 in FIG. 2 .
- the output from the comparator 16 a in the configuration shown in FIG. 2 is an analog quantity whereas the output from the ADC 21 in FIG. 7 is a digital quantity.
- the configuration has the effect that, as compared with the analog output, the digital output is easy to deal with by adjusting parameters, for example.
- control operation for adjusting the amount of delay of the delay circuit 17 is performed for an appropriate period of time T 1 (see FIG. 8B ) in synchronization with a vertical synchronizing signal VD shown in FIG. 8A , for example. Then, the control operation for adjusting the amount of delay may be halted for a time period T 2 , for example, as shown in FIG. 8B . During the time period T 2 , the ADC 21 and the digital control circuit 22 may be placed in a power saving mode such as a hold state. After the time period T 2 , the control operation for adjusting the amount of delay may be resumed.
- a control loop is configured that automatically adjusts the timing (phase amount) of clock signals ⁇ 1 , ⁇ 2 for sampling in the sampling circuit 13 on the basis of an output signal of the sampling circuit 13 so that the timing is synchronized to the timing of a zero crossing of a transmission signal TX 1 .
- a delay adjusting unit 10 C which constitutes a reception signal extracting unit 11 C in the receiver 5 C includes a setting unit 31 configured to set the amount of delay and a variable delay element 32 whose delay is variably set to a predetermined fixed value by the setting unit 31 .
- the setting unit 31 is used to set the amount of delay to be produced by the variable delay element 32 to that zero-crossing delay amount.
- the setting unit 31 includes a memory 31 a , for example. Data representing the zero-crossing delay amount is written in the memory 31 a through a terminal Di beforehand so that the setting unit 31 can use the data stored in the memory 31 a to set the amount of delay to be produced by the variable delay element 32 to the zero-crossing delay amount.
- the transmitter 4 includes a transmission signal generating unit 34 configured to generate a transmission signal TX 2 (specifically, clock signals ⁇ o 1 and ⁇ o 2 ) from the transmission signal TX 1 .
- a transmission signal generating unit 34 configured to generate a transmission signal TX 2 (specifically, clock signals ⁇ o 1 and ⁇ o 2 ) from the transmission signal TX 1 .
- the present embodiment enables a reception signal to be extracted in which the influence of noise or an interference wave due to a transmission signal TX 1 is cancelled or sufficiently reduced with a simpler configuration than that of the first embodiment.
- the fixed value of the zero-crossing delay amount is used to cancel or sufficiently reduce the influence of an interference wave due to a transmission signal TX 1 to extract a reception signal.
- the data written in the memory 31 a can be changed after the maintenance to appropriately address the influence of the transmission signal TX 1 .
- FIG. 10 shows a delay adjusting circuit 10 D which is an example of such configuration.
- a selection signal is applied to the multiplexers M 1 , M 2 from a source such as a memory.
- the delay circuits D 1 , D 2 , and D 3 may be implemented by delay elements D that produce predetermined amounts of delay, for example.
- the delay circuit Dk that produces the amount of delay closest to the amount of delay that provides the timing of sampling at a zero crossing of a transmission signal TX 1 is selected. Both ends of each of the delay circuits that are not selected are grounded to prevent noise from being induced.
- One delay adjusting circuit 10 D in which clock signal ⁇ o 1 is input is shown in FIG. 10 . In practice, another delay adjusting circuit 10 D having the same configuration is used for clock signal ⁇ o 2 .
- a delay adjusting circuit (correctly a delay setting circuit in this case) including only one delay circuit Dk for clock signal ⁇ o 1 or ⁇ o 2 may be used.
- the present invention also includes embodiments configured by combining any parts of the embodiments described above.
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- Noise Elimination (AREA)
Abstract
Description
Claims (17)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007258008A JP4874919B2 (en) | 2007-10-01 | 2007-10-01 | Wireless device |
JP2007-258008 | 2007-10-01 |
Publications (2)
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US20090088201A1 US20090088201A1 (en) | 2009-04-02 |
US8112112B2 true US8112112B2 (en) | 2012-02-07 |
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Application Number | Title | Priority Date | Filing Date |
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US12/241,681 Expired - Fee Related US8112112B2 (en) | 2007-10-01 | 2008-09-30 | Radio apparatus and radio receiving method |
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US (1) | US8112112B2 (en) |
JP (1) | JP4874919B2 (en) |
CN (1) | CN101404510B (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4703452B2 (en) * | 2006-03-27 | 2011-06-15 | 富士通オプティカルコンポーネンツ株式会社 | Optical transceiver |
JP4874919B2 (en) * | 2007-10-01 | 2012-02-15 | 株式会社東芝 | Wireless device |
US9641205B1 (en) * | 2015-09-08 | 2017-05-02 | Amazon Technologies, Inc. | Active interference cancellation |
Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5757858A (en) * | 1994-12-23 | 1998-05-26 | Qualcomm Incorporated | Dual-mode digital FM communication system |
US5812607A (en) * | 1996-02-01 | 1998-09-22 | Qualcomm Incorporated | Method and apparatus for processing wideband data in a digital cellular communication system |
JP2000013274A (en) | 1998-06-26 | 2000-01-14 | Sharp Corp | Multimode radio device |
US20030071684A1 (en) | 1999-12-17 | 2003-04-17 | Basim Noori | Linearisation method and signal processing device |
JP2003133981A (en) | 2001-10-25 | 2003-05-09 | Matsushita Electric Ind Co Ltd | Dual-mode receiver and receiving method |
US20030102960A1 (en) * | 1994-06-20 | 2003-06-05 | Avid Marketing, Inc. | Electronic identification system with improved sensitivity |
WO2004114683A2 (en) | 2003-05-27 | 2004-12-29 | Interdigital Technology Corporation | Multi-mode radio with interference cancellation circuit |
US20050084238A1 (en) * | 1998-06-01 | 2005-04-21 | Kunio Kashino | High-speed signal search method, device, and recording medium for the same |
US20050094745A1 (en) * | 2003-10-30 | 2005-05-05 | Kenji Miyanaga | Ask demodulation device and wireless device using the same |
US20050135508A1 (en) * | 2003-12-22 | 2005-06-23 | Lg Electronics Inc. | Carrier recovery apparatus and broadcasting receiver using the same |
US20070099669A1 (en) * | 2005-10-26 | 2007-05-03 | Sadri Ali S | Communication signaling using multiple frequency bands in a wireless network |
US7383024B2 (en) | 2005-09-30 | 2008-06-03 | Avago Technologies Wireless Ip Pte Ltd | Multi-band handset architecture |
US20080143453A1 (en) * | 2006-12-13 | 2008-06-19 | Kiyotaka Ichiyama | Oscillator circuit, pll circuit, semiconductor chip, and test apparatus |
US20090088201A1 (en) * | 2007-10-01 | 2009-04-02 | Kabushiki Kaisha Toshiba | Radio apparatus and radio receiving method |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58133047A (en) * | 1982-02-02 | 1983-08-08 | Hagiwara Denki Kk | Eliminating method of hum superposed on signal |
JPH11345289A (en) * | 1998-06-01 | 1999-12-14 | Nippon Electric Ind Co Ltd | Signal shaping circuit for reader-writer for ic card |
JP2003124823A (en) * | 2001-10-16 | 2003-04-25 | Mitsubishi Electric Corp | System and method for removing interfering wave |
-
2007
- 2007-10-01 JP JP2007258008A patent/JP4874919B2/en not_active Expired - Fee Related
-
2008
- 2008-09-30 US US12/241,681 patent/US8112112B2/en not_active Expired - Fee Related
- 2008-10-06 CN CN2008101659843A patent/CN101404510B/en not_active Expired - Fee Related
Patent Citations (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030102960A1 (en) * | 1994-06-20 | 2003-06-05 | Avid Marketing, Inc. | Electronic identification system with improved sensitivity |
US5757858A (en) * | 1994-12-23 | 1998-05-26 | Qualcomm Incorporated | Dual-mode digital FM communication system |
US5812607A (en) * | 1996-02-01 | 1998-09-22 | Qualcomm Incorporated | Method and apparatus for processing wideband data in a digital cellular communication system |
US20050084238A1 (en) * | 1998-06-01 | 2005-04-21 | Kunio Kashino | High-speed signal search method, device, and recording medium for the same |
JP2000013274A (en) | 1998-06-26 | 2000-01-14 | Sharp Corp | Multimode radio device |
US20030071684A1 (en) | 1999-12-17 | 2003-04-17 | Basim Noori | Linearisation method and signal processing device |
JP2003133981A (en) | 2001-10-25 | 2003-05-09 | Matsushita Electric Ind Co Ltd | Dual-mode receiver and receiving method |
WO2004114683A2 (en) | 2003-05-27 | 2004-12-29 | Interdigital Technology Corporation | Multi-mode radio with interference cancellation circuit |
JP2007505591A (en) | 2003-05-27 | 2007-03-08 | インターディジタル テクノロジー コーポレイション | Multi-mode radio with interference cancellation circuit |
US20050094745A1 (en) * | 2003-10-30 | 2005-05-05 | Kenji Miyanaga | Ask demodulation device and wireless device using the same |
US20050135508A1 (en) * | 2003-12-22 | 2005-06-23 | Lg Electronics Inc. | Carrier recovery apparatus and broadcasting receiver using the same |
US7383024B2 (en) | 2005-09-30 | 2008-06-03 | Avago Technologies Wireless Ip Pte Ltd | Multi-band handset architecture |
US20070099669A1 (en) * | 2005-10-26 | 2007-05-03 | Sadri Ali S | Communication signaling using multiple frequency bands in a wireless network |
US20080143453A1 (en) * | 2006-12-13 | 2008-06-19 | Kiyotaka Ichiyama | Oscillator circuit, pll circuit, semiconductor chip, and test apparatus |
US20090088201A1 (en) * | 2007-10-01 | 2009-04-02 | Kabushiki Kaisha Toshiba | Radio apparatus and radio receiving method |
Also Published As
Publication number | Publication date |
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JP2009089175A (en) | 2009-04-23 |
CN101404510A (en) | 2009-04-08 |
US20090088201A1 (en) | 2009-04-02 |
JP4874919B2 (en) | 2012-02-15 |
CN101404510B (en) | 2013-08-14 |
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