US8076754B2 - Silicide-interface polysilicon resistor - Google Patents
Silicide-interface polysilicon resistor Download PDFInfo
- Publication number
- US8076754B2 US8076754B2 US11/684,277 US68427707A US8076754B2 US 8076754 B2 US8076754 B2 US 8076754B2 US 68427707 A US68427707 A US 68427707A US 8076754 B2 US8076754 B2 US 8076754B2
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- United States
- Prior art keywords
- silicide
- junctions
- resistor
- polysilicon
- layer
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 55
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 55
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 39
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 39
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 17
- 238000004519 manufacturing process Methods 0.000 claims description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 38
- 239000002019 doping agent Substances 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- 239000003870 refractory metal Substances 0.000 description 5
- 230000008901 benefit Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/8605—Resistors with PN junctions
Definitions
- the present invention relates to semiconductor manufacturing in general, and, in particular, to a method for manufacturing polysilicon resistors. Still more particularly, the present invention relates to a method for manufacturing silicide-interface polysilicon resistors.
- Semiconductor device fabrication involves a variety of processes and operations. Such operations include, but are not limited to, layering, doping, heat treatments, and patterning. Layering is the operation used to add layers of a selected thickness to a wafer surface.
- the layers can be insulators, semiconductors, and/or conductors, which can be grown or deposited by a number of suitable methods such as chemical vapor deposition, sputtering, etc.
- Doping is the process that introduces specific amounts of dopants in the wafer surface through openings in surface layers.
- Two general techniques of doping are thermal diffusion and ion implantation.
- Heat treatments are operations in which a wafer is heated and cooled to achieve specific results. Generally, no additional material is added although contaminates and vapors may evaporate from the wafer surface. A common heat treatment is called an anneal that is typically employed to repair damage to crystal structures introduced by ion implantation.
- Patterning is the operation that employs a series of steps that results in the removal of selected portions of added surface layers.
- the series of steps include forming a layer of resist or photoresist over a semiconductor device. Then, a resist mask or reticle is aligned with the semiconductor device. Subsequently, the layer of resist is exposed or irradiated through the resist mask, which selects portions of the layer of resist that are later removed to expose underlying portions of the semiconductor device.
- a fabrication process such as ion implantation, ion diffusion, deposition, and/or etching, can then be performed on exposed portions of the semiconductor device.
- Semiconductor devices typically include transistor and resistors. Many transistors have gate electrodes formed with polysilicon material. Similarly, many resistors are also formed with polysilicon material and are commonly referred to as polysilicon resistors or poly resistors.
- a silicide-interface polysilicon resistor includes a substrate, an oxide layer located on top of the substrate, and a polysilicon layer located on top of the oxide layer.
- the polysilicon layer includes multiple semiconductor junctions.
- the silicide-interface polysilicon resistor also includes a layer of silicide sheets, and at least one of the silicon sheets is in contact with one of the semiconductor junctions located within the polysilicon layer.
- FIGS. 1 a - 1 e are high-level process flow diagrams of a method for manufacturing a silicide-interface polysilicon resistor, in accordance with a preferred embodiment of the present invention
- FIGS. 2 a - 2 b depict the current flow within a silicide-interface polysilicon resistor, in accordance with a preferred embodiment of the present invention.
- FIG. 3 is a silicide-interface polysilicon resistor, in accordance with an alternative embodiment of the present invention.
- FIGS. 1 a - 1 e there are depicted multiple high-level process flow diagrams of a method for manufacturing a silicide-interface polysilicon resistor, in accordance with a preferred embodiment of the present invention.
- a field oxide layer 11 is deposited on top of a substrate 10 , as shown in FIG. 1 a .
- the thickness of field oxide layer 11 is preferably 0.4 ⁇ m.
- polysilicon layer 12 is deposited on top of field oxide layer 11 .
- Polysilicon layer 12 is then patterned to the shape and size of a desired polysilicon resistor, as deposited in FIG. 1 b .
- the thickness of polysilicon layer 12 is preferably 0.2 ⁇ m.
- Polysilicon layer 12 is subsequently implanted with N + dopants and P + dopants in an alternate (or interleaving) fashion, as shown in FIG. 11 c .
- N + dopants can be arsenic or phosphorus
- P + dopants can be boron.
- the N + doped regions and the P + doped regions are shown to be directly contacted with each other, it is understood by those skilled in the art that a small gap can be formed between an N + doped region and a P + doped region.
- An isolation layer is deposited on top of polysilicon layer 12 having N + and P + doped regions. Having a preferable thickness of 0.02 ⁇ m, the isolation layer can be made of silicon oxide or silicon nitride.
- the isolation layer is then etched according to a desired pattern to yield multiple silicide blocks 13 , which leaves all PN junctions in polysilicon layer 12 exposed, as depicted in FIG. 1 d .
- the purpose of silicide blocks 13 is to serve as a barrier such that silicide will not be formed on the areas under silicide blocks 13 .
- a refractory metal layer is then deposited on top of silicide blocks 13 as well as on top of the exposed PN junctions within polysilicon layer 12 .
- Refractory metal layer can be, for example, titanium, cobalt, nickel, platinum, etc. Heat is subsequently applied to transform refractory metal layer into silicide sheets at the exposed portions of polysilicon layer 12 . The portions on which the refractory metal layer situated on top of silicide blocks 13 remains to be a metal layer.
- All portions of the refractory metal layer situated on top of insulator layer 13 are then stripped off from polysilicon layer 12 to form a silicide-interface polysilicon resistor having silicide sheets 14 at various exposed portions of polysilicon layer 12 , as shown in FIG. 1 e.
- a redistribution of dopant atoms in polysilicon layer 12 occurs during the transformation of the metal to silicide sheets 14 , which may result in an impurity depletion zone located underneath the contact interface between silicide sheets 14 and polysilicon layer 12 . While silicide sheets 14 have a relatively low resistance in general, the impurity depletion zone can have a very high resistance. Such resistive property can be exploited by forcing current to repeatedly traverse the silicide interface, as described below.
- a silicide-interface polysilicon resistor 20 includes multiple N + and P + doped regions that yield PN junctions 23 - 26 at respective locations where an N + doped region meets a P + doped region.
- PN junction 23 is in contact with a silicide sheet 27 a
- PN junction 24 is in contact with a silicide sheet 27 b
- PN junction 25 is in contact with a silicide sheet 27 c
- PN junction 26 is in contact with a silicide sheet 27 d.
- Silicide-interface polysilicon resistor 20 also includes a contact 21 and a contact 22 .
- PN junctions 23 and 25 provide forward-bias to the current while PN junctions 24 and 26 provide reverse-bias to the current.
- the current is forced to flow through silicide sheet 27 b at PN junction 24 because silicide sheet 27 b has less resistance than the adjacent PN junction.
- the current is forced to flow through silicide sheet 27 d at PN junction 26 .
- PN junctions 23 - 26 can be placed closely together between contacts 21 and 22 , and the interface resistance of the corresponding silicide sheets associated with the PN junctions, such as silicide sheets 27 a - 27 d , can be quite high, a very high resistance silicide-interface polysilicon resistor can be achieved in a relatively small physical area.
- a silicide-interface polysilicon resistor 30 includes a substrate 31 , a field oxide layer 32 , a polysilicon layer 33 having alternate N + and P + doped regions. But instead of having one PN junction being contacted by one silicide sheet, two PN junctions are being contacted by one silicide sheet. For example, two PN junctions 34 - 35 being contacted by one silicide sheet 36 . Regardless of the direction of current flow (either from left to right or from right to left in FIG. 3 ), current will enter an N + doped region located between two P + doped regions.
- each silicide sheet in silicide-interface polysilicon resistor 30 is capable of handling current flowing in both directions.
- the advantage of this alternative embodiment over the preferred embodiment shown in FIGS. 2 a - 2 b is that a higher resistance can be maintained at high current levels because current is forced through every high-resistance silicide interface within silicide-interface polysilicon resistor 30 .
- the present invention provides a method for manufacturing silicide-interface polysilicon resistors.
- PN junctions are utilized the principle of the invention, it is understood by those skilled in the art that the present invention is also applicable to semiconductor junctions having an intrinsic regions such as PIN junctions, PIP junctions, or NIN junctions.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (10)
Priority Applications (1)
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US11/684,277 US8076754B2 (en) | 2007-03-09 | 2007-03-09 | Silicide-interface polysilicon resistor |
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US11/684,277 US8076754B2 (en) | 2007-03-09 | 2007-03-09 | Silicide-interface polysilicon resistor |
Publications (2)
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US20080217741A1 US20080217741A1 (en) | 2008-09-11 |
US8076754B2 true US8076754B2 (en) | 2011-12-13 |
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US11/684,277 Active US8076754B2 (en) | 2007-03-09 | 2007-03-09 | Silicide-interface polysilicon resistor |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20190289741A1 (en) * | 2018-03-16 | 2019-09-19 | Yazaki Corporation | Electrical junction box |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8748256B2 (en) | 2012-02-06 | 2014-06-10 | Texas Instruments Incorporated | Integrated circuit having silicide block resistor |
US10229966B2 (en) * | 2016-12-30 | 2019-03-12 | Texas Instruments Incorporated | Semiconductor resistor structure and method for making |
US20230395646A1 (en) * | 2022-06-07 | 2023-12-07 | Nxp Usa, Inc. | Polycrystalline semiconductor resistor |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5847988A (en) * | 1997-05-13 | 1998-12-08 | International Business Machines Corporation | ROM storage cell and method of fabrication |
US6088256A (en) * | 1998-09-25 | 2000-07-11 | Stmicroelectronics, Inc. | Integrated circuit with electrically programmable fuse resistor |
US6429492B1 (en) * | 1999-06-23 | 2002-08-06 | Bae Systems Information And Electronic Systems Integration, Inc. | Low-power CMOS device and logic gates/circuits therewith |
US6580156B1 (en) * | 2002-04-04 | 2003-06-17 | Broadcom Corporation | Integrated fuse with regions of different doping within the fuse neck |
US20060120143A1 (en) * | 2003-06-13 | 2006-06-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | SRAM cell design with high resistor CMOS gate structure for soft error rate improvement |
US7148556B2 (en) * | 2004-11-09 | 2006-12-12 | Lsi Logic Corporation | High performance diode-implanted voltage-controlled poly resistors for mixed-signal and RF applications |
US20070026579A1 (en) * | 2005-07-29 | 2007-02-01 | International Business Machines Corporation | Doped single crystal silicon silicided efuse |
US20070099326A1 (en) * | 2005-11-03 | 2007-05-03 | International Business Machines Corporation | eFuse and methods of manufacturing the same |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4488350A (en) * | 1981-10-27 | 1984-12-18 | Fairchild Camera & Instrument Corp. | Method of making an integrated circuit bipolar memory cell |
US6670824B2 (en) * | 2002-03-20 | 2003-12-30 | Agilent Technologies, Inc. | Integrated polysilicon fuse and diode |
US6933591B1 (en) * | 2003-10-16 | 2005-08-23 | Altera Corporation | Electrically-programmable integrated circuit fuses and sensing circuits |
-
2007
- 2007-03-09 US US11/684,277 patent/US8076754B2/en active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5847988A (en) * | 1997-05-13 | 1998-12-08 | International Business Machines Corporation | ROM storage cell and method of fabrication |
US6088256A (en) * | 1998-09-25 | 2000-07-11 | Stmicroelectronics, Inc. | Integrated circuit with electrically programmable fuse resistor |
US6429492B1 (en) * | 1999-06-23 | 2002-08-06 | Bae Systems Information And Electronic Systems Integration, Inc. | Low-power CMOS device and logic gates/circuits therewith |
US6580156B1 (en) * | 2002-04-04 | 2003-06-17 | Broadcom Corporation | Integrated fuse with regions of different doping within the fuse neck |
US20060120143A1 (en) * | 2003-06-13 | 2006-06-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | SRAM cell design with high resistor CMOS gate structure for soft error rate improvement |
US7148556B2 (en) * | 2004-11-09 | 2006-12-12 | Lsi Logic Corporation | High performance diode-implanted voltage-controlled poly resistors for mixed-signal and RF applications |
US20070026579A1 (en) * | 2005-07-29 | 2007-02-01 | International Business Machines Corporation | Doped single crystal silicon silicided efuse |
US20070099326A1 (en) * | 2005-11-03 | 2007-05-03 | International Business Machines Corporation | eFuse and methods of manufacturing the same |
Non-Patent Citations (1)
Title |
---|
Quirk et al., "Characteristics of Semiconductor Materials," Semiconductor Manufacturing Technology, Prentice Hall, 2001, pp. 33-39. * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20190289741A1 (en) * | 2018-03-16 | 2019-09-19 | Yazaki Corporation | Electrical junction box |
US10701827B2 (en) * | 2018-03-16 | 2020-06-30 | Yazaki Corporation | Electrical junction box with divided portions |
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US20080217741A1 (en) | 2008-09-11 |
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Owner name: SILICON LABORATORIES, TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YOUNG, STEVEN G.;SZMYD, DAVID M.;REEL/FRAME:019030/0682 Effective date: 20070307 |
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