US7991282B1 - Method and circuit for charging of super capacitor as energy source for flash diodes - Google Patents
Method and circuit for charging of super capacitor as energy source for flash diodes Download PDFInfo
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- US7991282B1 US7991282B1 US12/330,448 US33044808A US7991282B1 US 7991282 B1 US7991282 B1 US 7991282B1 US 33044808 A US33044808 A US 33044808A US 7991282 B1 US7991282 B1 US 7991282B1
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03B—APPARATUS OR ARRANGEMENTS FOR TAKING PHOTOGRAPHS OR FOR PROJECTING OR VIEWING THEM; APPARATUS OR ARRANGEMENTS EMPLOYING ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ACCESSORIES THEREFOR
- G03B15/00—Special procedures for taking photographs; Apparatus therefor
- G03B15/02—Illuminating scene
- G03B15/03—Combinations of cameras with lighting apparatus; Flash units
- G03B15/05—Combinations of cameras with electronic flash apparatus; Electronic flash units
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03B—APPARATUS OR ARRANGEMENTS FOR TAKING PHOTOGRAPHS OR FOR PROJECTING OR VIEWING THEM; APPARATUS OR ARRANGEMENTS EMPLOYING ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ACCESSORIES THEREFOR
- G03B15/00—Special procedures for taking photographs; Apparatus therefor
- G03B15/02—Illuminating scene
- G03B15/03—Combinations of cameras with lighting apparatus; Flash units
- G03B15/04—Combinations of cameras with non-electronic flash apparatus; Non-electronic flash units
- G03B15/0442—Constructional details of the flash apparatus; Arrangement of lamps, reflectors, or the like
- G03B15/0447—Energy sources; Batteries; Capacitors
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03B—APPARATUS OR ARRANGEMENTS FOR TAKING PHOTOGRAPHS OR FOR PROJECTING OR VIEWING THEM; APPARATUS OR ARRANGEMENTS EMPLOYING ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ACCESSORIES THEREFOR
- G03B7/00—Control of exposure by setting shutters, diaphragms or filters, separately or conjointly
- G03B7/26—Power supplies; Circuitry or arrangement to switch on the power source; Circuitry to check the power source voltage
Definitions
- the invention is related to electronic circuits, and in particular, to a method and circuit for charging a super capacitor to the optimal voltage needed to produce a desired flash current.
- Flash diodes actually LEDs (light emitting diodes), that emit white light when fired.
- the flash diode firing current is supplied from a voltage source, such as a lithium ion battery, that is carried by the camera or cell phone.
- FIG. 1 is a circuit diagram of a first embodiment of the invention
- FIG. 1A includes timing diagrams associated with an embodiment of the circuit of FIG. 1 ;
- FIG. 2 is diagram showing the fall off of voltage supplied by the super capacitor during the period of the firing of the flash diode for an embodiment of the circuit of FIG. 1 ;
- FIG. 3 is a circuit diagram of another embodiment of the circuit of FIG. 1 ;
- FIG. 3A includes timing diagrams associated with an embodiment of the circuit of FIG. 3 , in accordance with aspects of the present invention.
- the invention is related to a circuit having a flash diode that is supplied current from the voltage stored by a super capacitor in which the voltage to which the super capacitor is charged is controlled to an optimal value so as to produce a desired optimal current value that fires the diode. This minimizes the power that has to be dissipated in circuit elements other than the flash diode when the flash diode is fired.
- a circuit is provided that operates to charge the super capacitor while periodically firing the flash diode for very small time periods to sample the magnitude of the current through the flash LED at each of the sampling times and to optimally terminate the charging of the super capacitor at a voltage value that will produce the predetermined desired flash diode current when the diode is fired. This method of determining the charge termination instantly results in the optimal voltage on the super capacitor, which guarantees adequate voltage to provide the desired flash current, while minimizing power dissipation in all elements other than the flash diode.
- One embodiment of the circuit includes a charger to supply the charging voltage to the super capacitor whose output voltage is applied to a series circuit of the flash diode, a switching transistor, and a resistor used for sensing the current flowing in the series circuit.
- a controller starts a charging cycle for the super capacitor and affects the periodic sampling of the flash current by making the switching transistor conduct for short periods of time so that current flows through the flash diode and the sensing resistor.
- the magnitude of the flash current during each short sampling period increases with increasing super capacitor charge voltage and provides an indication as to when the super capacitor voltage is just high enough to deliver a given magnitude of current through the flash diode, switching transistor, and series sensing resistor.
- the voltage developed across the sensing resistor is applied to one input of a comparator whose other input is a reference voltage that, in conjunction with the sense resistor value, sets the predetermined desired flash current that is used to test for the optimal value of voltage to which the super capacitor is to be charged in order to achieve the desired current as the diode is flashed.
- a comparator determines that the charge voltage level of the super capacitor is at the desired optimal value, the charging of the super capacitor is terminated.
- a circuit is provided that adds the feature of keeping the current of the flash diode at a substantially constant level during the entire period of the firing of the flash diode when a sufficient voltage value has first been established on the super capacitor. This enables the super capacitor optimal voltage to be determined so that fall off in current supplied to the flash diode as the voltage of the super capacitor decreases during the time that the flash diode is being fired does not occur.
- the total amount of light output that is generated by the LEDs is proportional to the number of LEDs and the current supplied to each of them.
- the light output that is required by the camera image sensor determines the number of diodes used and the current supplied to each.
- a camera, cell phone, or other device can have one or more flash diodes connected in any desired series, parallel or series-parallel configuration as is required to produce the desired light output quantity. All of these configurations of one or more flash diodes are hereafter included within the use of the singular term “flash diode” hereinafter in the specification and claims.
- a super capacitor is a capacitor that has a high energy density when compared to common capacitors, typically on the order of thousands of times greater than a high-capacity electrolytic capacitor.
- Super capacitors having capacitance values of 0.1-1 F are currently commercially available.
- the super capacitor is charged from the battery by a charger to a voltage and the charge is stored.
- the super capacitor output voltage is applied to a series circuit of the flash diode and a switching device, such as a transistor, and the flash occurs by making the switching transistor go conductive causing current to flow through the flash diode.
- Embodiments of the invention relate to having a flash diode that is supplied current from the voltage stored by a super capacitor in which the voltage to which the super capacitor is charged is controlled to an optimal value so as to produce a desired optimal current value that fires the diode.
- the circuit 100 operates from a source of voltage Vdd that can be a lithium ion, or any other type of battery, or the like.
- the voltage Vdd is applied to the input of charger circuit 12 which can be any suitable circuit such as an LDO (low drop out linear regulator), pass device such as an MOS or bipolar transistor, a current-limited switch, or any suitable type of DC-to-DC voltage converter.
- the charger 12 can have a boost capability to enable it to produce an output voltage of greater value than Vdd or a buck capability to produce an output voltage less the value of Vdd.
- the charger may include other configurations, such as buck-boost or the like.
- the charger 12 produces a charging current Ichrg that is supplied to the upper terminal of a super capacitor 16 which charges to an increasing voltage Va as the charging current is being supplied.
- the super capacitor 16 has an equivalent series resistance component Resr 17 , such as caused by its connecting leads and other non-idealities, and a capacitor C component 18 .
- the lower terminal of the super capacitor is connected to a point of reference potential such as ground.
- the flash diode 20 is an LED that has a white light output.
- the flash diode 20 is an LED that has a white light output.
- the flash diode 20 includes a plurality of these diodes that can be used connected in any desired series, parallel or series-parallel configuration as is required to produce the desired light output quantity. All of these configurations of one or more flash diodes are hereafter included within the use of the singular term “flash diode”.
- the flash diode 20 has its anode coupled to the output terminal of the super capacitor to receive the capacitor voltage charge Va.
- Circuit 100 has a sampling circuit section S, which is arranged as follows in one embodiment.
- the cathode of the flash diode is coupled to the drain of a switching transistor M 1 whose source is connected to the upper terminal of a resistor 22 (Rsense) whose lower terminal is connected to ground.
- the resistor 22 senses the current flowing through the flash diode 20 and transistor M 1 when M 1 is conducting with the current sensed being represented by the voltage Vsense developed across the resistor 22 .
- the voltage Vsense provides an indication of how much flash current the super capacitor can deliver to the LED given the present voltage charge Va on the super capacitor.
- a controller-timer 30 that has three outputs. These are a periodic clock signal phi on line 32 , the inverted version of phi on line 34 , and a start clock pulse on line 36 .
- a switch driver, or buffer 26 receives its input from the output of an OR gate 25 and has its output connected to the gate of transistor M 1 .
- One input to the OR gate 25 is the periodic clock signal phi on the controller-timer output line 32 .
- the clock signal phi is used to make transistor M 1 periodically conduct as the super capacitor is being charged so as to sample the current that flows through the flash diode and the transistor M 1 , which is a function of the present value of the voltage Va to which the super capacitor has been charged.
- the second OR gate input is a “flash” operating signal produced by the camera or cell phone when the flash diode 20 is to be fired.
- the camera or cell phone has a button or switch that the user operates to produce the flash operating signal.
- the flash operating signal is a voltage that causes transistor M 1 to conduct and fire the flash diode.
- a flip flop 40 of the DQ type has a CLR input to which the start clock pulse output on line 36 of the controller 30 is applied.
- CLR is a logic high
- Q is forced to a logic low.
- the inverted version of the clock signal phi on line 34 of the controller is applied to the Z input of the flip-flop 40 .
- the Z input signifies a rising edge clock trigger and this indicates that the input at D is transferred to the output Q on the rising edge of the input clock pulse.
- the Q output of the flip-flop 40 produces a shutdown signal that is applied over line 42 to the SD (Shut Down) input of charger 12 to turn it off and stop the charging of the super capacitor 16 .
- a comparator 50 receives the voltage Vsense from the upper end of the sensing resistor 22 at its non-inverting (+) input.
- the inverting ( ⁇ ) input of comparator 50 is from a voltage reference source 54 that sets a voltage reference level Vref that sets the target Vsense that corresponds, in conjunction with sensing resistor 22 , to the target desired flash current.
- Vsense reaches the level of Vref
- the optimum voltage Vopt to which the super capacitor 16 is to be charged has been reached, and the resulting output transition of the comparator 50 indicates that the optimal super capacitor voltage has been reached.
- the capacitor voltage value Vopt is the value at which the capacitor is just able to provide the desired target flash current and the charging of the capacitor is terminated.
- the optimum capacitor voltage value is that needed to fire the flash diode at the predetermined target flash current so as not to produce excess heat that will have to be dissipated by the transistor M 1 and possibly other components of the camera device.
- a charging cycle for the super capacitor starts at time To and ends at time Tc when the super capacitor 16 is charged to the voltage Vopt.
- the charge is held until the user of the camera fires the flash diode by actuating the “flash” switch connected to the OR gate 25 input.
- This applies a firing signal that causes the transistor M 1 to conduct and produce a current by discharging the super capacitor that fires the flash diode.
- Line A of FIG. 1A shows a start clock pulse that is produced by controller 30 on line 36 that is applied to the CLR input of the flip-flop 40 to reset it. This causes the flip flop output Q to transition from the initial logic high state shown, to a logic low state.
- Line B shows this signal that is applied on line 42 and which is the shutdown logic signal for the charger 12 .
- the charger will produce Ichrg and start to charge the super capacitor.
- the controller 30 can produce the start clock pulse upon the camera being turned on, after the flash diode has been fired, when a capacitor optimal voltage charge refresh is desired, or for any other desired reason to establish the optimal capacitor charge voltage.
- the voltage charge Va on the super capacitor is shown on line E and it is a rising linear ramp for the case when Ichrg is a constant, which it may or may not necessarily be.
- Lines C and D show the periodic clock signals phi and not(phi) on lines 32 and 34 of the controller 30 .
- the periodic clock signal phi on line 32 of the controller 30 is applied through the OR gate 25 to the input of the switch driver 26 .
- the logical high intervals of the signal phi define the sampling interval of the flash current.
- the sampling intervals occur periodically during the time that the current Ichrg from the charger 12 increases the charge voltage Va on the super capacitor 16 .
- These logic high intervals of phi cause the transistor M 1 to conduct.
- M 1 conduction causes current to flow through the flash diode to briefly fire it and also causes current to flow through the resistor 22 to produce Vsense.
- the duration of the sampling intervals produced by the clock signals on controller output line 32 are very short relative to the entire time needed to charge the super capacitor.
- sampling intervals are minimized so that super capacitor discharge is minimal during the charging of the super capacitor. This helps to minimize the time required to charge the super capacitor to the optimal voltage.
- blip a slight decrease, or “blip”, “b”, in the super capacitor charge voltage Va each time that a sampling pulse causes the transistor M 1 to conduct. While three clock sampling pulses are shown on line C of FIG. 1A during the super capacitor charging period from To to Tc, there can be as many of these sampling pulses as desired. In practice Va changes very little between the intervals of the sampling pulses, and the time between sampling intervals is chosen to be much shorter than the over all time required to charge the super capacitor so that the optimal voltage is determined precisely and accurately.
- the waveform on line E is shown as changing relatively quickly for purposes of illustration.
- the comparator 50 produces an output Vc that is logically high when Vsense is greater than the reference voltage Vref from source 54 , and an output Vc that is logically low when Vsense is less than Vref from source 54 .
- the signal not(phi) from the controller line 34 transitions from low to high and triggers the transfer of the logical signal present at D, provided by Vc, to the output Q of flip flop 40 .
- the Q output is supplied to the charger 12 over line 42 .
- Vsense ⁇ Vref SD stays low and charging continues.
- Vsense>Vref SD is driven high and charging stops.
- the signal Vc is shown on line G.
- Tc the logic high from Vc is transferred to Q and the super capacitor is charged to its optimum voltage value Vopt that will produce the predetermined current value with which to fire the flash diode.
- V OFT V LED +I Flash ( R ON — M1 +R ESR +R sense ) (1)
- Vled is the forward voltage of LED 20
- I FLASH is the pre-determined diode flash current
- R ON — M1 is the on resistance of transistor M 1 when conducting
- R ESR is the resistance of resistor 17
- R sense is the resistance of sense resistor 22 .
- I FLASH is the magnitude of the current that exists in the flash diode during the last sample interval before charge termination, and also at the beginning of a flash firing period. Its value is:
- the super capacitor can hold the charge voltage Vopt until the user of the camera or cell phone actuates the button or switch that produces the flash signal at the input of the OR circuit 25 .
- the desired value (i.e., target value) of current that flows through the flash diode and the transistor M 1 is set by the voltage Vref and resistor Rsense.
- the optimum voltage Vopt to which the super capacitor has been charged guarantees that the desired value of current can be provided.
- FIG. 1 operates to charge the super capacitor to an optimum voltage that produces the desired predetermined current value in the flash diode when fired.
- FIG. 2 shows the effect on the stored super capacitor voltage during the time that the flash diode is being fired. This time in some measure depends on how long the camera operator actuates the firing switch.
- the super capacitor stored voltage for flashing the diode at the desired current value is at its optimum voltage charge value Vopt prior to the time of the user actuating the firing switch.
- the super capacitor starts to supply voltage Va to the flash diode from a value somewhat below Vopt due to the voltage drop Vesr across the super capacitor equivalent series resistance 17 .
- the voltage supplied from the super capacitor to the flash diode, Va decreases in a pseudo-linear manner during the time that the flash diode is being fired until the end of the firing “Flash End”. At that time Va will increase by V esr since the current through Resr 17 goes to zero.
- the voltage Va supplied to the flash diode decreases from Vopt by an amount Vdroop.
- the current through the flash diode decreases in a similar manner. That is, the current supplied to the diode is below the desired pre-determined value that is achieved only initially on the firing of the flash LED.
- the light output of the flash diode decreases over the duration of the flash as the firing current decreases.
- FIG. 3 shows an embodiment of circuit 300 .
- Circuit 300 is a modification of circuit 100 of FIG. 1 , where circuit 300 provides for the elimination of the current decrease during the flash diode firing period as explained above.
- Circuit 300 has the sampling section S and also has a current regulator section C. It differs from that of circuit 100 of FIG. 1 in that the switch driver 26 circuit 100 of FIG. 1 has been replaced by amplifier 126 , and the voltage Vsense that is an input to the comparator 50 is taken from the drain of M 1 , rather than from the source of M 1 as in FIG. 1 .
- a resistor 122 is connected from the source of M 1 to ground.
- a voltage V set from a source 127 applied to the non-inverting input of amplifier 126 , the amplifier 126 , transistor M 1 , and resistor 122 form a negative feedback system that operates as a current regulator that is arranged to provide a well regulated current through the drain of transistor M 1 by regulating the voltage Vfb at the source of M 1 to the voltage V set that is applied at the non-inverting input of amplifier 126 .
- An OR gate 125 receives the sampling voltage signal phi from controller line 32 at one input and the flash firing signal voltage at a second input. The OR gate 125 has an output EN applied to amplifier 126 . When the EN input to the amplifier 126 is high, the current regulator is enabled and current conducts.
- amplifier 126 drives the gate of M 1 low and current flow is ceased.
- EN When EN is high, the regulated current that flows into the drain of M 1 is equal to the voltage V set at the amplifier 126 non-inverting input divided by the resistance Rset of resistor 122 .
- the amplifier 126 drives the gate voltage of M 1 as high as the output compliance of the amplifier allows but the source of M 1 does not rise to a voltage equal to that at the non-inverting input of 126 .
- the current regulator composed of amplifier 126 , transistor M 1 , resistor 122 , and the voltage V set at the non-inverting input of amplifier 126 is said to be in “drop out”, meaning that the current regulator is not providing the desired output current determined by the reference input Vset and resistor 122 .
- the current regulator circuit keeps the M 1 drain current very constant.
- the voltage that is required at the drain of M 1 so that the desired output current is regulated is:
- V OH_min V SET ⁇ ( 1 + R ON_M ⁇ 1 R set ) ( 3 )
- V SET is the voltage applied at the non-inverting input of amplifier 126
- R ON — M1 is the “on” resistance of transistor M 1
- R set is the resistance of resistor 122 .
- M 1 drain current is less than V set /R set .
- M 1 drain current is equal to V set /R set .
- Circuit 300 operates very similarly to the circuit 100 of FIG. 1 with the difference being that the super capacitor optimal charge voltage Vopt is determined as the minimum capacitor voltage necessary to provide a constant flash current over the desired duration of the flash pulse.
- the optimal charge voltage Vopt in this case is that voltage which will allow the current regulator to remain out of the drop out condition throughout the flash duration, and will result in the drain voltage of M 1 decaying to V OH — min at the instant just prior to the end of the flash duration.
- This optimal voltage again minimizes power dissipation during the flash event, but now provides exactly the right “overhead voltage” so that a constant current can be maintained throughout the flash pulse. This is explained by referring to FIG. 3A .
- Line A of FIG. 3A shows the start clock pulse that starts the charging at To. This causes the flip flop 40 output Q to transition from the initial logic high state shown, to a logic low state.
- Line B shows this signal that is applied to the shutdown logic input for the charger 12 .
- the controller 30 can produce the start clock pulse upon the camera being turned on, after the flash diode has been fired, when a capacitor optimal voltage charge refresh is desired, or for any other desired reason to establish the optimal capacitor charge voltage.
- Lines C and D show the periodic clock signals phi and not(phi) on lines 32 and 34 , respectively, of the controller 30 with the high pulse intervals on line C being the current regulator overhead sampling pulses.
- the voltage charge Va on the super capacitor is shown on line E and it is shown as a rising linear ramp in this illustration.
- the clock signal phi on line 32 of the controller 30 is applied to the OR gate 125 that actuates the EN input of amplifier 126 .
- the OR gate 125 is used so that when either of the signals phi or Flash are a logic high, the current regulator conducts.
- the current regulator sinks a current equal to Vset/Rsense.
- the current regulator sinks no current.
- Line F shows that the drain voltage Vsense of M 1 is pulled low during each sampling pulse interval as the current regulator pulls current through the flash diode.
- Line G shows the voltage Vfb over the charge period, and illustrates that Vfb increases with Va during test pulses until Va is sufficient to provide a voltage greater than or equal to V OH — min at the drain of M 1 .
- the voltage during sampling pulses on line G is regulated to Vfb, indicating that a fixed test current is being fired during each interval from that time on.
- the sampling pulses continue until the Vsense voltage at the end of a test pulse as shown on line F reaches or just exceeds the reference voltage V oh applied to t the inverting ( ⁇ ) input of comparator 50 , which is set based on the predetermined desired flash current, flash duration, M 1 on-resistance, sense resistance 126 , and super capacitor C value C 18 .
- Vsense exceeds V OH during a test pulse
- the comparator 50 output Vc transitions high, and when the signal not(phi) transitions high, the logic high D input to the flip flop 40 is transferred to Q and shuts down the charger 12 . This event is shown to occur at time Tc in FIG. 3A .
- the reference voltage V OH can be set by the following equation to account for the “drop out” voltage V OH — min of the current regulator and the droop voltage of the super capacitor that occurs over the desired flash duration:
- I Flash is the predetermined desired flash current Vset/Rsense
- T Flash is the flash duration
- R- ON — M1 is the M 1 on resistance
- R set is the current regulator set resistance
- C is the capacitance of the super capacitor.
- equation (5) has the term V droop . This term represents the voltage droop that occurs on the super capacitor during the flash pulse determined by the flash duration, flash current level, and super capacitor capacitance.
- the current regulator When the user actuates the diode firing button or switch, the current regulator is enabled. At this time, the amplifier 126 impresses the voltage Vset across the Rset resistor 122 making the flash current equal to Vset/Rset. The current regulator maintains the desired current value substantially constant for the predetermined duration that the flash button or contact is actuated. Therefore, there will be a substantially steady current flow through the flash diode during its entire firing time and the Vdroop caused by the discharge of the super capacitor as shown in FIG. 2 will not affect the diode light output.
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Abstract
Description
V OFT =V LED +I Flash(R ON
Where Vled is the forward voltage of
Where VSET is the voltage applied at the non-inverting input of
Where IFlash is the predetermined desired flash current Vset/Rsense, TFlash is the flash duration, R-ON
V OFT =V LED +I Flash(R ON
Claims (20)
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US12/330,448 US7991282B1 (en) | 2008-12-08 | 2008-12-08 | Method and circuit for charging of super capacitor as energy source for flash diodes |
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20120104962A1 (en) * | 2010-02-26 | 2012-05-03 | Triune Ip Llc | Flash LED Controller |
DE102011112455A1 (en) * | 2011-09-03 | 2013-03-07 | Vision Components Gesellschaft für Bildverarbeitungsysteme mbH | Method for supplying power to LED in e.g. camera for image processing system, involves controlling output voltage of switching regulator by measured voltage drop as feedback signal during measuring period |
CN102983718A (en) * | 2012-11-30 | 2013-03-20 | 西安智海电力科技有限公司 | Power supply converting circuit capable of supporting various input waveforms |
US20140226059A1 (en) * | 2013-02-12 | 2014-08-14 | Non-Typical, Inc. | Illumination assembly for a scouting camera |
RU172180U1 (en) * | 2016-05-12 | 2017-06-30 | Юрий Пантелеевич Лепеха | POWER SUPPLY |
US10332676B2 (en) | 2011-03-24 | 2019-06-25 | Triune Systems, LLC | Coupled inductor system having multi-tap coil |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060159441A1 (en) * | 2005-01-14 | 2006-07-20 | Asia Optical Co., Inc. | Charging device for camera flash |
US20080136960A1 (en) * | 2000-07-25 | 2008-06-12 | Chikuni Kawakami | Electronic flash, electronic camera and light emitting head |
US20090128045A1 (en) * | 2007-11-16 | 2009-05-21 | Gregory Szczeszynski | Electronic Circuits for Driving Series Connected Light Emitting Diode Strings |
-
2008
- 2008-12-08 US US12/330,448 patent/US7991282B1/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080136960A1 (en) * | 2000-07-25 | 2008-06-12 | Chikuni Kawakami | Electronic flash, electronic camera and light emitting head |
US20060159441A1 (en) * | 2005-01-14 | 2006-07-20 | Asia Optical Co., Inc. | Charging device for camera flash |
US20090128045A1 (en) * | 2007-11-16 | 2009-05-21 | Gregory Szczeszynski | Electronic Circuits for Driving Series Connected Light Emitting Diode Strings |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20120104962A1 (en) * | 2010-02-26 | 2012-05-03 | Triune Ip Llc | Flash LED Controller |
US8704450B2 (en) * | 2010-02-26 | 2014-04-22 | Triune Ip, Llc | Flash LED controller |
US10332676B2 (en) | 2011-03-24 | 2019-06-25 | Triune Systems, LLC | Coupled inductor system having multi-tap coil |
DE102011112455A1 (en) * | 2011-09-03 | 2013-03-07 | Vision Components Gesellschaft für Bildverarbeitungsysteme mbH | Method for supplying power to LED in e.g. camera for image processing system, involves controlling output voltage of switching regulator by measured voltage drop as feedback signal during measuring period |
CN102983718A (en) * | 2012-11-30 | 2013-03-20 | 西安智海电力科技有限公司 | Power supply converting circuit capable of supporting various input waveforms |
CN102983718B (en) * | 2012-11-30 | 2016-06-08 | 西安智海电力科技有限公司 | The power-switching circuit of multiple input waveform can be supported |
US20140226059A1 (en) * | 2013-02-12 | 2014-08-14 | Non-Typical, Inc. | Illumination assembly for a scouting camera |
US9001265B2 (en) * | 2013-02-12 | 2015-04-07 | Non-Typical, Inc. | Illumination assembly for a scouting camera |
RU172180U1 (en) * | 2016-05-12 | 2017-06-30 | Юрий Пантелеевич Лепеха | POWER SUPPLY |
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