US7971120B2 - Method and apparatus for covering a multilayer process space during at-speed testing - Google Patents
Method and apparatus for covering a multilayer process space during at-speed testing Download PDFInfo
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- US7971120B2 US7971120B2 US12/340,072 US34007208A US7971120B2 US 7971120 B2 US7971120 B2 US 7971120B2 US 34007208 A US34007208 A US 34007208A US 7971120 B2 US7971120 B2 US 7971120B2
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2882—Testing timing characteristics
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
Definitions
- the present invention relates generally to design automation, and relates more particularly to statistical timing of integrated circuit (IC) chips.
- IC integrated circuit
- IC chips When IC chips come off the manufacturing line, the chips are tested “at-speed” to ensure that they perform correctly (and to filter out chips that do not perform correctly). In particular, a set of paths is selected, and the set of paths is then tested for each chip in order to identify the chips in which one or more of the selected paths fail timing requirements. Selection of these paths is complicated by the presence of process variations. Because of these variations, different paths can be critical in different chips. That is, a path that is critical in one chip may not be critical in another chip, and vice versa. As such, selection of the paths that have a higher probability of being critical is typically a goal.
- test pattern generation tools select these paths based on a single-layer process space coverage metric. As such, some points (i.e., combinations of process parameters) in the process space may only be covered by one path. If that path is not sensitizable (i.e., not capable of being tested), then these points in the process space may be left uncovered by the at-speed testing, resulting in a loss of test quality.
- the invention is a method and apparatus covering a multilayer process space during at-speed testing.
- One embodiment of a method for selecting a set of paths with which to test a process space includes determining a number N of paths to be included in the set of paths such that at least number M of paths in N for which testing of the process space will fail, computing a metric that substantially ensures that the set of paths satisfies the requirements of N and M, and outputting the metric for use in selecting the set of paths.
- FIG. 1 is a schematic diagram illustrating the concepts of the present invention
- FIG. 2 is a flow diagram illustrating one embodiment of a method for recursively computing a multilayer process coverage metric
- FIG. 3 illustrates an exemplary computation sequence graph for computing a multilayer process coverage metric
- FIG. 4 illustrates one embodiment of a binary tree data structure for use in updating a multilayer process coverage metric
- FIG. 5 is a high-level block diagram of the metric computation method that is implemented using a general purpose computing device.
- the present invention is a method and apparatus for covering a process space multiple times during at-speed testing of IC chips.
- Embodiments of the invention select paths for at-speed testing such that each point in the process space is covered at least “M” times, where M is a user definable parameter.
- M is a user definable parameter.
- at least M test paths cover each point.
- the redundancy achieved by controlling or customizing the coverage of the process space in this way improves the robustness of the at-speed testing process.
- ⁇ X is a k ⁇ 1 vector containing normalized Gaussian random variables to model the variation of the process parameters, including chip-to-chip, within chip, and local random variations.
- ⁇ N (1) ⁇ 1 ⁇ . . . ⁇ N (EQN. 2)
- a set of paths defines (or covers) a subspace of the entire process space such that by testing the set of paths at-speed, all bad chips manufactured under those process conditions can be sorted out.
- the corresponding process coverage metric C can thus be interpreted as:
- the subspace covered by path slack S 1 is C ⁇ D ⁇ E
- the subspace covered by path slack S 2 is B ⁇ C ⁇ D ⁇ F
- the subspace covered by path slack S 3 is A ⁇ B ⁇ C.
- ⁇ M (M) ⁇ 1 ⁇ . . . ⁇ M (EQN. 4)
- the subspace ⁇ M (M) is covered M times.
- the subspace covered at least M times by the set of N paths, ⁇ N (M) ⁇ ⁇ would be the union of ⁇ M,i (M) with each ⁇ m,i (M) covered by all paths forming a subset of M paths from ⁇ .
- ⁇ N ( M ) ⁇ ⁇ i ⁇ ( N M ) ⁇ comb ⁇ ( ⁇ M , i ( M ) ) ( EQN . ⁇ 5 )
- a multilayer process space coverage metric can be thus defined as:
- the result is B ⁇ C ⁇ D.
- the number of combinations is:
- N M (and, thus, for selecting the best set of test paths to achieve M-layer coverage) is discussed in greater detail below.
- C P(min ⁇ S i ⁇ S M ), where S i indicates the i th path slack of the set of paths selected for testing.
- embodiments of the present invention provide a multilayer process coverage metric. Referring back to EQN. 9:
- the present invention defines a function f N,k (S 1 , . . . , S N ) ⁇ k th smallest path slack of N path slacks S 1 , . . . , S N .
- f N,1 (S 1 , . . . , S N ) min(S 1 , . . . , S N ) is the statistical minimum of the N path slacks; and
- f N,N (S 1 , . . . , S N ) max(S 1 , . . .
- EQN. 14 or EQN. 15 one can improve the evaluation of an M-layer coverage metric C from exponential complexity to linear complexity (e.g., O(NM) in time, and O(N+M) in space).
- f N,M (S 1 , . . . , S N ) can be computed as shown in EQN. 14.
- R N,M (S 1 , . . . , S N ) the process space overlapped M times by N path slacks.
- R N,M (S 1 , . . . , S N ) R N ⁇ 1,M (S 1 , . . . , S N ⁇ 1 ) ⁇ R N ⁇ 1,M ⁇ 1 (S 1 , . . . , S N ⁇ 1 ) ⁇ R 1,1 (S N ) ⁇ .
- the process space covered M times by the path slacks S 1 through S N is the process space covered M times by path slacks S 1 through S N ⁇ 1 , plus the joint space of the process space covered by path slack S N and the process space covered M ⁇ 1 times by path slacks S 1 through S N ⁇ 1 .
- this relation can be represented as shown in EQN. 15.
- FIG. 2 is a flow diagram illustrating one embodiment of a method 200 for recursively computing a multilayer process coverage metric C by referring to EQN. 15.
- the method 200 is initialized at step 202 and proceeds to step 204 , where the method 200 receives (e.g., from a user) as input the desired level of coverage (M), the number (N) of paths having path slacks ( ⁇ S 1 , . . . , S N ⁇ ), and the required path slack S M .
- M desired level of coverage
- N number of paths having path slacks
- S M the required path slack S M .
- step 206 the method 200 computes a first value B 1 , where B 1 is the M ⁇ 1 th smallest path slack of N ⁇ 1 of the path slacks.
- B 1 f N ⁇ 1,M ⁇ 1 (S 1 , . . . , S N ⁇ 1 ).
- B 1 f 3,1 (S 1 , S 2 , S 3 ).
- step 208 the method 200 computes a second value B 2 , where B 2 is the M th smallest path slack of the N ⁇ 1 path slacks.
- B 2 f N ⁇ 1,M (S 1 , . . . , S N ⁇ 1 ).
- B 2 f 3,2 (S 1 , S 2 , S 3 ).
- step 210 the method 200 computes a third value B 3 , where B 3 is the maximum of the first value B 1 and the rest (last) path slack S N .
- B 3 max(B 1 , S N ).
- B 3 max(f 3,1 (S 1 , S 2 , S 3 ), S N ).
- step 212 the method 200 computes a fourth value B M , where B M is the minimum of the second value B 2 and the third value B 3 .
- B M min(B 2 , B 3 ).
- B M min((f 3,1 (S 1 , S 2 , S 3 )), (max(f 3,1 (S 1 , S 2 , S 3 ), S N ))).
- step 214 the method 200 computes the multilayer process coverage metric C as the probability that the fourth value B M is less than or equal to the required path slack S M .
- C P(B M ⁇ S M ).
- C P(min((f 3,1 (S 1 , S 2 , S 3 )), (max(f 3,1 (S 1 , S 2 , S 3 ), S N ))) ⁇ S M ).
- step 216 the method 200 outputs or stores the multilayer process coverage metric C (e.g., for use in at-speed testing or other applications) before terminating in step 218 .
- the multilayer process coverage metric C e.g., for use in at-speed testing or other applications
- the method 200 computes the multilayer process coverage metric C for M-layer coverage as the probability that the M th smallest path slack in the process space is less than the required path slack S M .
- Each recursion as shown in the method 200 requires two min/max operations, as shown below (same as EQN. 15).
- f N,M ( S 1 , . . . ,S N ) min( f N ⁇ 1,M ( S 1 , . . . ,S N ⁇ 1 ),max(f N ⁇ 1,M ⁇ 1 ( S 1 , . . . ,S N ⁇ 1 ), S N )) (EQN. 17)
- FIG. 3 illustrates an exemplary computation sequence graph 300 for computing the multilayer process coverage metric C.
- each node represents an input to a computation at a higher-level node
- each edge represents a single min or max operation.
- a given node's two input nodes and two edges (which correspond to the two inputs and the two min/max operations, respectively) are needed to compute the results stored at the given node according to EQN. 17.
- EQN. 17 By performing the computation along the dashed lines bottom-up and only keeping those results necessary for the next level of computation, one can compute all required order statistics (f 6,3 , f 6,2 , and f 6,1 ) in linear time O(NM and space O(N+M).
- the evaluation of the M-layer process coverage metric can be performed linearly.
- values of f N,M (S 1 , . . . , S N ) may be stored in a data structure such as a binary tree, allowing for quick computation and updating of the multilayer process coverage metric C.
- a second function g N,k (S 1 , . . . , S N ) is defined as: g N,k (S 1 , . . . ,S N ) ⁇ f N,1 (S 1 , . . . ,S N ),f N,2 (S 1 , . . . ,S N ), . . . ,f N,k (S 1 , . . .
- g N,k (S 1 , . . . , S N ) gives a set of k order statistics for N path slacks S 1 , . . . , S N .
- g N,k ( ⁇ ) ⁇ f N,1 ( ⁇ ), f N,2 ( ⁇ ), . . . , f N,N ( ⁇ ) ⁇ if N ⁇ k, i.e.:
- g N , k ⁇ ( S 1 , ... ⁇ , S N ) ⁇ f N , 1 ⁇ ( ⁇ ) , ... ⁇ , f N , k ⁇ ( ⁇ ) ⁇ ⁇ if ⁇ ⁇ N ⁇ k f N , 1 ⁇ ( ⁇ ) , ... ⁇ , f N , N ⁇ ( ⁇ ) ⁇ ⁇ if ⁇ ⁇ N ⁇ k ( EQN . ⁇ 19 )
- FIG. 4 illustrates one embodiment of a binary tree data structure 400 for use in updating a multilayer process coverage metric.
- the binary tree comprises a plurality of interconnected nodes D, where each leaf node (e.g., nodes S 1 , S 2 , . . . , S N ) corresponds to one path slack S i .
- each leaf node e.g., nodes S 1 , S 2 , . . . , S N
- the node slack set Q D At every node D in the tree, two sets of slacks are stored: the node slack set Q D and the complement node slack set Q D .
- the former contains the first to M th order statistics of all downstream leaf node slacks; the latter contains the first to M th order statistics of all but the downstream leaf node slacks.
- Q D g 2M,M ( Q Dleft ⁇ Q Dright ) (EQN. 20)
- Q D g 2M,M ( Q Dlparent ⁇ Q Dsibling ) (EQN. 21) where D left , D right , D parent , and D sibling are node D's left child, right child, parent, and sibling nodes, respectively.
- the first traversal is bottom-up from the leaves to the root by computing all node slack sets Q D via EQN. 20; the second traversal is top-down from the root to the leaves by computing all complement node slack sets Q D via EQN. 21.
- the complexity of constructing the binary tree data structure 400 is O(NM 2 ).
- C P ( f M+1,M ( g ( S N ),M , ⁇ tilde over (S) ⁇ N ) ⁇ S M ) (EQN. 25) by replacing the previous S N with the newly chosen ⁇ tilde over (S) ⁇ N .
- the replacement can be performed in O(N 2 M) time by updating the data structure 400 illustrated in FIG. 4 as follows. To perform bottom-up updating, one thread of a path from this leaf node to the root is used. To perform top-down updating, all internal nodes O(N) are used. The total complexity is O(NM 2 ).
- the complexity of updating the multilayer process coverage metric C can be reduced from O(N 2 M) to O(NM 2 ).
- the number of required paths N is on the order of thousands, while the number of required layers M for coverage is less than ten. Therefore, the complexity is reduced from quadratic O(N 2 ) to linear O(N).
- the multilayer process coverage metric may be used in place of a single-layer process coverage metric in substantially any circumstances where a single-layer process coverage metric is used.
- the branch and bound type framework for path selection described in U.S. patent application Ser. No. 12/244,512 which is herein incorporated by reference in its entirety, may be adapted to benefit from the multilayer process coverage metric of the present invention.
- the selected paths may be efficiently maintained and updated using a binary tree data structure or other data structure.
- process coverage metric of the present invention is described within the context of design automation, the process coverage metric may have application in other fields as well.
- process coverage metric is described within the context of path selection for at-speed testing, the process coverage metric may have application in other aspects of design automation where path selection plays a role (e.g., variation-aware critical path reporting, common path pessimism removal, chip binning, yield optimization).
- path selection plays a role (e.g., variation-aware critical path reporting, common path pessimism removal, chip binning, yield optimization).
- one or more of N, M, and S M may be user defined.
- FIG. 5 is a high-level block diagram of the metric computation method that is implemented using a general purpose computing device 500 .
- a general purpose computing device 500 comprises a processor 502 , a memory 504 , a metric computation module 505 and various input/output (I/O) devices 506 such as a display, a keyboard, a mouse, a stylus, a wireless network access card, and the like.
- I/O devices 506 such as a display, a keyboard, a mouse, a stylus, a wireless network access card, and the like.
- at least one I/O device is a storage device (e.g., a disk drive, an optical disk drive, a floppy disk drive).
- the metric computation module 505 can be implemented as a physical device or subsystem that is coupled to a processor through a communication channel.
- the metric computation module 505 can be represented by one or more software applications (or even a combination of software and hardware, e.g., using Application Specific Integrated Circuits (ASIC)), where the software is loaded from a storage medium (e.g., I/O devices 506 ) and operated by the processor 502 in the memory 504 of the general purpose computing device 500 .
- a storage medium e.g., I/O devices 506
- the metric computation module 505 for computing a multilayer process coverage metric can be stored on a computer readable storage medium or carrier (e.g., RAM, magnetic or optical drive or diskette, and the like).
- one or more steps of the methods described herein may include a storing, displaying and/or outputting step as required for a particular application.
- any data, records, fields, and/or intermediate results discussed in the methods can be stored, displayed, and/or outputted to another device as required for a particular application.
- steps or blocks in the accompanying Figures that recite a determining operation or involve a decision do not necessarily require that both branches of the determining operation be practiced. In other words, one of the branches of the determining operation can be deemed as an optional step.
Abstract
Description
ωi ={ΔX|S i =F i(ΔX)≦0} (EQN. 1)
ωN (1)=ω1∪ . . . ∪ωN (EQN. 2)
where |·| is a Lebesgue measure (i.e., probability-weighted area) of the process space.
ωM (M)=ω1∪ . . . ∪ωM (EQN. 4)
number of ωM,i (M). Mathematically, this is expressed as:
ω3 (2)=(ω1∩ω2)∪(ω1∩ω3)∪(ω2∩ω3) (EQN. 7)
The result is B∪C∪D. Thus, in general, for M=2, one has:
More generally:
The number of combinations is:
Embodiments of methods for efficiently determining
(and, thus, for selecting the best set of test paths to achieve M-layer coverage) is discussed in greater detail below.
C=P(path slack≦S M) (EQN. 11)
For single-layer coverage (i.e., M=1), C=P(min{Si}≦SM), where Si indicates the ith path slack of the set of paths selected for testing. In other words, the process coverage metric for single-layer coverage is the weighted area covered by all paths selected for testing. For instance, referring to the
Where M=2, the combinations of paths are O(N2); however, for M>2, the combinations are exponentially larger (i.e., O(N3)˜O(2N)). Brute force computation of the multilayer process coverage metric C is therefore likely to be infeasible to compute in most cases. The present invention therefore provides methods for efficiently computing the multilayer process coverage metric C, described in greater detail below with respect to
C=P(f N,k(S 1 , . . . ,S N)≦S M) (EQN. 13)
f N,M(S 1 ,S N)=f M+1,M(f N−1,1(S 1 , . . . ,S N−1), . . . ,f N−1,M(S 1 , . . . ,S N−1),S N) (EQN. 14)
or as
f N,M(S 1 , . . . ,S N)=min(f N−1,M(S 1 , . . . ,S N−1),max(f N−1,M−1(S 1 , . . . ,S N−1),S N)) (EQN. 15)
- min{max{S1, S2}, max{S1, S3}, max{S1, S4}, max{S2, S3}, max{S2, S4}, max{S3, S4}≦SM
- if and only if
- the second smallest path slack of {S1, S2, S3, S4}≦SM.
f 4,2(S 1 ,S 2 ,S 3 ,S 4)=f 3,2(f 3,2(f 3,1(S 1 ,S 2 ,S 3),f 3,2(S 1 ,S 2 ,S 3)S 4)
f 5,2(S 1 ,S 2 ,S 3 ,S 4 ,S 5)=f 3,2(f 4,1(S 1 ,S 2 ,S 3 ,S 4),f 4,2(S 1 ,S 2 S 3 ,S 4),S 5)
f 6,2(S 1 ,S 2 ,S 3 ,S 4 ,S 5 ,S 6)=f 3,2(f 5,1(S 1 ,S 2 ,S 3 ,S 4 ,S 5),f 5,2(S 1 ,S 2 ,S 3 ,S 4 ,S 5),S 6)
. . .
fN,2(S 1 , . . . ,S N)=f 3,2(f N−1,1(S 1 , . . . ,S N−1),f N−1,2(S 1 , . . . ,S N−1),S N)
. . .
f N,M(S 1 , . . . ,S N)=f M+1,M(f N−1,1(S 1 , . . . ,S N−1), . . . ,f N−1,M S 1 , . . . ,S N−1),S N)
Thus, as the pattern implies, fN,M(S1, . . . , SN) can be computed as shown in EQN. 14.
C=P(f N,M(S 1 , . . . ,S N)≦S M), (EQN. 16)
thus confirming the logic of the
f N,M(S 1 , . . . ,S N)=min(f N−1,M(S 1 , . . . ,S N−1),max(fN−1,M−1(S 1 , . . . ,S N−1),S N)) (EQN. 17)
gN,k(S1, . . . ,SN)≡{fN,1(S1, . . . ,SN),fN,2(S1, . . . ,SN), . . . ,fN,k(S1, . . . ,SN)} (EQN. 18)
In other words, gN,k(S1, . . . , SN) gives a set of k order statistics for N path slacks S1, . . . , SN. Furthermore, gN,k(·)={fN,1(·), fN,2(·), . . . , fN,N(·)} if N<k, i.e.:
Q D =g 2M,M(Q Dleft ∪Q Dright) (EQN. 20)
where Dleft, Dright, Dparent, and Dsibling are node D's left child, right child, parent, and sibling nodes, respectively.
QS
C=P(f M+1,M(g N−1,M(S 1 , . . . ,S N−1),S N)≦SM) (EQN. 24)
This is easy to update if the path slack at a leaf node (for example, SN) is replaced.
C=P(f M+1,M(g (
by replacing the previous SN with the newly chosen {tilde over (S)}N. If the newly computed process coverage metric is better, the replacement can be performed in O(N2M) time by updating the
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US8104005B2 (en) * | 2008-10-02 | 2012-01-24 | International Business Machines Corporation | Method and apparatus for efficient incremental statistical timing analysis and optimization |
US8340939B2 (en) * | 2009-10-30 | 2012-12-25 | International Business Machines Corporation | Method and apparatus for selecting paths for use in at-speed testing |
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US20100162064A1 (en) | 2010-06-24 |
KR20100071889A (en) | 2010-06-29 |
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