US7939884B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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US7939884B2
US7939884B2 US11/922,092 US92209206A US7939884B2 US 7939884 B2 US7939884 B2 US 7939884B2 US 92209206 A US92209206 A US 92209206A US 7939884 B2 US7939884 B2 US 7939884B2
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epitaxial layer
region
trench
semiconductor device
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Masaru Takaishi
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Rohm Co Ltd
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Rohm Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156—Drain regions of DMOS transistors
    • H10D62/157—Impurity concentrations or distributions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/256—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies

Definitions

  • the present invention relates to a semiconductor device and, particularly, to a semiconductor device including a MOSFET configured along side surfaces of trenches.
  • trench semiconductor device In recent years, there has been an increasing demand for a semiconductor device including a MOSFET configured along side surfaces of trenches (hereinafter referred to as “trench semiconductor device”), because this semiconductor device has a lower ON resistance than a semiconductor device including a MOSFET (planar DMOSFET (double diffused MOSFET)) configured along an upper surface of an epitaxial layer.
  • MOSFET planar DMOSFET (double diffused MOSFET)
  • the semiconductor device 101 includes an N ⁇ type epitaxial layer 111 provided on an upper surface of an N type semiconductor substrate 110 .
  • a plurality of trenches (grooves) 120 are provided in the epitaxial layer 111 as extending downward from an upper surface of the epitaxial layer 111 .
  • a MOSFET is configured along opposite side surfaces of the trenches 120 .
  • a gate electrode 121 is embedded in each of the trenches, and an N + type source region 113 and a P ⁇ type base region 114 are arranged in this order toward a lower side along each of the opposite side surfaces of the trenches 120 .
  • a portion of the epitaxial layer 111 below the base region 114 serves as an N ⁇ type drain region 115 .
  • a base high concentration region 116 is provided adjacent the source region 113 and the base region 114 in spaced relation from the trench 120 as extending downward from the upper surface of the epitaxial layer 111 .
  • the base high concentration region 116 has the same conductivity type as the base region 114 and a higher impurity concentration than the base region 114 , and is shallower than the base region 114 .
  • the base high concentration region 116 has an ohmic contact with a source electrode 125 to be described later, and reduces the resistance component of the base region 114 .
  • a gate insulating film 122 of a thin silicon oxide film is provided between the trench 120 and the gate electrode 121 .
  • the gate insulating film 122 extends onto the upper surface of the epitaxial layer 111 .
  • an interlayer insulating film 123 is provided on the gate electrode and the gate insulating film 22 as partly covering the upper surface of the epitaxial layer 111 .
  • the gate insulating film 122 and the interlayer insulating film 123 each have an etched-off portion serving as a contact hole 124 on a part of the source region 113 and an upper surface of the base high concentration region 116 .
  • a metal layer is provided as the source electrode 125 to provide electrical contacts to the source region 113 and the base high concentration region 116 through the contact hole 124 .
  • depletion layers 140 and 141 are formed as respectively spreading from lower surfaces of the base region 114 and the trench 120 into the drain region 115 in the epitaxial layer 111 as shown in FIG. 5 .
  • the depletion layer 140 spreading from the base region 114 has a relatively great width, while the depletion layer 141 spreading from the lower surface of the trench 120 has a relatively small width.
  • a gate-drain capacitance CGD which is a capacitance between the gate electrode 121 and the drain region 115 is generally equal to a capacitance provided by serially coupling the capacitance of the gate insulating film 122 with the capacitance of the depletion layer 141 formed below the lower surface of the trench 120 .
  • the value of the capacitance of the depletion layer 141 is inversely proportional to the width of the depletion layer 141 . Therefore, the depletion layer 141 , if having a smaller width, has a greater capacitance value, resulting in a greater gate-drain capacitance CGD. Conversely, the depletion layer 141 , if having a greater width, has a smaller capacitance value, resulting in a smaller gate-drain resistance CGD.
  • the inventor of the present invention previously proposes a semiconductor device having a planar DMOSFET which ensures a reduced turn-on time to achieve a higher speed switching capability.
  • the gate-drain capacitance CGD can be reduced by controlling the orientation and the width of a depletion layer in an OFF state. As a result, the turn-on time is reduced.
  • the inventor of the present invention has come up with an idea that, if the art of the previous patent application is modified to be applied to a trench semiconductor device, it is possible to achieve a further higher speed switching capability with a reduced turn-on time and a lower ON resistance, and accomplished the present invention.
  • a semiconductor device includes: a first epitaxial layer provided on a semiconductor substrate; a second epitaxial layer provided in contact with an upper surface of the first epitaxial layer and having a lower impurity concentration than the first epitaxial layer; a plurality of trenches provided in the second epitaxial layer as extending downward from an upper surface of the second epitaxial layer; a gate electrode embedded in each of the trenches; a source region extending downward from the upper surface of the second epitaxial layer along each of opposite side surfaces of the trench; a base region extending downward from a lower surface of the source region along each of the opposite side surfaces of the trench; and a base high concentration region provided adjacent the source region and the base region in spaced relation from the trench as extending downward from the upper surface of the second epitaxial layer to a greater depth than the base region, and having the same conductivity type as the base region and a higher impurity concentration than the base region.
  • An interlayer insulating film may be provided on the gate electrode as covering a part of the upper surface of the second epitaxial layer, and a source electrode may be provided in contact with the interlayer insulating film, a part of the source region and an upper surface of the base high concentration region.
  • a buried insulating film may be provided on the gate electrode to fill the trench to the vicinity of an opening edge of the trench, and a source electrode may be provided in contact with the buried insulating film, the source region and an upper surface of the base high concentration region.
  • depletion layers spreading from base high concentration regions disposed on the opposite sides of the trench are merged with each other at a position below the trench when the semiconductor device is in an OFF state.
  • a gate-drain capacitance CGD is reduced, thereby reducing a turn-on time.
  • FIG. 1 is a sectional view of a semiconductor device according to a preferred embodiment of the present invention.
  • FIG. 2 is a sectional view illustrating an OFF state of the semiconductor device.
  • FIG. 3 is a sectional view of a semiconductor device according to another preferred embodiment of the present invention.
  • FIG. 4 is a sectional view of a conventional semiconductor device.
  • FIG. 5 is a sectional view illustrating an OFF state of the conventional semiconductor device.
  • FIG. 1 is a sectional view of a semiconductor device according to a preferred embodiment of the present invention.
  • the semiconductor device 1 includes an N ⁇ type first epitaxial layer 11 provided on an N type semiconductor substrate 10 (for example, having an impurity concentration of about 10 19 /cm 3 ) and having the same conductivity type as the semiconductor substrate 10 and a lower impurity concentration (e.g., an impurity concentration of about 10 16 /cm 3 ) than the semiconductor substrate 10 , and an N ⁇ type second epitaxial layer 12 provided in contact with an upper surface of the first epitaxial layer 11 and having the same conductivity type as the first epitaxial layer 11 and a lower impurity concentration (e.g., an impurity concentration of about 10 15 /cm 3 ) than the first epitaxial layer 11 .
  • the semiconductor device 101 described in BACKGROUND ART is of a single epitaxial layer structure including the epitaxial layer 111 , but the semiconductor device 1 is of a double epitaxial layer structure obtained by forming the second epitaxial layer 12 on the upper surface of the first epitaxial layer 11 which corresponds to the epitaxial layer 111 .
  • a plurality of trenches 20 are provided in the second epitaxial layer 12 as extending downward from an upper surface of the second epitaxial layer 12 .
  • a MOSFET is configured along opposite side surfaces of the trenches 20 . That is, a gate electrode 21 is embedded in each of the trenches 20 .
  • Provided along each of the opposite side surfaces of the trench are an N + type source region 13 extending downward from the upper surface of the second epitaxial layer 12 and a P ⁇ type base region 14 extending downward from a lower surface of the source region 13 .
  • a portion of the epitaxial layer 12 below the base region 14 and a base high concentration region 16 to be described later serves as an N ⁇ type drain region 15 .
  • the base high concentration region 16 is disposed adjacent the source region 13 and the base region 14 in spaced relation from the trench 20 as extending downward from the upper surface of the second epitaxial layer 12 .
  • the base high concentration region 16 has the same conductivity type as the base region 14 and a higher impurity concentration than the base region 14 , and is formed as extending to a greater depth than the base region 14 , and to have a depth that is smaller than a depth of the trenches 20 .
  • the base high concentration region 16 has an ohmic contact with a source electrode 25 to be described later, and reduces the resistance component of the base region 14 . As will be described later, the base high concentration region 16 has an important function for reducing a gate-drain capacitance CGD when the semiconductor device 1 is in an OFF state.
  • the source region 13 , the base region 14 and the base high concentration region 16 are provided in a portion of the second epitaxial layer 12 , and the rest of the second epitaxial layer 12 serves as the drain region 15 .
  • the first epitaxial layer 11 provided below the second epitaxial layer 12 in contact with the drain region 15 also serves as a part of the drain region.
  • the second epitaxial layer 12 (drain region 15 ) has a low impurity concentration such that, when the semiconductor device is in the OFF state, depletion layers respectively spreading from base high concentration regions 16 disposed on opposite sides of each trench 20 are merged with each other at a position below the trench 20 .
  • a gate insulating film 22 of a thin silicon oxide film is provided between the trench 20 and the gate electrode 21 .
  • the gate insulating film 22 extends onto the upper surface of the second epitaxial layer 12 .
  • an interlayer insulating film 23 is provided over the gate electrode 21 and the gate insulating film 22 as covering a part of the upper surface of the second epitaxial layer 12 .
  • the gate insulating film 22 and the interlayer insulating film 23 each have an etched-off portion serving as a contact hole 24 on a part of the source region 13 and an upper surface of the base high concentration region 16 .
  • a metal layer is provided as a source electrode 25 to provide electrical contacts to the source region 13 and the base high concentration region 16 through the contact hole 24 . Therefore, the source electrode 25 (mechanically) contacts the interlayer insulating film 23 , the part of the source region 13 and the upper surface of the base high concentration region 16 .
  • the first epitaxial layer 11 is formed on the semiconductor substrate 10 by an epitaxial technique
  • the second epitaxial layer 12 is formed on the first epitaxial layer 11 by an epitaxial technique
  • the base high concentration region 16 is formed as extending to a greater depth than the base region 41 by an impurity diffusion technique or an impurity implantation technique.
  • the semiconductor device 1 is in the ON state when a gate-source voltage VGS which is a voltage between the gate electrodes 21 and the source electrode 25 is not less than a threshold, and is in the OFF state when the gate-source voltage VGS is less than the threshold.
  • VGS gate-source voltage
  • channel layers are formed in the base regions 14 , so that ON electric current flows from the semiconductor substrate 10 to the source electrode 25 through the first epitaxial layer 11 , the drain region 15 , the base regions 14 and the source regions 13 .
  • a drain-source voltage VDS which is a voltage between the semiconductor substrate 10 and the source electrode 25 is generally reduced.
  • the drain-source voltage VDS is higher (e.g., 20V), so that the depletion layers 40 occur as shown in FIG. 2 .
  • the base high concentration region 16 is formed as having a greater depth and a higher impurity concentration than the base region 14 and, therefore, a depletion layer 40 spreading depthwise and laterally from the base high concentration region 16 fills the drain region 15 having a very low impurity concentration to extend into an inner portion of the first epitaxial layer 11 . That is, the depletion layers 40 spreading from the base high concentration regions 16 disposed on the opposite sides of each trench 20 are merged with each other below the trench 20 . Depletion layers spreading from lower surfaces of the base region 14 and the trench 20 are completely contained in and integrated with the depletion layers 40 widely spreading from the base high concentration regions 16 .
  • the depletion layer 40 present below the lower surface of the trench 20 has a greater width, so that the depletion layer portion has a smaller capacitance value. Since the gate-drain capacitance CGD is equal to a capacitance obtained by serially coupling the capacitance of the gate insulating film 22 and the capacitance of the depletion layer portion formed below the lower surface of the trench 20 as described above, the gate-drain capacitance CGD is reduced. As a result, the semiconductor device 1 has a reduced turn-on time, thereby achieving higher speed switching.
  • the width of the depletion layer portion present below the lower surface of the trench 20 is increased and, therefore, the gate-drain capacitance CGD is reduced.
  • the drain region 15 in the second epitaxial layer 12 has a higher resistivity. Therefore, if the distance from the lower surface of the trench 20 to the upper surface of the first epitaxial layer 11 is increased, the semiconductor device 1 is liable to have an increased ON resistance in the ON state. Therefore, it is necessary to determine the distance from the lower surface of the trench 20 to the upper surface of the first epitaxial layer 11 so that the resulting ON resistance is within a permissible range.
  • FIG. 3 is a sectional view of the semiconductor device 2 .
  • the semiconductor device 2 includes a semiconductor substrate 10 , a first epitaxial layer 11 and a second epitaxial layer 12 .
  • Source regions 13 , base regions 14 , base high concentration regions 16 and a drain region 15 are provided in the second epitaxial layer 12 .
  • Gate electrodes 21 are respectively embedded in trenches 20 provided in the second epitaxial layer 12 .
  • buried insulating films 26 are respectively provided on the gate electrodes 21 to fill the trenches to the vicinities of opening edges of the trenches 20 for isolation between the gate electrodes 21 and the source electrodes 25 .
  • a source electrode 25 is provided over and in contact with upper surfaces of the buried insulating films 26 , the source regions 13 and the base high concentration regions 16 .
  • the buried insulating films 26 of the semiconductor device 2 are provided at a level not higher than the upper surface of the second epitaxial layer 12 . Therefore, there is no need to provide contact holes for electrically contacting the source electrode 25 to the source regions 13 and the base high concentration regions 16 . As a result, microminiaturization can be achieved to locate the base high concentration regions 16 closer to the trenches 20 . Therefore, even if the impurity concentration of the second epitaxial layer 12 is higher than in the semiconductor device 1 , depletion layers 40 spreading from the base high concentration regions 16 disposed on opposite sides of each trench 20 are merged with each other at a position below the trench 20 . Thus, the drain region 15 in the second epitaxial layer 12 is permitted to have a relatively low resistivity, thereby suppressing an increase in ON resistance.
  • the MOSFET configured along the side surfaces of the trenches is of the N type in the embodiments, but may be of a P type with the conductivity types of the respective regions being reversed.

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Abstract

A trench semiconductor device is provided which ensures a reduced turn-on time. The semiconductor device (1) includes: a first epitaxial layer provided on a semiconductor substrate; a second epitaxial layer provided in contact with an upper surface of the first epitaxial layer and having a lower impurity concentration than the first epitaxial layer; a plurality of trenches provided in the second epitaxial layer as extending downward from an upper surface of the second epitaxial layer; a gate electrode embedded in each of the trenches; a source region extending downward from the upper surface of the second epitaxial layer along each of opposite side surfaces of the trench; a base region extending downward from a lower surface of the source region along each of the opposite side surfaces of the trench; and a base high concentration region provided adjacent the source region and the base region in spaced relation from the trench as extending downward from the upper surface of the second epitaxial layer to a greater depth than the base region, and having the same conductivity type as the base region and a higher impurity concentration than the base region.

Description

TECHNICAL FIELD
The present invention relates to a semiconductor device and, particularly, to a semiconductor device including a MOSFET configured along side surfaces of trenches.
BACKGROUND ART
In recent years, there has been an increasing demand for a semiconductor device including a MOSFET configured along side surfaces of trenches (hereinafter referred to as “trench semiconductor device”), because this semiconductor device has a lower ON resistance than a semiconductor device including a MOSFET (planar DMOSFET (double diffused MOSFET)) configured along an upper surface of an epitaxial layer.
A conventional trench semiconductor device is shown in FIG. 4. The semiconductor device 101 includes an N− type epitaxial layer 111 provided on an upper surface of an N type semiconductor substrate 110. A plurality of trenches (grooves) 120 are provided in the epitaxial layer 111 as extending downward from an upper surface of the epitaxial layer 111. A MOSFET is configured along opposite side surfaces of the trenches 120.
That is, a gate electrode 121 is embedded in each of the trenches, and an N+ type source region 113 and a P− type base region 114 are arranged in this order toward a lower side along each of the opposite side surfaces of the trenches 120. A portion of the epitaxial layer 111 below the base region 114 serves as an N− type drain region 115. A base high concentration region 116 is provided adjacent the source region 113 and the base region 114 in spaced relation from the trench 120 as extending downward from the upper surface of the epitaxial layer 111. The base high concentration region 116 has the same conductivity type as the base region 114 and a higher impurity concentration than the base region 114, and is shallower than the base region 114. The base high concentration region 116 has an ohmic contact with a source electrode 125 to be described later, and reduces the resistance component of the base region 114.
A gate insulating film 122 of a thin silicon oxide film is provided between the trench 120 and the gate electrode 121. The gate insulating film 122 extends onto the upper surface of the epitaxial layer 111. Further, an interlayer insulating film 123 is provided on the gate electrode and the gate insulating film 22 as partly covering the upper surface of the epitaxial layer 111. The gate insulating film 122 and the interlayer insulating film 123 each have an etched-off portion serving as a contact hole 124 on a part of the source region 113 and an upper surface of the base high concentration region 116. A metal layer is provided as the source electrode 125 to provide electrical contacts to the source region 113 and the base high concentration region 116 through the contact hole 124.
Where the semiconductor device 101 is in an OFF state, depletion layers 140 and 141 are formed as respectively spreading from lower surfaces of the base region 114 and the trench 120 into the drain region 115 in the epitaxial layer 111 as shown in FIG. 5. The depletion layer 140 spreading from the base region 114 has a relatively great width, while the depletion layer 141 spreading from the lower surface of the trench 120 has a relatively small width. A gate-drain capacitance CGD which is a capacitance between the gate electrode 121 and the drain region 115 is generally equal to a capacitance provided by serially coupling the capacitance of the gate insulating film 122 with the capacitance of the depletion layer 141 formed below the lower surface of the trench 120. The value of the capacitance of the depletion layer 141 is inversely proportional to the width of the depletion layer 141. Therefore, the depletion layer 141, if having a smaller width, has a greater capacitance value, resulting in a greater gate-drain capacitance CGD. Conversely, the depletion layer 141, if having a greater width, has a smaller capacitance value, resulting in a smaller gate-drain resistance CGD.
  • Patent Document 1: Japanese Unexamined Patent Publication No. 8-250731
DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
Meanwhile, in Japanese Patent Application No. 2005-115952 filed in Japanese Patent Office, the inventor of the present invention previously proposes a semiconductor device having a planar DMOSFET which ensures a reduced turn-on time to achieve a higher speed switching capability. According to the previous patent application, the gate-drain capacitance CGD can be reduced by controlling the orientation and the width of a depletion layer in an OFF state. As a result, the turn-on time is reduced.
The inventor of the present invention has come up with an idea that, if the art of the previous patent application is modified to be applied to a trench semiconductor device, it is possible to achieve a further higher speed switching capability with a reduced turn-on time and a lower ON resistance, and accomplished the present invention.
In view of the foregoing, it is an object of the present invention to provide a trench semiconductor device which ensures a reduced turn-on time.
Means for Solving the Problems
A semiconductor device according to the present invention includes: a first epitaxial layer provided on a semiconductor substrate; a second epitaxial layer provided in contact with an upper surface of the first epitaxial layer and having a lower impurity concentration than the first epitaxial layer; a plurality of trenches provided in the second epitaxial layer as extending downward from an upper surface of the second epitaxial layer; a gate electrode embedded in each of the trenches; a source region extending downward from the upper surface of the second epitaxial layer along each of opposite side surfaces of the trench; a base region extending downward from a lower surface of the source region along each of the opposite side surfaces of the trench; and a base high concentration region provided adjacent the source region and the base region in spaced relation from the trench as extending downward from the upper surface of the second epitaxial layer to a greater depth than the base region, and having the same conductivity type as the base region and a higher impurity concentration than the base region.
An interlayer insulating film may be provided on the gate electrode as covering a part of the upper surface of the second epitaxial layer, and a source electrode may be provided in contact with the interlayer insulating film, a part of the source region and an upper surface of the base high concentration region.
Alternatively, a buried insulating film may be provided on the gate electrode to fill the trench to the vicinity of an opening edge of the trench, and a source electrode may be provided in contact with the buried insulating film, the source region and an upper surface of the base high concentration region.
According to the inventive semiconductor device, depletion layers spreading from base high concentration regions disposed on the opposite sides of the trench are merged with each other at a position below the trench when the semiconductor device is in an OFF state. As a result, a gate-drain capacitance CGD is reduced, thereby reducing a turn-on time.
The foregoing and other objects, features and effects of the present invention will become more apparent from the following description of the preferred embodiments with reference to the attached drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a sectional view of a semiconductor device according to a preferred embodiment of the present invention.
FIG. 2 is a sectional view illustrating an OFF state of the semiconductor device.
FIG. 3 is a sectional view of a semiconductor device according to another preferred embodiment of the present invention.
FIG. 4 is a sectional view of a conventional semiconductor device.
FIG. 5 is a sectional view illustrating an OFF state of the conventional semiconductor device.
 BEST MODE FOR CARRYING OUT THE INVENTION
The best mode for carrying out the invention will hereinafter be described with reference to the drawings.
FIG. 1 is a sectional view of a semiconductor device according to a preferred embodiment of the present invention. The semiconductor device 1 includes an N− type first epitaxial layer 11 provided on an N type semiconductor substrate 10 (for example, having an impurity concentration of about 1019/cm3) and having the same conductivity type as the semiconductor substrate 10 and a lower impurity concentration (e.g., an impurity concentration of about 1016/cm3) than the semiconductor substrate 10, and an N−− type second epitaxial layer 12 provided in contact with an upper surface of the first epitaxial layer 11 and having the same conductivity type as the first epitaxial layer 11 and a lower impurity concentration (e.g., an impurity concentration of about 1015/cm3) than the first epitaxial layer 11. That is, the semiconductor device 101 described in BACKGROUND ART is of a single epitaxial layer structure including the epitaxial layer 111, but the semiconductor device 1 is of a double epitaxial layer structure obtained by forming the second epitaxial layer 12 on the upper surface of the first epitaxial layer 11 which corresponds to the epitaxial layer 111.
A plurality of trenches 20 are provided in the second epitaxial layer 12 as extending downward from an upper surface of the second epitaxial layer 12. A MOSFET is configured along opposite side surfaces of the trenches 20. That is, a gate electrode 21 is embedded in each of the trenches 20. Provided along each of the opposite side surfaces of the trench are an N+ type source region 13 extending downward from the upper surface of the second epitaxial layer 12 and a P− type base region 14 extending downward from a lower surface of the source region 13. A portion of the epitaxial layer 12 below the base region 14 and a base high concentration region 16 to be described later serves as an N−− type drain region 15. The base high concentration region 16 is disposed adjacent the source region 13 and the base region 14 in spaced relation from the trench 20 as extending downward from the upper surface of the second epitaxial layer 12. The base high concentration region 16 has the same conductivity type as the base region 14 and a higher impurity concentration than the base region 14, and is formed as extending to a greater depth than the base region 14, and to have a depth that is smaller than a depth of the trenches 20. The base high concentration region 16 has an ohmic contact with a source electrode 25 to be described later, and reduces the resistance component of the base region 14. As will be described later, the base high concentration region 16 has an important function for reducing a gate-drain capacitance CGD when the semiconductor device 1 is in an OFF state.
Thus, the source region 13, the base region 14 and the base high concentration region 16 are provided in a portion of the second epitaxial layer 12, and the rest of the second epitaxial layer 12 serves as the drain region 15. The first epitaxial layer 11 provided below the second epitaxial layer 12 in contact with the drain region 15 also serves as a part of the drain region. As will be described later, the second epitaxial layer 12 (drain region 15) has a low impurity concentration such that, when the semiconductor device is in the OFF state, depletion layers respectively spreading from base high concentration regions 16 disposed on opposite sides of each trench 20 are merged with each other at a position below the trench 20.
As in the semiconductor device 101 described in BACKGROUND ART, a gate insulating film 22 of a thin silicon oxide film is provided between the trench 20 and the gate electrode 21. The gate insulating film 22 extends onto the upper surface of the second epitaxial layer 12. Further, an interlayer insulating film 23 is provided over the gate electrode 21 and the gate insulating film 22 as covering a part of the upper surface of the second epitaxial layer 12. The gate insulating film 22 and the interlayer insulating film 23 each have an etched-off portion serving as a contact hole 24 on a part of the source region 13 and an upper surface of the base high concentration region 16. A metal layer is provided as a source electrode 25 to provide electrical contacts to the source region 13 and the base high concentration region 16 through the contact hole 24. Therefore, the source electrode 25 (mechanically) contacts the interlayer insulating film 23, the part of the source region 13 and the upper surface of the base high concentration region 16.
Although a production method for the semiconductor device 1 will not be described, features of the production method are that the first epitaxial layer 11 is formed on the semiconductor substrate 10 by an epitaxial technique, that the second epitaxial layer 12 is formed on the first epitaxial layer 11 by an epitaxial technique, and that the base high concentration region 16 is formed as extending to a greater depth than the base region 41 by an impurity diffusion technique or an impurity implantation technique.
Next, ON and OFF states of the semiconductor device 1 will be described. The semiconductor device 1 is in the ON state when a gate-source voltage VGS which is a voltage between the gate electrodes 21 and the source electrode 25 is not less than a threshold, and is in the OFF state when the gate-source voltage VGS is less than the threshold. In the ON state, channel layers are formed in the base regions 14, so that ON electric current flows from the semiconductor substrate 10 to the source electrode 25 through the first epitaxial layer 11, the drain region 15, the base regions 14 and the source regions 13. As a result, a drain-source voltage VDS which is a voltage between the semiconductor substrate 10 and the source electrode 25 is generally reduced.
In the OFF state, on the other hand, the drain-source voltage VDS is higher (e.g., 20V), so that the depletion layers 40 occur as shown in FIG. 2. It should be herein noted that the base high concentration region 16 is formed as having a greater depth and a higher impurity concentration than the base region 14 and, therefore, a depletion layer 40 spreading depthwise and laterally from the base high concentration region 16 fills the drain region 15 having a very low impurity concentration to extend into an inner portion of the first epitaxial layer 11. That is, the depletion layers 40 spreading from the base high concentration regions 16 disposed on the opposite sides of each trench 20 are merged with each other below the trench 20. Depletion layers spreading from lower surfaces of the base region 14 and the trench 20 are completely contained in and integrated with the depletion layers 40 widely spreading from the base high concentration regions 16.
Therefore, a portion of the depletion layer 40 present below the lower surface of the trench 20 has a greater width, so that the depletion layer portion has a smaller capacitance value. Since the gate-drain capacitance CGD is equal to a capacitance obtained by serially coupling the capacitance of the gate insulating film 22 and the capacitance of the depletion layer portion formed below the lower surface of the trench 20 as described above, the gate-drain capacitance CGD is reduced. As a result, the semiconductor device 1 has a reduced turn-on time, thereby achieving higher speed switching.
In this case, as a distance from the lower surface of the trench 20 to the upper surface of the first epitaxial layer 11 increases, the width of the depletion layer portion present below the lower surface of the trench 20 is increased and, therefore, the gate-drain capacitance CGD is reduced. However, it should be noted that the drain region 15 in the second epitaxial layer 12 has a higher resistivity. Therefore, if the distance from the lower surface of the trench 20 to the upper surface of the first epitaxial layer 11 is increased, the semiconductor device 1 is liable to have an increased ON resistance in the ON state. Therefore, it is necessary to determine the distance from the lower surface of the trench 20 to the upper surface of the first epitaxial layer 11 so that the resulting ON resistance is within a permissible range.
Next, a semiconductor device according to another preferred embodiment of the present invention will be described. FIG. 3 is a sectional view of the semiconductor device 2. Like the semiconductor device 1, the semiconductor device 2 includes a semiconductor substrate 10, a first epitaxial layer 11 and a second epitaxial layer 12. Source regions 13, base regions 14, base high concentration regions 16 and a drain region 15 are provided in the second epitaxial layer 12. Gate electrodes 21 are respectively embedded in trenches 20 provided in the second epitaxial layer 12. Further, buried insulating films 26 are respectively provided on the gate electrodes 21 to fill the trenches to the vicinities of opening edges of the trenches 20 for isolation between the gate electrodes 21 and the source electrodes 25. A source electrode 25 is provided over and in contact with upper surfaces of the buried insulating films 26, the source regions 13 and the base high concentration regions 16.
Unlike the interlayer insulating film 23 of the semiconductor device 1, the buried insulating films 26 of the semiconductor device 2 are provided at a level not higher than the upper surface of the second epitaxial layer 12. Therefore, there is no need to provide contact holes for electrically contacting the source electrode 25 to the source regions 13 and the base high concentration regions 16. As a result, microminiaturization can be achieved to locate the base high concentration regions 16 closer to the trenches 20. Therefore, even if the impurity concentration of the second epitaxial layer 12 is higher than in the semiconductor device 1, depletion layers 40 spreading from the base high concentration regions 16 disposed on opposite sides of each trench 20 are merged with each other at a position below the trench 20. Thus, the drain region 15 in the second epitaxial layer 12 is permitted to have a relatively low resistivity, thereby suppressing an increase in ON resistance.
The present invention is not limited to the embodiments described above, but any of various design modifications may be made within the purview defined by the claims. For example, the MOSFET configured along the side surfaces of the trenches is of the N type in the embodiments, but may be of a P type with the conductivity types of the respective regions being reversed.
While the embodiments of the present invention have been described in detail, it should be understood that these embodiments are merely illustrative of the technical principles of the present invention but not limitative of the invention. The spirit and scope of the present invention are to be limited only by the appended claims.
This application corresponds to Japanese Patent Application No. 2005-173243 filed in the Japanese Patent Office on Jun. 14, 2005, the disclosure of which is incorporated herein by reference.

Claims (3)

1. A semiconductor device, comprising:
a first epitaxial layer provided on a semiconductor substrate;
a second epitaxial layer provided in contact with an upper surface of the first epitaxial layer and having a lower impurity concentration than the first epitaxial layer;
a plurality of trenches provided in the second epitaxial layer as extending downward from an upper surface of the second epitaxial layer;
a gate electrode embedded in each of the trenches;
a source region extending downward from the upper surface of the second epitaxial layer along each of opposite side surfaces of the trench;
a base region extending downward from a lower surface of the source region along each of the opposite side surfaces of the trench; and
a base high concentration region provided adjacent the source region and the base region in spaced relation from the trench as extending downward from the upper surface of the second epitaxial layer to a depth that is greater than a depth of the base region and is smaller than a depth of the trenches, and having the same conductivity type as the base region and a higher impurity concentration than the base region.
2. The semiconductor device according to claim 1,
wherein an interlayer insulating film is provided on the gate electrode as covering a part of the upper surface of the second epitaxial layer,
wherein a source electrode is provided in contact with the interlayer insulating film, a part of the source region and an upper surface of the base high concentration region.
3. The semiconductor device according to claim 1,
wherein a buried insulating film is provided on the gate electrode to fill the trench to the vicinity of an opening edge of the trench,
wherein a source electrode is provided in contact with the buried insulating film, the source region and an upper surface of the base high concentration region.
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US20090302379A1 (en) 2009-12-10
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JP5008046B2 (en) 2012-08-22
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EP1909330A4 (en) 2009-12-09
WO2006134810A1 (en) 2006-12-21

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