US7893728B2 - Voltage-current converter and voltage controlled oscillator - Google Patents

Voltage-current converter and voltage controlled oscillator Download PDF

Info

Publication number
US7893728B2
US7893728B2 US12/289,758 US28975808A US7893728B2 US 7893728 B2 US7893728 B2 US 7893728B2 US 28975808 A US28975808 A US 28975808A US 7893728 B2 US7893728 B2 US 7893728B2
Authority
US
United States
Prior art keywords
current
voltage
nmos
input
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US12/289,758
Other versions
US20090140776A1 (en
Inventor
Kazunosuke Hirai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Assigned to NEC ELECTRONICS CORPORATION reassignment NEC ELECTRONICS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HIRAI, KAZUNOSUKE
Publication of US20090140776A1 publication Critical patent/US20090140776A1/en
Assigned to RENESAS ELECTRONICS CORPORATION reassignment RENESAS ELECTRONICS CORPORATION CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: NEC ELECTRONICS CORPORATION
Application granted granted Critical
Publication of US7893728B2 publication Critical patent/US7893728B2/en
Assigned to RENESAS ELECTRONICS CORPORATION reassignment RENESAS ELECTRONICS CORPORATION CHANGE OF ADDRESS Assignors: RENESAS ELECTRONICS CORPORATION
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H03K3/0315—Ring oscillators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00026—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00195—Layout of the delay element using FET's
    • H03K2005/00202—Layout of the delay element using FET's using current mirrors

Definitions

  • the present invention relates to a voltage-current converter and a voltage controlled oscillator.
  • the threshold value voltage of a transistor has been decreasing along with the high-speed operation and reduced voltage of LSI. Along with this, a leak current flowing between a source and a drain even when the transistor is in an off state, which is off leak, cannot be ignored. The off-leak current tends to be increased when the threshold value voltage of the transistor is low and the temperature is high. The off-leak current greatly influences on each characteristic especially in an analog design; therefore, any proper countermeasure should be taken in a low-voltage operation area.
  • the off-leak current cancel circuit includes cancel portions 110 and 120 .
  • the cancel portions 110 and 120 cancel off-leak current of an input circuit protecting PMOS 102 and NMOS 103 .
  • the cancel portions 110 and 120 are formed on a semiconductor substrate of the PMOS 102 and NMOS 103 .
  • the PMOS 102 is connected between the input terminal 101 and a power supply potential VDD.
  • the NMOS 103 is connected between the input terminal 101 and a ground potential GND.
  • the cancel portion 110 cancels off-leak current of the PMOS 102 and includes a PMOS 111 and NMOS 112 , 113 , 114 .
  • the PMOS 111 has a gate length identical to the PMOS 102 and a gate width of 1/n of the gate width of the PMOS 102 .
  • the PMOS 111 has a source and a gate connected to the power supply potential VDD and a drain connected to a node 131 . That is, the PMOS 111 is diode-connected in the reverse direction like the PMOS 102 and configured so that 1/n of the off-leak current flowing in the PMOS 102 flows.
  • the node 131 is connected to the drain and the gate of the NMOS 112 whose source is connected to the ground potential GND.
  • the node 131 is connected to the gate of the NMOS 113 whose drain and source are connected to the input terminal 101 and the ground terminal GND, respectively.
  • the NMOS 113 has a gate length identical to the NMOS 112 , and a gate width which is n times as large as the gate width of the NMOS 112 . That is, the NMOS 112 and 113 constitute a current mirror circuit and the current n times as large as the current flowing in the NMOS 112 flows in the NMOS 113 .
  • the NMOS 114 has a drain connected to the node 131 .
  • the NMOS 114 has a source connected to the ground potential GND and a gate connected to the power supply potential VDD. Accordingly, the NMOS 114 is always in on state.
  • the NMOS 114 has a gate length and gate width formed so that the ON resistance of the NMOS 114 exhibits quite a high resistance value. Accordingly, the NMOS 114 makes the node 131 the ground potential GND for stability of the operation when almost no off-leak current is present in the PMOS 111 .
  • the cancel portion 120 cancels off-leak current of the NMOS 103 and includes an NMOS 121 and PMOS 122 , 123 , 124 .
  • the NMOS 121 has a gate length identical to the NMOS 103 and a gate width of 1/n of the gate width of the NMOS 103 .
  • the NMOS 121 has a source and a gate connected to the ground potential GND and a drain connected to a node 132 . That is, the NMOS 121 is diode-connected in the reverse direction like the NMOS 103 and configured so that 1/n of the off-leak current flowing in the NMOS 103 flows.
  • the node 132 is connected to the drain and the gate of the PMOS 122 whose source is connected to the power supply potential VDD.
  • the node 132 is connected to the gate of the PMOS 123 whose drain and source are connected to the input terminal 101 and to the power supply potential VDD, respectively.
  • the PMOS 123 has a gate length identical to the PMOS 122 , and a gate width which is n times as large as the gate width of the PMOS 112 . That is, the PMOS 122 and 123 constitute a current mirror circuit and the current n times as large as the current flowing in the PMOS 122 flows in the PMOS 123 .
  • the PMOS 124 has a drain connected to the node 132 .
  • the PMOS 124 has a source connected to the power supply potential VDD and a gate connected to the ground potential GND. Accordingly, the PMOS 124 is always in on state.
  • the PMOS 124 has a gate length and gate width formed so that the ON resistance of the PMOS 124 exhibits quite a high resistance value. Accordingly, the PMOS 124 makes the node 132 the power supply potential VDD for stability of the operation when almost no off-leak current is present in the NMOS 121 .
  • the NMOS 114 of the cancel portion 110 is in an ON state and accordingly, the node 131 is almost ground potential GND and the NMOS 112 and 113 are in an OFF state.
  • the PMOS 124 of the cancel portion 120 is in an ON state and accordingly, the node 132 becomes almost power supply potential VDD and PMOS 122 and 123 become OFF.
  • the ambient temperature has increased and off-leak current flows in the PMOS 102 .
  • the PMOS 102 and the PMOS 111 in the cancel portion 110 are formed on the same semiconductor substrate and have an identical gate length. Accordingly, off-leak current also flows in this PMOS 111 .
  • the gate length is identical, the off-leak current flowing is proportional to the gate width and accordingly, the off-leak current flowing in the PMOS 111 becomes 1/n of the PMOS 102 .
  • the off-leak current flowing in the PMOS 111 flows into the node 131 .
  • the node 131 is connected to the NMOS 112 and 114 but since the NMOS 114 has quite a high resistance, almost no current flows in the NMOS 114 .
  • the NMOS 112 current almost identical to the PMOS 111 flows.
  • the NMOS 112 is connected to the NMOS 113 constituting a current mirror circuit of the current ratio of n multiples.
  • current n times as large as the PMOS 111 flows in the ground potential GND through the NMOS 113 .
  • the current of the PMOS 111 becomes 1/n of the current of the PMOS 102 ; therefore, the current identical to the current flowing in the PMOS 102 flows in the NMOS 113 .
  • the off-leak current flowing in the PMOS 102 all flows into the ground potential GND via the NMOS 113 and no off-leak current flows into the signal source connected to the input terminal 101 .
  • the off-leak current flowing in the NMOS 103 is detected by the NMOS 121 for monitoring of the cancel portion 120 and supplied from the power supply potential VDD via the PMOS 123 to the NMOS 103 . Accordingly, no off-leak current flows to the signal source connected to the input terminal 101 .
  • the circuit shown in FIG. 4 is a circuit for canceling the off-leak current of the input circuit protecting PMOS 102 and NMOS 103 .
  • the off-leak current flowing in the NMOS 103 is detected by the NMOS 121 for monitoring of the cancel portion 120 .
  • the current is supplied from the power supply potential VDD via the PMOS 123 to the NMOS 103 to cancel the off-leak current.
  • FIG. 5 is a circuit diagram showing a configuration of the voltage-current converter.
  • the off-leak current of the NMOS 4 is cancelled by a second current generating circuit 12 .
  • the second current generating circuit 12 has a function of decreasing the off-leak current.
  • the off-leak current greatly depends on the threshold value voltage and the temperature. For example, the off-leak current especially increases when the threshold value voltage of the transistor is low and the temperature is high. Therefore, the off-leak current cannot be ignored depending on the diffusion state in the LSI and the operating temperature of the LSI or the like. Therefore, it becomes difficult to generate the current according to the input voltage. As such, the off-leak current degrades the accuracy of the output current, which degrades the characteristic of the analog circuit.
  • the gate is connected to the input terminal 1
  • the source is connected to the resistance element 3
  • the bulk is connected to the ground GND. Therefore, there is generated a difference potential between the source and the bulk, whereby the threshold value is made somewhat high due to the back bias effect.
  • the off-leak current flowing in the NMOS 4 depends on the threshold value and the voltage between the gate and the source.
  • the off-leak current flowing in the NMOS 4 of the voltage-current converter 11 is different from the current amount generated in the NMOS 8 in the second current generating circuit 12 . Therefore, the current value almost the same as the current value flowing in the NMOS 4 cannot be generated in the NMOS 8 . Accordingly, it is not possible to cancel the off-leak current flowing in the NMOS 4 without fail.
  • the related off-leak current cancel circuit it is not possible to accurately reproduce the off-leak current generated in the circuit such as the voltage-current converter in which a source is connected to a resistor. As such, according to the related voltage-current converter, the output current accuracy with respect to the input voltage decreases due to the off-leak current.
  • a first exemplary aspect of an embodiment of the present invention is a voltage-current converter converting an input voltage input to an input terminal to a current to output the current, the voltage-current converter including a first current generating circuit including an input transistor having a gate connected to the input terminal and generating an output current according to a current flowing in the input transistor, and a second current generating circuit including a transistor having a gate having a potential different from potential of a source and a drain, the second current generating circuit generating a superimposed current according to the current flowing in the transistor to supply the superimposed current to the input transistor.
  • the present invention it is possible to cancel the off-leak current flowing in the input transistor without fail; therefore, the output current accuracy with respect to the input voltage can be improved.
  • FIG. 1 is a circuit diagram showing a configuration of a voltage-current converter according to an exemplary embodiment of the present invention
  • FIG. 2 is a circuit diagram showing a configuration of a voltage controlled oscillator according to the exemplary embodiment of the present invention
  • FIG. 3 is a diagram showing an oscillation frequency of the voltage controlled oscillator
  • FIG. 4 is a circuit diagram showing a configuration of an off-leak current cancel circuit according to a related art
  • FIG. 5 is a circuit diagram showing a configuration of a voltage-current converter employing the off-leak current cancel circuit of FIG. 4 ;
  • FIG. 6 is a circuit diagram showing a configuration of a voltage controlled oscillator which does not cancel the off-leak current.
  • FIG. 1 is a circuit diagram showing a configuration of the voltage-current converter.
  • the voltage-current converter includes a first current generating circuit 11 and a second current generating circuit 12 .
  • the first current generating circuit 11 includes an output terminal 2 , a resistance element 3 , an NMOS (n channel type MOS transistor) 4 , a PMOS (p channel type MOS transistor) 5 , and a PMOS 6 .
  • the NMOS 4 is an input transistor, and a gate of the NMOS 4 is connected to an input terminal 1 . Accordingly, an input potential is supplied to the gate of the NMOS 4 .
  • a drain of the NMOS 4 is connected to a node 21 .
  • a source of the NMOS 4 is connected to a ground potential GND through the resistance element 3 .
  • one end of the resistance element 3 is connected to the source of the NMOS 4 , and the other end of the resistance element 3 is connected to the ground potential GND.
  • a node 20 is between the resistance element 3 and the source of the NMOS 4 .
  • a drain and a gate of the PMOS 5 are connected to the node 21 .
  • a source of the PMOS 5 is connected to a power supply potential VDD.
  • the PMOS 5 is diode-connected.
  • a gate of the PMOS 6 is connected to the node 21 , and a source of the PMOS 6 is connected to the power supply potential VDD.
  • a drain of the PMOS 6 is connected to the output terminal 2 .
  • the PMOS 6 has a gate length same to that of the PMOS 5 , and has a gate width n (or 1/n) times as large as the gate width of the PMOS 6 . Accordingly, the PMOS 5 and the PMOS 6 constitute a current mirror circuit of the current ratio of n multiples.
  • the current flows in the ground potential GND side according to the potential supplied to the input terminal 1 . Therefore, the current flows from the power supply potential VDD to the PMOS 5 , the NMOS 4 , and the resistance element 3 .
  • the PMOS 5 and the PMOS 6 constitute a current mirror circuit. Therefore, the current according to the current flowing in the NMOS 4 flows into the output terminal 2 from the power supply potential VDD through the PMOS 6 .
  • the input voltage input to the input terminal 1 is converted into the current and the current is output from the output terminal 2 .
  • the output current according to the input voltage is output from the output terminal 2 .
  • the second current generating circuit 12 is a constant current circuit supplying the current to the NMOS 4 which is the input transistor.
  • the second current generating circuit 12 outputs a superimposed current superimposed on the active current of the NMOS 4 .
  • the active current of the NMOS 4 is a current flowing from the power supply potential VDD to the NMOS through the PMOS 5 . Therefore, the active current is the current flowing in the NMOS 4 which does not include the current flowing from the second current generating circuit 12 . Accordingly, the current actually flowing in the NMOS 4 in the voltage-current converter has the value which is obtained by adding the superimposed current to the active current of the NMOS 4 .
  • the superimposed current has the current value identical to the active current flowing in the NMOS 4 in a fixed input voltage.
  • the second current generating circuit 12 includes a resistance element 7 , an NMOS 8 , a PMOS 9 , and a PMOS 10 .
  • the NMOS 8 has a gate length and a gate width identical to those of the NMOS 4 .
  • a gate of the NMOS 8 is the ground potential GND.
  • a drain of the NMOS 8 is connected to a node 24 .
  • a source of the NMOS 8 is connected to the ground potential GND through the resistance element 7 .
  • one end of the resistance element 7 is connected to the source of the NMOS 8 , and the other end of the resistance element 7 is connected to the ground potential GND.
  • a node 23 is between the resistance element 7 and the source of the NMOS 8 .
  • the resistance element 7 has the same resistance value as that of the resistance element 3 . In summary, the resistance element 7 and the resistance element 3 have the same characteristics.
  • the node 24 is connected to a drain and a gate of the PMOS 9 whose source is connected to the power supply potential VDD.
  • a gate of the PMOS 10 is connected to the node 24 .
  • a source of the PMOS 10 is connected to the power supply potential VDD.
  • a drain of the PMOS 10 is connected to the node 21 .
  • the PMOS 9 and the PMOS 10 constitute a current mirror circuit of the current ratio of 1 multiple. For example, when the PMOS 9 and the PMOS 10 are formed to have the same gate width and the same gate length, the current mirror circuit of the current ratio of 1 multiple is formed.
  • the second current generating circuit 12 and the first current generating circuit 11 are formed on the same semiconductor substrate. As such, the second current generating circuit 12 and the first current generating circuit 11 almost have the same circuit arrangement.
  • the gate of the input terminal 1 is the ground potential GND.
  • the current flows in the NMOS 4 even when the input voltage is the ground potential GND.
  • the off-leak current is generated in the NMOS 4 .
  • the NMOS 4 and the second current generating circuit 12 are formed on the same semiconductor substrate.
  • the NMOS 8 has the same gate length and the same gate width. Therefore, current identical to the current flowing in the NMOS 4 flows in the NMOS 8 , which means the off-leak current of the NMOS 8 and the off-leak current of the NMOS 4 are equal to each other.
  • the NMOS 8 is connected to the PMOS 9 , where the current identical to the current flowing in the NMOS 8 flows.
  • the PMOS 10 is connected to the PMOS 9 constituting a current mirror circuit of the current ratio of 1 multiple. Accordingly, current identical to the current flowing in the NMOS 8 flows in the node 21 through the PMOS 10 .
  • current identical to the active current of the NMOS 4 is output from the second current generating circuit 12 .
  • the second current generating circuit 12 is formed to have the configuration substantially identical to the configuration of the first current generating circuit 11 in order to output such a superimposed current.
  • the ground potential GND is connected to the gate of the NMOS 8 corresponding to the NMOS 4 which is the input transistor.
  • the superimposed current is superimposed on the active current of the NMOS 4 which is the input transistor.
  • the output current accuracy in reduced voltage input can be corrected. As such, it is possible to obtain the output current depending on the threshold value voltage of the NMOS 4 and the input voltage.
  • the NMOS 8 and the NMOS 4 have the same gate length and the same gate width, and both of them are formed on the same semiconductor substrate. Accordingly, the NMOS 8 and the NMOS 4 substantially have the same property. Accordingly, the output current can be corrected with high accuracy.
  • the source of the NMOS 8 is connected to the ground potential GND through the resistance element 7 . Accordingly, when the current flows between the source and the drain of the NMOS 8 , the gate of the NMOS 8 has the different potential from those of the source and the drain. More specifically, although the gate of the NMOS 8 is connected to the ground potential GND, the source of the NMOS 8 has the different potential from the ground potential GND due to the resistance element 7 . Accordingly, when current flows in the NMOS 8 , the voltage between the gate and the source fluctuates, which produces a potential difference between the source and the bulk. Therefore, the threshold value voltage fluctuates due to the voltage fluctuation between the gate and the source and the back gate effect.
  • the threshold value voltage of the NMOS 8 becomes somewhat higher. Since the resistance element 3 and the resistance element 7 have the same resistance value, the fluctuation of the threshold value of the NMOS 4 and the NMOS 8 is almost equal to each other. Accordingly, the current almost identical to the active current of the NMOS 4 flows in the NMOS 8 .
  • the voltage decreases when the current flows from the NMOS 4 to the resistance element 3 .
  • the source voltage increases and the voltage between the gate and the source fluctuates due to this voltage decrease.
  • the source voltage of the NMOS 4 increases from the ground potential GND by the voltage amount corresponding to the current value flowing from the NMOS 4 to the resistance element 3 and the resistance value of the resistance element 3 .
  • the potential of the node 20 increases from the ground potential GND.
  • the resistance element 7 is connected to the NMOS 8 of the second current generating circuit 12 as well. The voltage decreases due to the resistance element 7 .
  • the source voltage of the NMOS 8 increases as is the same way as the NMOS 4 .
  • the voltage between the gate and the source of the NMOS 8 fluctuates as in the same way as the voltage between the gate and the source of the NMOS 4 .
  • the threshold value voltage of the NMOS 8 fluctuates as in the same way as the threshold value voltage of the NMOS 4 . It is possible to make the off-leak current of the NMOS 8 equal to the off-leak current of the NMOS 4 .
  • the superimposed current also changes in accordance with the off-leak current of the NMOS 4 , and the off-leak current of the NMOS 4 and the superimposed current become equal to each other. Accordingly, the off-leak current of the NMOS 4 can be canceled by the superimposed current. It is possible to correct the output current accuracy in the low voltage input, and to realize the voltage-current converter which enables simple current control. For example, the output current can be corrected even when the ambient temperature is changed.
  • the superimposed current for canceling the off-leak current of the NMOS 4 is output from the second current generating circuit 12 . Accordingly, the superimposed current has a value according to the off-leak current of the NMOS 8 . Furthermore, since the NMOS 4 and the NMOS 8 have the same property, the off-leak current becomes equal to each other. As such, the superimposed current changes according to the off-leak current of the NMOS 4 . This superimposed current is superimposed on the active current of the NMOS 4 . Accordingly, it is possible to correct the output voltage with higher accuracy than the voltage-current converter as shown in FIG.
  • the gate and the source of the NMOS 8 are directly connected to the ground potential GND in the voltage-current converter shown in FIG. 5 . Accordingly, in the voltage-current converter shown in FIG. 5 , the threshold value voltage does not change due to the voltage fluctuation between the gate and the source or the back gate effect. Therefore, it is not possible to cancel the off-leak current without fail in the voltage-current converter shown in FIG. 5 , which means that the output current accuracy cannot be improved.
  • the gate of the NMOS 8 is connected to the ground potential GND; therefore, the superimposed current does not change according to the input voltage. Therefore, the second current generating circuit 12 outputs the superimposed current having the current value which does not relate to the input potential of the input terminal 1 . Further, the gate and the source of the NMOS 8 have the different potential with each other. As such, the off-leak current can be canceled without fail even with the voltage-current converter in which the resistance element 3 is connected to the source of the NMOS 4 which is the input transistor.
  • the second current generating circuit 12 is the constant current circuit generating the superimposed current having the current value equal to the current value flowing in the NMOS 4 except the superimposed current when the input level of the NMOS 4 is in the ground potential GND. Therefore, the active current of the NMOS 4 becomes equal to the superimposed current when the input level of the NMOS 4 is in the ground potential GND. Accordingly, it is possible to cancel the off-leak current without fail.
  • the off-leak current of the NMOS 4 is correctly reproduced in the second current generating circuit 12 to be output to the NMOS 4 as the superimposed current. Accordingly, the output current accuracy with respect to the input voltage can be improved.
  • FIG. 2 is a circuit diagram showing a configuration of a voltage controlled oscillator (VCO) including the voltage-current converter shown in FIG. 1 .
  • the VCO includes a first current generating circuit 11 , a second current generating circuit 12 , a third current generating circuit 13 , and an oscillator 14 .
  • the VCO has a circuit configuration in which the third current generating circuit 13 and the oscillator 14 are added to the voltage-current converter shown in FIG. 1 . Since the first current generating circuit 11 and the second current generating circuit 12 have the similar circuit configuration as the circuit shown in FIG.
  • the VCO is a circuit used in generating clocks or the like.
  • the first current generating circuit 11 , the second current generating circuit 12 , the third current generating circuit 13 , and the oscillator 14 are formed on the same semiconductor substrate.
  • the third current generating circuit 13 is the constant current circuit and is connected to the node 21 .
  • the third current generating circuit 13 includes an NMOS 30 , an NMOS 31 , and a current source 32 .
  • the NMOS 30 has a gate and a drain connected to the current source 32 through a node 25 .
  • a source of the NMOS 30 is connected to the ground potential GND.
  • the NMOS 31 has a gate connected to the current source 32 through the node 25 , a drain connected to the node 21 , and a source connected to the ground potential GND.
  • the NMOS 31 has a gate length identical to that of the NMOS 30 .
  • a gate width of the NMOS 31 is n times (or 1/n times) as large as the gate width of the NMOS 30 .
  • the oscillator 14 oscillates in an oscillation frequency according to the output current from the first current generating circuit 11 . Therefore, the oscillator 14 is able to generate the clock signal according to the output current from the first current generating circuit 11 . In other words, the oscillator 14 is connected to the output terminal 2 of FIG. 1 . Note that the circuit configuration of the oscillator 14 is not specifically limited.
  • the current flows in the node 21 through the NMOS 4 as the potential of the input terminal 1 increases.
  • the PMOS 5 is connected to the node 21 .
  • the PMOS 6 is connected to the PMOS 5 constituting a current mirror circuit of the current ratio of 1/n (or n) multiples. Accordingly, the output current 1/n (or n) times as large as the PMOS 5 flows in the node 22 through the PMOS 6 . Then the oscillation frequency of the oscillator 14 can be controlled by the output current.
  • the current flows in the NMOS 30 from the current source 32 through the node 25 . Accordingly, the current 1/n (or n) times as large as the NMOS 30 flows in the node 21 through the NMOS 31 . Further, the PMOS 5 is connected to the node 21 . The PMOS 6 is connected to the PMOS 5 constituting a current mirror circuit of the current ratio of 1/n (or n) multiples. Accordingly, the current 1/n (or n) times as large as the PMOS 5 flows in the node 22 through the PMOS 6 . Accordingly, the oscillation frequency of the oscillator 14 when the input terminal 1 is in the GND level is determined by the third current generating circuit 13 . When the input voltage of the input terminal 1 changes, the oscillation frequency changes.
  • FIG. 6 shows a VCO as a comparative example in order to describe the effect of the VCO according to the exemplary embodiment.
  • FIG. 6 shows a circuit configuration of the VCO which does not include a second current generating circuit 12 . Therefore, the VCO as the comparative example includes a first current generating circuit 11 , a third current generating circuit 13 , and an oscillator 14 .
  • the oscillation frequency is typically determined only by the current from the third current generating circuit 13 .
  • the off-leak current flowing in the NMOS 4 is so large that cannot be ignored, the off-leak current of the NMOS 4 is added to the current from the third current generating circuit 13 in the node 21 .
  • the PMOS 5 is connected to the node 21 .
  • the PMOS 6 is connected to the PMOS 5 .
  • the PMOS 5 and the PMOS 6 constitute a current mirror circuit of the current ratio of 1/n (or n) times.
  • the VCO shown in FIG. 2 includes a second current generating circuit 12 .
  • the second current generating circuit 12 superimposes on the NMOS 4 the superimposed current having the current value identical to the active current flowing when the input potential has a fixed value in the first current generating circuit 11 having the same structure as the related first current generating circuit 11 .
  • the gate of the NMOS 8 of the second current generating circuit 12 is connected to the ground potential GND. Therefore, the superimposed current is supplied from the second current generating circuit 12 to the input transistor NMOS 4 of the first current generating circuit 11 . Accordingly, the output current accuracy of the NMOS 4 in the low voltage input can be corrected. As a result, the oscillation frequency depending on the threshold value voltage of the NMOS 4 and the voltage of the input terminal 1 can be obtained.
  • the horizontal axis indicates the input voltage of the input terminal 1 of FIGS. 6 and 2
  • the vertical axis is what the output frequency of the oscillator 14 is normalized.
  • a shown by dashed-dotted line indicates the oscillation frequency in the related circuit, which is the circuit shown in FIG. 6 .
  • B shown by solid line indicates the oscillation frequency in the circuit of the present invention, which is the circuit shown in FIG. 2 .
  • C shown by dotted line is the expectation value, which is the value when it is assumed that there is no off-leak current flows.
  • the frequency is about twice higher than the expectation value due to the off-leak current when the input voltage is 0.1.
  • the frequency which is quite close to the expectation value can be obtained even when the input voltage is 0.1. Accordingly, the output current accuracy in the low voltage input can be corrected, which means the voltage-current converter which can easily control the current can be obtained.
  • the circuit of the present invention is effective in realizing the controlling of the oscillation frequency with high accuracy. Hence, the output accuracy with respect to the input voltage can be improved.
  • the off-leak current increases; however, the output current can be controlled with high accuracy by the above-described voltage-current converter.
  • the constant current circuit is added which superimposes on the input transistor the current value equal to the active current flowing when the input potential of the voltage-current converter has a fixed value. According to the present invention, it is possible to realize the analog circuit with high accuracy, and to realize cost reduction by shortening the development period and improving the yield.
  • the input transistor is the NMOS 4 in the above description
  • the input transistor may be PMOS as well.
  • the PMOS is used instead of using the NMOS 4 and the NMOS 8 .
  • each PMOS may be connected to the power supply potential through the resistance element having the same characteristics.
  • the MOS transistor may be connected to the power supply voltage or the ground potential GND through the resistance element.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)
  • Amplifiers (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)

Abstract

An exemplary aspect of an embodiment of the present invention is a voltage-current converter converting an input voltage input to an input terminal to a current to output the current, the voltage-current converter including a first current generating circuit including an input transistor having a gate connected to the input terminal and generating an output current according to a current flowing in the input transistor, and a second current generating circuit including a transistor having a gate having a potential different from potential of a source and a drain, the second current generating circuit generating a superimposed current according to the current flowing in the transistor to supply the superimposed current to the input transistor.

Description

BACKGROUND
1. Field of the Invention
The present invention relates to a voltage-current converter and a voltage controlled oscillator.
2. Description of Related Art
In recent years, the threshold value voltage of a transistor has been decreasing along with the high-speed operation and reduced voltage of LSI. Along with this, a leak current flowing between a source and a drain even when the transistor is in an off state, which is off leak, cannot be ignored. The off-leak current tends to be increased when the threshold value voltage of the transistor is low and the temperature is high. The off-leak current greatly influences on each characteristic especially in an analog design; therefore, any proper countermeasure should be taken in a low-voltage operation area.
An off-leak current cancel circuit for canceling such off-leak current is disclosed in Japanese Unexamined Patent Application Publication No. 2002-344251 (Kondo). The off-leak current cancel circuit disclosed in Kondo will be described with reference to FIG. 4. The off-leak current cancel circuit includes cancel portions 110 and 120. The cancel portions 110 and 120 cancel off-leak current of an input circuit protecting PMOS 102 and NMOS 103. The cancel portions 110 and 120 are formed on a semiconductor substrate of the PMOS 102 and NMOS 103. The PMOS 102 is connected between the input terminal 101 and a power supply potential VDD. The NMOS 103 is connected between the input terminal 101 and a ground potential GND.
The cancel portion 110 cancels off-leak current of the PMOS 102 and includes a PMOS 111 and NMOS 112, 113, 114. The PMOS 111 has a gate length identical to the PMOS 102 and a gate width of 1/n of the gate width of the PMOS 102. The PMOS 111 has a source and a gate connected to the power supply potential VDD and a drain connected to a node 131. That is, the PMOS 111 is diode-connected in the reverse direction like the PMOS 102 and configured so that 1/n of the off-leak current flowing in the PMOS 102 flows.
The node 131 is connected to the drain and the gate of the NMOS 112 whose source is connected to the ground potential GND. The node 131 is connected to the gate of the NMOS 113 whose drain and source are connected to the input terminal 101 and the ground terminal GND, respectively. The NMOS 113 has a gate length identical to the NMOS 112, and a gate width which is n times as large as the gate width of the NMOS 112. That is, the NMOS 112 and 113 constitute a current mirror circuit and the current n times as large as the current flowing in the NMOS 112 flows in the NMOS 113.
The NMOS 114 has a drain connected to the node 131. The NMOS 114 has a source connected to the ground potential GND and a gate connected to the power supply potential VDD. Accordingly, the NMOS 114 is always in on state. The NMOS 114 has a gate length and gate width formed so that the ON resistance of the NMOS 114 exhibits quite a high resistance value. Accordingly, the NMOS 114 makes the node 131 the ground potential GND for stability of the operation when almost no off-leak current is present in the PMOS 111.
The cancel portion 120 cancels off-leak current of the NMOS 103 and includes an NMOS 121 and PMOS 122, 123, 124. The NMOS 121 has a gate length identical to the NMOS 103 and a gate width of 1/n of the gate width of the NMOS 103. The NMOS 121 has a source and a gate connected to the ground potential GND and a drain connected to a node 132. That is, the NMOS 121 is diode-connected in the reverse direction like the NMOS 103 and configured so that 1/n of the off-leak current flowing in the NMOS 103 flows.
The node 132 is connected to the drain and the gate of the PMOS 122 whose source is connected to the power supply potential VDD. The node 132 is connected to the gate of the PMOS 123 whose drain and source are connected to the input terminal 101 and to the power supply potential VDD, respectively. The PMOS 123 has a gate length identical to the PMOS 122, and a gate width which is n times as large as the gate width of the PMOS 112. That is, the PMOS 122 and 123 constitute a current mirror circuit and the current n times as large as the current flowing in the PMOS 122 flows in the PMOS 123.
The PMOS 124 has a drain connected to the node 132. The PMOS 124 has a source connected to the power supply potential VDD and a gate connected to the ground potential GND. Accordingly, the PMOS 124 is always in on state. The PMOS 124 has a gate length and gate width formed so that the ON resistance of the PMOS 124 exhibits quite a high resistance value. Accordingly, the PMOS 124 makes the node 132 the power supply potential VDD for stability of the operation when almost no off-leak current is present in the NMOS 121.
Next, explanation will be given on operation. For example, when the ambient temperature is a room temperature and there is almost no off-leak current, the NMOS 114 of the cancel portion 110 is in an ON state and accordingly, the node 131 is almost ground potential GND and the NMOS 112 and 113 are in an OFF state. Similarly, the PMOS 124 of the cancel portion 120 is in an ON state and accordingly, the node 132 becomes almost power supply potential VDD and PMOS 122 and 123 become OFF.
Here, it is assumed that the ambient temperature has increased and off-leak current flows in the PMOS 102. The PMOS 102 and the PMOS 111 in the cancel portion 110 are formed on the same semiconductor substrate and have an identical gate length. Accordingly, off-leak current also flows in this PMOS 111. When the gate length is identical, the off-leak current flowing is proportional to the gate width and accordingly, the off-leak current flowing in the PMOS 111 becomes 1/n of the PMOS 102. The off-leak current flowing in the PMOS 111 flows into the node 131. The node 131 is connected to the NMOS 112 and 114 but since the NMOS 114 has quite a high resistance, almost no current flows in the NMOS 114. Accordingly, in the NMOS 112, current almost identical to the PMOS 111 flows. The NMOS 112 is connected to the NMOS 113 constituting a current mirror circuit of the current ratio of n multiples. Thus, current n times as large as the PMOS 111 flows in the ground potential GND through the NMOS 113. The current of the PMOS 111 becomes 1/n of the current of the PMOS 102; therefore, the current identical to the current flowing in the PMOS 102 flows in the NMOS 113.
Thus, the off-leak current flowing in the PMOS 102 all flows into the ground potential GND via the NMOS 113 and no off-leak current flows into the signal source connected to the input terminal 101. Similarly, the off-leak current flowing in the NMOS 103 is detected by the NMOS 121 for monitoring of the cancel portion 120 and supplied from the power supply potential VDD via the PMOS 123 to the NMOS 103. Accordingly, no off-leak current flows to the signal source connected to the input terminal 101.
As has been described, the circuit shown in FIG. 4 is a circuit for canceling the off-leak current of the input circuit protecting PMOS 102 and NMOS 103. The off-leak current flowing in the NMOS 103 is detected by the NMOS 121 for monitoring of the cancel portion 120. The current is supplied from the power supply potential VDD via the PMOS 123 to the NMOS 103 to cancel the off-leak current. Based on this background art, when the cancel circuit described above is applied to the voltage-current converter, the problem is raised as follows.
FIG. 5 is a circuit diagram showing a configuration of the voltage-current converter. In the voltage-current converter, the off-leak current of the NMOS 4 is cancelled by a second current generating circuit 12. Thus, the second current generating circuit 12 has a function of decreasing the off-leak current.
Even when the voltage of the input terminal 1 is the ground potential GND, current flows in the PMOS 6 due to the off-leak current of the NMOS 4. This off-leak current greatly depends on the threshold value voltage and the temperature. For example, the off-leak current especially increases when the threshold value voltage of the transistor is low and the temperature is high. Therefore, the off-leak current cannot be ignored depending on the diffusion state in the LSI and the operating temperature of the LSI or the like. Therefore, it becomes difficult to generate the current according to the input voltage. As such, the off-leak current degrades the accuracy of the output current, which degrades the characteristic of the analog circuit.
When the potential of the input terminal 1 increases and the gate potential of the NMOS 4 exceeds the threshold value voltage, current flowing in the node 21 also increases in proportion to the voltage amount that exceeds the threshold value voltage. However, when the large volume of off-leak current flows in the NMOS 4, it becomes difficult to generate the current according to the input voltage. The gate, the source, and the bulk of the NMOS 8 of the second current generating circuit 12 are connected to the ground GND. Therefore, even when the off leak flows in the NMOS 8, there is no voltage fluctuation occurred between the gate and the source. Further, there is no potential difference between the source and the bulk. Therefore, there is no change in the threshold value voltage of the transistor due to the back gate effect and the voltage fluctuation between the gate and the source. However, in the NMOS 4 of the voltage-current converter 11, the gate is connected to the input terminal 1, the source is connected to the resistance element 3, and the bulk is connected to the ground GND. Therefore, there is generated a difference potential between the source and the bulk, whereby the threshold value is made somewhat high due to the back bias effect. The off-leak current flowing in the NMOS 4 depends on the threshold value and the voltage between the gate and the source. The off-leak current flowing in the NMOS 4 of the voltage-current converter 11 is different from the current amount generated in the NMOS 8 in the second current generating circuit 12. Therefore, the current value almost the same as the current value flowing in the NMOS 4 cannot be generated in the NMOS 8. Accordingly, it is not possible to cancel the off-leak current flowing in the NMOS 4 without fail.
SUMMARY
According to the related off-leak current cancel circuit, it is not possible to accurately reproduce the off-leak current generated in the circuit such as the voltage-current converter in which a source is connected to a resistor. As such, according to the related voltage-current converter, the output current accuracy with respect to the input voltage decreases due to the off-leak current.
A first exemplary aspect of an embodiment of the present invention is a voltage-current converter converting an input voltage input to an input terminal to a current to output the current, the voltage-current converter including a first current generating circuit including an input transistor having a gate connected to the input terminal and generating an output current according to a current flowing in the input transistor, and a second current generating circuit including a transistor having a gate having a potential different from potential of a source and a drain, the second current generating circuit generating a superimposed current according to the current flowing in the transistor to supply the superimposed current to the input transistor. According to the present invention, it is possible to cancel the off-leak current flowing in the input transistor without fail; therefore, the output current accuracy with respect to the input voltage can be improved.
According to the present invention, it is possible to provide a voltage-current converter and a voltage controlled oscillator having a high output accuracy with respect to the input voltage.
BRIEF DESCRIPTION OF THE DRAWINGS
The above and other exemplary aspects, advantages and features will be more apparent from the following description of certain exemplary embodiments taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a circuit diagram showing a configuration of a voltage-current converter according to an exemplary embodiment of the present invention;
FIG. 2 is a circuit diagram showing a configuration of a voltage controlled oscillator according to the exemplary embodiment of the present invention;
FIG. 3 is a diagram showing an oscillation frequency of the voltage controlled oscillator;
FIG. 4 is a circuit diagram showing a configuration of an off-leak current cancel circuit according to a related art;
FIG. 5 is a circuit diagram showing a configuration of a voltage-current converter employing the off-leak current cancel circuit of FIG. 4; and
FIG. 6 is a circuit diagram showing a configuration of a voltage controlled oscillator which does not cancel the off-leak current.
 DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS
The exemplary embodiment to which the present invention can be applied will hereinafter be described. The following description describes the exemplary embodiment of the present invention, and this invention is not limited to the following exemplary embodiment. Hereinafter, some parts of the description are omitted and simplified as appropriate for the sake of clarity. A person skilled in the art would readily change, add or modify each element in the following exemplary embodiment within the scope of the present invention. The same components in each drawing are denoted by the same reference numerals, and the description thereof is omitted as appropriate.
A voltage-current converter according to the exemplary embodiment will be described with reference to FIG. 1. FIG. 1 is a circuit diagram showing a configuration of the voltage-current converter. The voltage-current converter includes a first current generating circuit 11 and a second current generating circuit 12.
The first current generating circuit 11 includes an output terminal 2, a resistance element 3, an NMOS (n channel type MOS transistor) 4, a PMOS (p channel type MOS transistor) 5, and a PMOS 6. The NMOS 4 is an input transistor, and a gate of the NMOS 4 is connected to an input terminal 1. Accordingly, an input potential is supplied to the gate of the NMOS 4. A drain of the NMOS 4 is connected to a node 21. A source of the NMOS 4 is connected to a ground potential GND through the resistance element 3. In summary, one end of the resistance element 3 is connected to the source of the NMOS 4, and the other end of the resistance element 3 is connected to the ground potential GND. A node 20 is between the resistance element 3 and the source of the NMOS 4.
A drain and a gate of the PMOS 5 are connected to the node 21. A source of the PMOS 5 is connected to a power supply potential VDD. The PMOS 5 is diode-connected. Further, a gate of the PMOS 6 is connected to the node 21, and a source of the PMOS 6 is connected to the power supply potential VDD. A drain of the PMOS 6 is connected to the output terminal 2. The PMOS 6 has a gate length same to that of the PMOS 5, and has a gate width n (or 1/n) times as large as the gate width of the PMOS 6. Accordingly, the PMOS 5 and the PMOS 6 constitute a current mirror circuit of the current ratio of n multiples.
The current flows in the ground potential GND side according to the potential supplied to the input terminal 1. Therefore, the current flows from the power supply potential VDD to the PMOS 5, the NMOS 4, and the resistance element 3. The PMOS 5 and the PMOS 6 constitute a current mirror circuit. Therefore, the current according to the current flowing in the NMOS 4 flows into the output terminal 2 from the power supply potential VDD through the PMOS 6. In summary, the input voltage input to the input terminal 1 is converted into the current and the current is output from the output terminal 2. Thus the output current according to the input voltage is output from the output terminal 2.
The second current generating circuit 12 is a constant current circuit supplying the current to the NMOS 4 which is the input transistor. The second current generating circuit 12 outputs a superimposed current superimposed on the active current of the NMOS 4. Note that the active current of the NMOS 4 is a current flowing from the power supply potential VDD to the NMOS through the PMOS 5. Therefore, the active current is the current flowing in the NMOS 4 which does not include the current flowing from the second current generating circuit 12. Accordingly, the current actually flowing in the NMOS 4 in the voltage-current converter has the value which is obtained by adding the superimposed current to the active current of the NMOS 4. The superimposed current has the current value identical to the active current flowing in the NMOS 4 in a fixed input voltage.
The second current generating circuit 12 includes a resistance element 7, an NMOS 8, a PMOS 9, and a PMOS 10. The NMOS 8 has a gate length and a gate width identical to those of the NMOS 4. In the exemplary embodiment, a gate of the NMOS 8 is the ground potential GND. A drain of the NMOS 8 is connected to a node 24. A source of the NMOS 8 is connected to the ground potential GND through the resistance element 7. In summary, one end of the resistance element 7 is connected to the source of the NMOS 8, and the other end of the resistance element 7 is connected to the ground potential GND. A node 23 is between the resistance element 7 and the source of the NMOS 8. The resistance element 7 has the same resistance value as that of the resistance element 3. In summary, the resistance element 7 and the resistance element 3 have the same characteristics.
The node 24 is connected to a drain and a gate of the PMOS 9 whose source is connected to the power supply potential VDD. A gate of the PMOS 10 is connected to the node 24. A source of the PMOS 10 is connected to the power supply potential VDD. A drain of the PMOS 10 is connected to the node 21. The PMOS 9 and the PMOS 10 constitute a current mirror circuit of the current ratio of 1 multiple. For example, when the PMOS 9 and the PMOS 10 are formed to have the same gate width and the same gate length, the current mirror circuit of the current ratio of 1 multiple is formed. Note that the second current generating circuit 12 and the first current generating circuit 11 are formed on the same semiconductor substrate. As such, the second current generating circuit 12 and the first current generating circuit 11 almost have the same circuit arrangement.
First, explanation will be given on a case in which the gate of the input terminal 1 is the ground potential GND. The current flows in the NMOS 4 even when the input voltage is the ground potential GND. In summary, the off-leak current is generated in the NMOS 4. The NMOS 4 and the second current generating circuit 12 are formed on the same semiconductor substrate. Further, the NMOS 8 has the same gate length and the same gate width. Therefore, current identical to the current flowing in the NMOS 4 flows in the NMOS 8, which means the off-leak current of the NMOS 8 and the off-leak current of the NMOS 4 are equal to each other.
The NMOS 8 is connected to the PMOS 9, where the current identical to the current flowing in the NMOS 8 flows. The PMOS 10 is connected to the PMOS 9 constituting a current mirror circuit of the current ratio of 1 multiple. Accordingly, current identical to the current flowing in the NMOS 8 flows in the node 21 through the PMOS 10. In summary, current identical to the active current of the NMOS 4 is output from the second current generating circuit 12.
Now, description will be made on a case where the input voltage of the input terminal 1 increases. When the input voltage increases to exceed the threshold value voltage of the NMOS 4, current flowing in the node 21 also increases in proportion to the voltage amount that exceeds the threshold value voltage. Further, when the off-leak current is large, superimposed current is output from the second current generating circuit 12 in order to generate the output current according to the input voltage. The superimposed current has a current value identical to that of the active current flowing in a fixed input voltage. Then the superimposed current generated in the second current generating circuit 12 is supplied to the NMOS 4, and the potential of the node 21 changes. Accordingly, the off-leak current of the NMOS 4 is canceled by the superimposed current from the second current generating circuit 12.
The second current generating circuit 12 is formed to have the configuration substantially identical to the configuration of the first current generating circuit 11 in order to output such a superimposed current. For example, the ground potential GND is connected to the gate of the NMOS 8 corresponding to the NMOS 4 which is the input transistor. The superimposed current is superimposed on the active current of the NMOS 4 which is the input transistor. As a result, the output current accuracy in reduced voltage input can be corrected. As such, it is possible to obtain the output current depending on the threshold value voltage of the NMOS 4 and the input voltage.
The NMOS 8 and the NMOS 4 have the same gate length and the same gate width, and both of them are formed on the same semiconductor substrate. Accordingly, the NMOS 8 and the NMOS 4 substantially have the same property. Accordingly, the output current can be corrected with high accuracy.
Further, in the exemplary embodiment, the source of the NMOS 8 is connected to the ground potential GND through the resistance element 7. Accordingly, when the current flows between the source and the drain of the NMOS 8, the gate of the NMOS 8 has the different potential from those of the source and the drain. More specifically, although the gate of the NMOS 8 is connected to the ground potential GND, the source of the NMOS 8 has the different potential from the ground potential GND due to the resistance element 7. Accordingly, when current flows in the NMOS 8, the voltage between the gate and the source fluctuates, which produces a potential difference between the source and the bulk. Therefore, the threshold value voltage fluctuates due to the voltage fluctuation between the gate and the source and the back gate effect. More specifically, the threshold value voltage of the NMOS 8 becomes somewhat higher. Since the resistance element 3 and the resistance element 7 have the same resistance value, the fluctuation of the threshold value of the NMOS 4 and the NMOS 8 is almost equal to each other. Accordingly, the current almost identical to the active current of the NMOS 4 flows in the NMOS 8.
The voltage decreases when the current flows from the NMOS 4 to the resistance element 3. The source voltage increases and the voltage between the gate and the source fluctuates due to this voltage decrease. In other words, the source voltage of the NMOS 4 increases from the ground potential GND by the voltage amount corresponding to the current value flowing from the NMOS 4 to the resistance element 3 and the resistance value of the resistance element 3. As such, the potential of the node 20 increases from the ground potential GND. The resistance element 7 is connected to the NMOS 8 of the second current generating circuit 12 as well. The voltage decreases due to the resistance element 7. The source voltage of the NMOS 8 increases as is the same way as the NMOS 4. The voltage between the gate and the source of the NMOS 8 fluctuates as in the same way as the voltage between the gate and the source of the NMOS 4. The threshold value voltage of the NMOS 8 fluctuates as in the same way as the threshold value voltage of the NMOS 4. It is possible to make the off-leak current of the NMOS 8 equal to the off-leak current of the NMOS 4. The superimposed current also changes in accordance with the off-leak current of the NMOS 4, and the off-leak current of the NMOS 4 and the superimposed current become equal to each other. Accordingly, the off-leak current of the NMOS 4 can be canceled by the superimposed current. It is possible to correct the output current accuracy in the low voltage input, and to realize the voltage-current converter which enables simple current control. For example, the output current can be corrected even when the ambient temperature is changed.
As described above, there is provided a resistance element 7 between the NMOS 8 and the ground potential GND in the second current generating circuit 12. The superimposed current for canceling the off-leak current of the NMOS 4 is output from the second current generating circuit 12. Accordingly, the superimposed current has a value according to the off-leak current of the NMOS 8. Furthermore, since the NMOS 4 and the NMOS 8 have the same property, the off-leak current becomes equal to each other. As such, the superimposed current changes according to the off-leak current of the NMOS 4. This superimposed current is superimposed on the active current of the NMOS 4. Accordingly, it is possible to correct the output voltage with higher accuracy than the voltage-current converter as shown in FIG. 5. In summary, the gate and the source of the NMOS 8 are directly connected to the ground potential GND in the voltage-current converter shown in FIG. 5. Accordingly, in the voltage-current converter shown in FIG. 5, the threshold value voltage does not change due to the voltage fluctuation between the gate and the source or the back gate effect. Therefore, it is not possible to cancel the off-leak current without fail in the voltage-current converter shown in FIG. 5, which means that the output current accuracy cannot be improved.
In the voltage-current converter according to the exemplary embodiment, the gate of the NMOS 8 is connected to the ground potential GND; therefore, the superimposed current does not change according to the input voltage. Therefore, the second current generating circuit 12 outputs the superimposed current having the current value which does not relate to the input potential of the input terminal 1. Further, the gate and the source of the NMOS 8 have the different potential with each other. As such, the off-leak current can be canceled without fail even with the voltage-current converter in which the resistance element 3 is connected to the source of the NMOS 4 which is the input transistor. More specifically, the second current generating circuit 12 is the constant current circuit generating the superimposed current having the current value equal to the current value flowing in the NMOS 4 except the superimposed current when the input level of the NMOS 4 is in the ground potential GND. Therefore, the active current of the NMOS 4 becomes equal to the superimposed current when the input level of the NMOS 4 is in the ground potential GND. Accordingly, it is possible to cancel the off-leak current without fail. The off-leak current of the NMOS 4 is correctly reproduced in the second current generating circuit 12 to be output to the NMOS 4 as the superimposed current. Accordingly, the output current accuracy with respect to the input voltage can be improved.
Now, an example of employing the voltage-current converter shown in FIG. 1 will be described with reference to FIG. 2. FIG. 2 is a circuit diagram showing a configuration of a voltage controlled oscillator (VCO) including the voltage-current converter shown in FIG. 1. As shown in FIG. 2, the VCO includes a first current generating circuit 11, a second current generating circuit 12, a third current generating circuit 13, and an oscillator 14. In summary, the VCO has a circuit configuration in which the third current generating circuit 13 and the oscillator 14 are added to the voltage-current converter shown in FIG. 1. Since the first current generating circuit 11 and the second current generating circuit 12 have the similar circuit configuration as the circuit shown in FIG. 1 and perform the same way as in the circuit shown in FIG. 1, the description will be omitted here. The VCO is a circuit used in generating clocks or the like. The first current generating circuit 11, the second current generating circuit 12, the third current generating circuit 13, and the oscillator 14 are formed on the same semiconductor substrate.
The third current generating circuit 13 is the constant current circuit and is connected to the node 21. The third current generating circuit 13 includes an NMOS 30, an NMOS 31, and a current source 32. The NMOS 30 has a gate and a drain connected to the current source 32 through a node 25. A source of the NMOS 30 is connected to the ground potential GND. The NMOS 31 has a gate connected to the current source 32 through the node 25, a drain connected to the node 21, and a source connected to the ground potential GND. The NMOS 31 has a gate length identical to that of the NMOS 30. A gate width of the NMOS 31 is n times (or 1/n times) as large as the gate width of the NMOS 30.
The oscillator 14 oscillates in an oscillation frequency according to the output current from the first current generating circuit 11. Therefore, the oscillator 14 is able to generate the clock signal according to the output current from the first current generating circuit 11. In other words, the oscillator 14 is connected to the output terminal 2 of FIG. 1. Note that the circuit configuration of the oscillator 14 is not specifically limited.
In the first current generating circuit 11, the current flows in the node 21 through the NMOS 4 as the potential of the input terminal 1 increases. The PMOS 5 is connected to the node 21. The PMOS 6 is connected to the PMOS 5 constituting a current mirror circuit of the current ratio of 1/n (or n) multiples. Accordingly, the output current 1/n (or n) times as large as the PMOS 5 flows in the node 22 through the PMOS 6. Then the oscillation frequency of the oscillator 14 can be controlled by the output current.
In the third current generating circuit 13, the current flows in the NMOS 30 from the current source 32 through the node 25. Accordingly, the current 1/n (or n) times as large as the NMOS 30 flows in the node 21 through the NMOS 31. Further, the PMOS 5 is connected to the node 21. The PMOS 6 is connected to the PMOS 5 constituting a current mirror circuit of the current ratio of 1/n (or n) multiples. Accordingly, the current 1/n (or n) times as large as the PMOS 5 flows in the node 22 through the PMOS 6. Accordingly, the oscillation frequency of the oscillator 14 when the input terminal 1 is in the GND level is determined by the third current generating circuit 13. When the input voltage of the input terminal 1 changes, the oscillation frequency changes.
FIG. 6 shows a VCO as a comparative example in order to describe the effect of the VCO according to the exemplary embodiment. FIG. 6 shows a circuit configuration of the VCO which does not include a second current generating circuit 12. Therefore, the VCO as the comparative example includes a first current generating circuit 11, a third current generating circuit 13, and an oscillator 14.
When the input terminal 1 is in the ground potential GND level, the oscillation frequency is typically determined only by the current from the third current generating circuit 13. However, when the off-leak current flowing in the NMOS 4 is so large that cannot be ignored, the off-leak current of the NMOS 4 is added to the current from the third current generating circuit 13 in the node 21. The PMOS 5 is connected to the node 21. Further, the PMOS 6 is connected to the PMOS 5. The PMOS 5 and the PMOS 6 constitute a current mirror circuit of the current ratio of 1/n (or n) times.
Accordingly, the current 1/n (or n) times as large as the off-leak current of the NMOS 4 flows in the node 22 in addition to the current amount from the third current generating circuit 13. Therefore, the oscillation frequency increases from what is expected. As a result, according to the circuit configuration in FIG. 6, it becomes difficult to control the frequency. In order to accurately control the frequency, it is needed to correct the output current accuracy of the NMOS 4 in the low voltage input. The VCO shown in FIG. 2 includes a second current generating circuit 12. The second current generating circuit 12 superimposes on the NMOS 4 the superimposed current having the current value identical to the active current flowing when the input potential has a fixed value in the first current generating circuit 11 having the same structure as the related first current generating circuit 11.
The gate of the NMOS 8 of the second current generating circuit 12 is connected to the ground potential GND. Therefore, the superimposed current is supplied from the second current generating circuit 12 to the input transistor NMOS 4 of the first current generating circuit 11. Accordingly, the output current accuracy of the NMOS 4 in the low voltage input can be corrected. As a result, the oscillation frequency depending on the threshold value voltage of the NMOS 4 and the voltage of the input terminal 1 can be obtained.
As such, it is possible to superimpose on the NMOS 4 the superimposed current equal to the active current flowing when the input potential of the input terminal 1 has a fixed value. By adding such a second current generating circuit 12, the output current accuracy in the low voltage input can be corrected. Hence, the oscillation circuit which can easily control the frequency can be realized.
Now, the frequency dependency due to the input voltage in the VCO will be described with reference to FIG. 3. The horizontal axis indicates the input voltage of the input terminal 1 of FIGS. 6 and 2, and the vertical axis is what the output frequency of the oscillator 14 is normalized. In FIG. 3, A shown by dashed-dotted line indicates the oscillation frequency in the related circuit, which is the circuit shown in FIG. 6. B shown by solid line indicates the oscillation frequency in the circuit of the present invention, which is the circuit shown in FIG. 2. C shown by dotted line is the expectation value, which is the value when it is assumed that there is no off-leak current flows.
As shown in FIG. 3, in the line A, the frequency is about twice higher than the expectation value due to the off-leak current when the input voltage is 0.1. On the other hand, in the line B, the frequency which is quite close to the expectation value can be obtained even when the input voltage is 0.1. Accordingly, the output current accuracy in the low voltage input can be corrected, which means the voltage-current converter which can easily control the current can be obtained. The circuit of the present invention is effective in realizing the controlling of the oscillation frequency with high accuracy. Hence, the output accuracy with respect to the input voltage can be improved.
Along with the high-speed operation and the low voltage of the LSI, it is needed to reduce the threshold value voltage. In this case, the off-leak current increases; however, the output current can be controlled with high accuracy by the above-described voltage-current converter.
In the present invention, the constant current circuit is added which superimposes on the input transistor the current value equal to the active current flowing when the input potential of the voltage-current converter has a fixed value. According to the present invention, it is possible to realize the analog circuit with high accuracy, and to realize cost reduction by shortening the development period and improving the yield.
Although the input transistor is the NMOS 4 in the above description, the input transistor may be PMOS as well. In this case, the PMOS is used instead of using the NMOS 4 and the NMOS 8. Then each PMOS may be connected to the power supply potential through the resistance element having the same characteristics. In other words, the MOS transistor may be connected to the power supply voltage or the ground potential GND through the resistance element.
While the invention has been described in terms of several exemplary embodiments, those skilled in the art will recognize that the invention can be practiced with various modifications within the spirit and scope of the appended claims and the invention is not limited to the examples described above.
Further, the scope of the claims is not limited by the exemplary embodiments described above.
Furthermore, it is noted that, Applicant's intent is to encompass equivalents of all claim elements, even if amended later during prosecution.

Claims (11)

1. A voltage-current converter converting an input voltage input to an input terminal to a current to output the current, the voltage-current converter comprising:
a first current generating circuit including an input transistor comprising a gate connected to the input terminal and generating an output current according to a current flowing in the input transistor; and
a second current generating circuit including a transistor comprising a gate having a potential different from a potential of a source and a drain, the second current generating circuit generating a superimposed current according to a current flowing in the transistor to supply the superimposed current to the input transistor,
wherein the superimposed current flows between a source and a drain of the input transistor, and
wherein the second current generating circuit generates the superimposed current having a current value which does not relate to an input potential of the input terminal.
2. The voltage-current converter according to claim 1, wherein the second current generating circuit comprises a constant current circuit generating the superimposed current having a current value equal to a current value flowing in the input transistor except the superimposed current when an input level of the input transistor is in a ground potential.
3. The voltage-current converter according to claim 1, wherein the transistor in the second current generating circuit is formed on a same substrate as the input transistor and has a size corresponding to a gate length and a gate width of the input transistor.
4. The voltage-current converter according to claim 2, wherein the transistor in the second current generating circuit is formed on a same substrate as the input transistor and has a size corresponding to a gate length and a gate width of the input transistor.
5. The voltage-current converter according to claim 1, wherein:
the input transistor is connected to a ground potential or a power supply potential through a first resistance element, and
the transistor is connected to the ground potential or the power supply potential through a second resistance element having same characteristics as the first resistance element.
6. The voltage-current converter according to claim 2, wherein:
the input transistor is connected to a ground potential or a power supply potential through a first resistance element, and
the transistor is connected to the ground potential or the power supply potential through a second resistance element having same characteristics as the first resistance element.
7. The voltage-current converter according to claim 3, wherein:
the input transistor is connected to a ground potential or a power supply potential through a first resistance element, and
the transistor is connected to the ground potential or the power supply potential through a second resistance element having same characteristics as the first resistance element.
8. The voltage-current converter according to claim 4, wherein:
the input transistor is connected to a ground potential or a power supply potential through a first resistance element, and
the transistor is connected to the ground potential or the power supply potential through a second resistance element having same characteristics as the first resistance element.
9. A voltage controlled oscillator, comprising:
a voltage-current converter according to claim 1; and
an oscillator oscillating in an oscillation frequency according to an output current from the voltage-current converter.
10. A voltage controlled oscillator, comprising:
a voltage-current converter according to claim 2; and
an oscillator oscillating in an oscillation frequency according to an output current from the voltage-current converter.
11. A voltage controlled oscillator, comprising:
a voltage-current converter according to claim 5; and
an oscillator oscillating in an oscillation frequency according to an output current from the voltage-current converter.
US12/289,758 2007-12-03 2008-11-03 Voltage-current converter and voltage controlled oscillator Active 2028-12-13 US7893728B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-312259 2007-12-03
JP2007312259A JP2009141393A (en) 2007-12-03 2007-12-03 Voltage/current converting circuit and voltage-controlled oscillation circuit

Publications (2)

Publication Number Publication Date
US20090140776A1 US20090140776A1 (en) 2009-06-04
US7893728B2 true US7893728B2 (en) 2011-02-22

Family

ID=40675074

Family Applications (1)

Application Number Title Priority Date Filing Date
US12/289,758 Active 2028-12-13 US7893728B2 (en) 2007-12-03 2008-11-03 Voltage-current converter and voltage controlled oscillator

Country Status (3)

Country Link
US (1) US7893728B2 (en)
JP (1) JP2009141393A (en)
CN (1) CN101453202A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110050196A1 (en) * 2009-09-02 2011-03-03 Kabushiki Kaisha Toshiba Reference current generating circuit
US20110304386A1 (en) * 2010-06-10 2011-12-15 Panasonic Corporation Constant-voltage circuit
US20190187739A1 (en) * 2017-12-14 2019-06-20 Ablic Inc. Current generation circuit

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101964659B (en) * 2010-08-11 2016-04-27 上海集成电路研发中心有限公司 Voltage current adapter
JP5643046B2 (en) * 2010-09-29 2014-12-17 旭化成エレクトロニクス株式会社 Capacitance sensor circuit
JP5980229B2 (en) * 2011-12-08 2016-08-31 株式会社ソシオネクスト Semiconductor memory device
CN103516357B (en) * 2013-10-08 2016-03-09 苏州芯格微电子有限公司 Voltage Controlled Oscillator for Rail-to-Rail Input Voltage Range
US9385689B1 (en) * 2015-10-13 2016-07-05 Freescale Semiconductor, Inc. Open loop band gap reference voltage generator

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5477170A (en) * 1994-02-17 1995-12-19 Nec Corporation Comparator capable of preventing large noise voltage
US5892390A (en) * 1995-07-11 1999-04-06 Mitsubishi Denki Kabushiki Kaisha Internal power supply circuit with low power consumption
US20020175733A1 (en) 2001-05-22 2002-11-28 Mamoru Kondo Off-leak current cancel circuit

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04170808A (en) * 1990-11-05 1992-06-18 Fuji Electric Co Ltd Voltage-current conversion type rectifier circuit
JP2001135038A (en) * 1999-11-01 2001-05-18 Nec Corp Pll circuit and data reader
JP2006174358A (en) * 2004-12-20 2006-06-29 Renesas Technology Corp Semiconductor integrated circuit device
JP4464294B2 (en) * 2005-03-02 2010-05-19 Ｏｋｉセミコンダクタ株式会社 Voltage controlled oscillator
JP2007129501A (en) * 2005-11-04 2007-05-24 Renesas Technology Corp Semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5477170A (en) * 1994-02-17 1995-12-19 Nec Corporation Comparator capable of preventing large noise voltage
US5892390A (en) * 1995-07-11 1999-04-06 Mitsubishi Denki Kabushiki Kaisha Internal power supply circuit with low power consumption
US20020175733A1 (en) 2001-05-22 2002-11-28 Mamoru Kondo Off-leak current cancel circuit
JP2002344251A (en) 2001-05-22 2002-11-29 Oki Electric Ind Co Ltd Off-leak current canceling circuit
US6650164B2 (en) 2001-05-22 2003-11-18 Oki Electric Industry Co., Ltd. Off-leak current cancel circuit

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110050196A1 (en) * 2009-09-02 2011-03-03 Kabushiki Kaisha Toshiba Reference current generating circuit
US8148970B2 (en) * 2009-09-02 2012-04-03 Kabushiki Kaisha Toshiba Reference current generating circuit
US20110304386A1 (en) * 2010-06-10 2011-12-15 Panasonic Corporation Constant-voltage circuit
US8368459B2 (en) * 2010-06-10 2013-02-05 Panasonic Corporation Constant-voltage circuit
US20190187739A1 (en) * 2017-12-14 2019-06-20 Ablic Inc. Current generation circuit
US10503197B2 (en) * 2017-12-14 2019-12-10 Ablic Inc. Current generation circuit

Also Published As

Publication number Publication date
CN101453202A (en) 2009-06-10
US20090140776A1 (en) 2009-06-04
JP2009141393A (en) 2009-06-25

Similar Documents

Publication Publication Date Title
US7893728B2 (en) Voltage-current converter and voltage controlled oscillator
JP4544458B2 (en) Semiconductor device
US7746149B2 (en) Voltage level shift circuit and semiconductor integrated circuit
JP3808867B2 (en) Reference power circuit
US7852142B2 (en) Reference voltage generating circuit for use of integrated circuit
JP2008015925A (en) Reference voltage generation circuit
US8134814B2 (en) Semiconductor device having an ESD protection circuit
US20120319793A1 (en) Oscillation circuit
JP2011150526A (en) Reference voltage generation circuit and integrated circuit incorporating the same
JP5085233B2 (en) Reference voltage generation circuit and timer circuit
JP4727294B2 (en) Power circuit
WO2008032606A1 (en) Reference current circuit, reference voltage circuit, and startup circuit
US7420414B2 (en) Amplifier, and step-down regulator and operational amplifier using the amplifier
US8089326B2 (en) PVT-independent current-controlled oscillator
JP7366692B2 (en) power circuit
JP2004187150A (en) Semiconductor integrated circuit
US6853256B2 (en) Voltage controlled oscillator with reference current generator
JP2004015423A (en) Circuit for generating constant current
US20180275710A1 (en) Standard voltage circuit and semiconductor integrated circuit
US7847645B2 (en) Oscillation control apparatus and oscillator
CN110601658B (en) Automatic compensation of control voltage range of low voltage VCO
US7474152B2 (en) Operational amplifier circuit
JP5198971B2 (en) Oscillator circuit
KR101919555B1 (en) Reference current source
TWI395087B (en) Pvt-independent current-controlled oscillator

Legal Events

Date Code Title Description
AS Assignment

Owner name: NEC ELECTRONICS CORPORATION, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HIRAI, KAZUNOSUKE;REEL/FRAME:021841/0460

Effective date: 20081023

AS Assignment

Owner name: RENESAS ELECTRONICS CORPORATION, JAPAN

Free format text: CHANGE OF NAME;ASSIGNOR:NEC ELECTRONICS CORPORATION;REEL/FRAME:025214/0175

Effective date: 20100401

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

AS Assignment

Owner name: RENESAS ELECTRONICS CORPORATION, JAPAN

Free format text: CHANGE OF ADDRESS;ASSIGNOR:RENESAS ELECTRONICS CORPORATION;REEL/FRAME:044928/0001

Effective date: 20150806

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 8

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 12