US7851266B2 - Microelectronic device wafers including an in-situ molded adhesive, molds for in-situ molding adhesives on microelectronic device wafers, and methods of molding adhesives on microelectronic device wafers - Google Patents
Microelectronic device wafers including an in-situ molded adhesive, molds for in-situ molding adhesives on microelectronic device wafers, and methods of molding adhesives on microelectronic device wafers Download PDFInfo
- Publication number
- US7851266B2 US7851266B2 US12/323,926 US32392608A US7851266B2 US 7851266 B2 US7851266 B2 US 7851266B2 US 32392608 A US32392608 A US 32392608A US 7851266 B2 US7851266 B2 US 7851266B2
- Authority
- US
- United States
- Prior art keywords
- wafer
- adhesive
- temperature
- face
- microelectronic device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000853 adhesive Substances 0.000 title claims abstract description 113
- 230000001070 adhesive effect Effects 0.000 title claims abstract description 113
- 238000000034 method Methods 0.000 title claims abstract description 26
- 238000004377 microelectronic Methods 0.000 title claims abstract description 23
- 238000000465 moulding Methods 0.000 title claims abstract description 19
- 235000012431 wafers Nutrition 0.000 title abstract description 78
- 238000011065 in-situ storage Methods 0.000 title abstract description 14
- 238000010438 heat treatment Methods 0.000 claims abstract description 12
- 239000007788 liquid Substances 0.000 claims abstract description 10
- 239000012790 adhesive layer Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 9
- 239000000843 powder Substances 0.000 claims description 5
- 238000004806 packaging method and process Methods 0.000 claims 4
- 238000001816 cooling Methods 0.000 claims 2
- 239000004065 semiconductor Substances 0.000 claims 2
- 238000000151 deposition Methods 0.000 claims 1
- 239000007787 solid Substances 0.000 abstract description 9
- 230000001678 irradiating effect Effects 0.000 abstract 1
- 238000001723 curing Methods 0.000 description 9
- RAXXELZNTBOGNW-UHFFFAOYSA-N imidazole Natural products C1=CNC=N1 RAXXELZNTBOGNW-UHFFFAOYSA-N 0.000 description 9
- 239000000463 material Substances 0.000 description 6
- 230000005855 radiation Effects 0.000 description 6
- 239000002904 solvent Substances 0.000 description 6
- 238000000576 coating method Methods 0.000 description 5
- 239000003054 catalyst Substances 0.000 description 4
- 230000005670 electromagnetic radiation Effects 0.000 description 4
- 239000000945 filler Substances 0.000 description 4
- 239000004848 polyfunctional curative Substances 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 238000011068 loading method Methods 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 239000004925 Acrylic resin Substances 0.000 description 2
- 229920000178 Acrylic resin Polymers 0.000 description 2
- VTYYLEPIZMXCLO-UHFFFAOYSA-L Calcium carbonate Chemical compound [Ca+2].[O-]C([O-])=O VTYYLEPIZMXCLO-UHFFFAOYSA-L 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 150000008065 acid anhydrides Chemical class 0.000 description 2
- 239000002313 adhesive film Substances 0.000 description 2
- -1 e.g. Substances 0.000 description 2
- 230000007613 environmental effect Effects 0.000 description 2
- 239000010419 fine particle Substances 0.000 description 2
- 239000003999 initiator Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- MXRIRQGCELJRSN-UHFFFAOYSA-N O.O.O.[Al] Chemical compound O.O.O.[Al] MXRIRQGCELJRSN-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- OJMOMXZKOWKUTA-UHFFFAOYSA-N aluminum;borate Chemical compound [Al+3].[O-]B([O-])[O-] OJMOMXZKOWKUTA-UHFFFAOYSA-N 0.000 description 1
- 150000008064 anhydrides Chemical class 0.000 description 1
- 150000001450 anions Chemical class 0.000 description 1
- KQNZLOUWXSAZGD-UHFFFAOYSA-N benzylperoxymethylbenzene Chemical compound C=1C=CC=CC=1COOCC1=CC=CC=C1 KQNZLOUWXSAZGD-UHFFFAOYSA-N 0.000 description 1
- 229910000019 calcium carbonate Inorganic materials 0.000 description 1
- 239000006229 carbon black Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000269 nucleophilic effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 150000003254 radicals Chemical class 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- VLCLHFYFMCKBRP-UHFFFAOYSA-N tricalcium;diborate Chemical compound [Ca+2].[Ca+2].[Ca+2].[O-]B([O-])[O-].[O-]B([O-])[O-] VLCLHFYFMCKBRP-UHFFFAOYSA-N 0.000 description 1
- WLOQLWBIJZDHET-UHFFFAOYSA-N triphenylsulfonium Chemical class C1=CC=CC=C1[S+](C=1C=CC=CC=1)C1=CC=CC=C1 WLOQLWBIJZDHET-UHFFFAOYSA-N 0.000 description 1
- 239000002966 varnish Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
- H01L24/743—Apparatus for manufacturing layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
- H01L2224/83856—Pre-cured adhesive, i.e. B-stage adhesive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0102—Calcium [Ca]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01049—Indium [In]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01057—Lanthanum [La]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/0665—Epoxy resin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Definitions
- the present disclosure is related to microelectronic device wafers and manufacturing the same.
- the present disclosure relates to a microelectronic device wafer including an adhesive that is molded in-situ on the wafer, a mold for in-situ molding, and methods of in-situ molding an adhesive onto a microelectronic device wafer.
- Adhesives are typically used to couple a microelectronic device die to a substrate and/or to couple a stack of microelectronic dies. These adhesives are conventionally applied to microelectronic devices at the wafer level via die attach adhesive films, stencil or screen printable adhesive coatings, or spin-coatable adhesive coatings. In the case of films, a solvent is used for the varnish to coat adhesive films. After coating, the solvent has to be dried. Spin-coatable materials conventionally also contain solvents that have to be dried after wafer coating. Drying solvents can raise environmental concerns and increase both the processing complexity and time required to conventionally apply an adhesive to a microelectronic device wafer.
- the conventional techniques for applying adhesives at the wafer level can also be wasteful insofar as material in excess of that required to coat the wafer frequently is cast off or must be removed. This waste also increases the processing complexity and time required to conventionally apply an adhesive to a microelectronic device wafer. Moreover, uneven coating thickness also can result from the conventional applications for applying adhesives to a microelectronic device wafer.
- FIG. 1 is a schematic perspective view of a wafer in accordance with embodiments of the present disclosure.
- FIG. 2 is a schematic cross-section view showing the wafer of FIG. 1 positioned in an opened mold in accordance with embodiments of the present disclosure.
- FIG. 3 is a schematic cross-section view showing adhesive dispensed in accordance with embodiments of the present disclosure on the wafer in the mold of FIG. 2 .
- FIG. 4 is a schematic cross-section view showing a closed mold in accordance with embodiments of the present disclosure.
- FIG. 5 is a schematic cross-section view showing an adhesive molded wafer in accordance with embodiments of the present disclosure.
- FIG. 6 is a schematic cross-section view showing the adhesive molded wafer of FIG. 5 mounted on dicing film in accordance with embodiments of the present disclosure.
- FIG. 7 is a schematic cross-section view showing the adhesive molded wafer of FIG. 6 singulated in accordance with embodiments of the present disclosure.
- FIG. 8 is a schematic elevation view showing a microelectronic device including a singulated wafer portion adhesively coupled to a substrate in accordance with embodiments of the present disclosure.
- the microelectronic devices can include, for example, micromechanical components, data storage elements, optics, read/write components, or other features.
- the microelectronic dies can be flash memory (e.g., NAND flash memory), SRAM, DRAM (e.g., DDR-SDRAM), processors, imagers, and other types of devices.
- flash memory e.g., NAND flash memory
- SRAM SRAM
- DRAM e.g., DDR-SDRAM
- processors imagers
- Other embodiments of the disclosure can have configurations, components, features or procedures different than those described in this section. A person of ordinary skill in the art, therefore, will accordingly understand that the disclosure may have other embodiments with additional elements, or the disclosure may have other embodiments without several of the elements shown and described below with reference to FIGS. 1 to 8 .
- FIG. 1 is a schematic perspective view of a wafer 10 in accordance with embodiments of the present disclosure.
- the wafer 10 can include a first face 20 , a second face 30 spaced from the first face 20 along an axis A, and an edge 40 adjoining the first and second faces 20 and 30 .
- the first face 20 is approximately circular with a perimeter 22 defined by a first radius 24 from the axis A.
- the second face 30 can be approximately parallel to the first face 20 .
- the first and second faces 20 and 30 can have any regular or irregular shape and can be obliquely oriented with respect to one another, and/or the edge 40 can have any suitable contour and can be oriented in a regular or skewed relationship with respect to the first and/or second faces 20 and 30 .
- the first face 20 can be, for example, a back side or passive side of the wafer 10
- the second face 30 can be, for example, a front side or active side of the wafer 10 where the dies are fabricated.
- the wafer 10 typically includes single crystalline silicon but can include any suitable wafer material.
- the wafer 10 can have a regular thickness, e.g., measured parallel to the axis A between the first and second faces 20 and 30 , or can be thinned according to any suitable technique. In the embodiment shown in FIG. 1 , the wafer 10 is not singulated such that a plurality of individual dies (not shown) is at the second face 30 of the wafer 10 .
- FIG. 2 is a schematic cross-section view showing a stage of a method for applying an adhesive to the wafer 10 using a mold 100 in accordance with embodiments of the present disclosure.
- an opened configuration of the mold 100 provides access to a cavity 102 that approximately conforms to the edge 40 of the wafer 10 .
- the cavity 102 has a right-cylindrical shape that is sized with respect to the wafer 10 so as to allow the wafer 10 to be freely positioned into and removed from the mold 100 .
- the cavity 102 is also sized so as to avoid or prevent an adhesive from being displaced between the edge 40 and the mold 100 .
- a vacuum source 110 is coupled with the cavity 102 via a passage system 112 .
- the passage system 112 includes a port 112 a coupled with a vent ring 112 b that is positioned around the mold 100 . Accordingly, the vacuum source 110 is in fluid communication with the cavity 102 via the passage system 112 .
- one or more discrete openings in lieu of the vent ring 112 b can be coupled to the port 112 a.
- FIG. 3 is a schematic cross-section view showing a subsequent stage of the method in which an adhesive 200 is dispensed onto the wafer 10 in the mold 100 in accordance with embodiments of the present disclosure.
- the adhesive 200 can be dispensed from an adhesive source 210 via a conduit system 212 .
- the conduit system 212 dispenses the adhesive 200 with the mold 100 in the opened configuration.
- the adhesive 200 can be injected into the cavity 102 with the mold 100 in a closed configuration (not shown), or by any suitable dispensing technique.
- the adhesive 200 is dispensed onto only one face surface, e.g., the first face 20 as shown in FIG. 3 .
- the volume and/or mass of adhesive 200 are precisely metered so that the thickness of the adhesive layer can be accurately controlled.
- the volume can be determined based on the area of the first face 20 and the target thickness of the adhesive 200 on the first face 20 of the wafer 10 . Accordingly, only the amount of adhesive 200 that is needed to cover only one side of the wafer 10 at the target thickness is dispensed from the adhesive source 200 . This enables good control of the target thickness with little or no waste according to the present disclosure.
- the adhesive 200 can have different forms including a liquid adhesive, a solid adhesive, e.g., powder, or any suitable form that can be dispensed.
- a liquid adhesive the adhesive 200 can flow onto the wafer 10 via the conduit system 212 .
- the adhesive 200 can be deposited on the wafer 10 by any suitable technique via the conduit system 212 .
- the adhesive 200 is solvent free to be more environmentally friendly and can include a high filler loading to reduce or eliminate warpage of the wafer 10 and/or the individual dies (not shown).
- the adhesive 200 can have a dual cure system.
- an acrylic resin can be cured during molding with a free radical initiator such as benzyl peroxide at a low temperature (e.g., below approximately 100 degrees Celsius), and an epoxy resin can be subsequently cured with a hardener such as acid anhydride and a catalyst such as imidazole and its derivatives at a relatively higher temperature (e.g., above approximately 150 degrees Celsius).
- a free radical initiator such as benzyl peroxide
- an epoxy resin can be subsequently cured with a hardener such as acid anhydride and a catalyst such as imidazole and its derivatives at a relatively higher temperature (e.g., above approximately 150 degrees Celsius).
- providing ultraviolet radiation during molding can be used to cure an acrylic resin including an ultraviolet initiator such as triphenylsulfonium salts with non-nucleophilic anions at room temperature, and an epoxy resin can be subsequently cured with a hardener such as acid anhydride and a catalyst such as imidazole and its derivatives at a temperature of approximately 150 degrees Celsius.
- the adhesive can include a high molecular epoxy resin, its hardener, a catalyst, and any suitable additives.
- a mixture is a powdered or fine particle solid at room temperature. At a molding temperature (e.g., approximately 100 degrees Celsius), the mixture can soften and be molded, and there can be a minimum curing reaction.
- the epoxy curing reaction can subsequently take place at a relatively higher temperature (e.g., above approximately 150 degrees Celsius).
- the epoxy curing reaction can be determined by the hardener, such as an anhydride, and the catalyst, such as imidazole and its derivatives.
- FIG. 4 is a schematic cross-section view showing a subsequent stage of the method in which a plate 120 approximately occludes the cavity 102 in a closed configuration of the mold 100 .
- the plate 120 is sized so as to avoid or prevent the adhesive 200 from being displaced between the mold 100 and the plate 120 .
- the plate 120 can exert a downward force, e.g., by gravity or an active force, against the adhesive 200 to distribute the adhesive 200 across the first face 20 of the wafer 10 .
- the plate 120 can be a thermally conductive material or transparent to electromagnetic energy (e.g., microwave or infrared).
- a heat source 130 is positioned with respect to the mold 100 so as to increase the temperature of the adhesive 200 .
- the heat source 130 can be coupled to the plate 120 such that heat from the heat source 130 is conducted via the plate 120 to the adhesive 200 .
- the heat source 130 can include an electromagnetic wave generator, e.g., an infrared generator, and the plate 120 can be transparent to the generated electromagnetic radiation.
- the adhesive 200 can accordingly be directly heated by the electromagnetic radiation.
- the heat source 130 can be arranged with respect to any suitable portion of the mold 100 and any suitable source of heat can be used that increases the temperature of the adhesive 200 .
- the vacuum source 110 and the heat source 130 can be activated concurrently.
- the vacuum source 110 can draw at least a partial vacuum in the cavity 102 via the passage system 112 , and the heat source 130 can increase the temperature of the adhesive 200 in the cavity 102 .
- Other embodiments in accordance with the present disclosure can sequentially or alternately activate the vacuum and heat sources 110 and 130 .
- the combination of drawing at least a partial vacuum and increasing the temperature to a first level in the cavity 102 molds in-situ the adhesive 200 on the wafer 10 .
- the first temperature level is sufficient to attach the adhesive 200 to the wafer 10 without fully curing or activating the adhesive 200 .
- in-situ molding of the adhesive 200 on the wafer 10 at the first temperature level can include partially curing, e.g., B-staging, the adhesive 200 .
- B-staging can refer to a process that includes converting adhesive in a liquid form to a solid or semi-solid form that is not hardened or fully cured.
- Ultraviolet radiation can also be used to partially cure the adhesive 200 .
- the ultraviolet radiation can be generated by an ultraviolet lamp (not shown) that is in addition to or in lieu of the heat source 130 .
- the plate 120 can be transparent to the ultraviolet radiation.
- any suitable source of electromagnetic radiation that partially cures the adhesive 200 can be arranged with respect to any suitable portion of the mold 100 .
- partially curing the adhesive 200 with electromagnetic radiation can occur while the adhesive 200 is at ambient temperature, e.g., at room temperature.
- the in-situ molding can include melting the adhesive 200 on the wafer 10 at the first temperature level. Melting the solid form of the adhesive 200 allows the adhesive to spread across the first face 20 and become approximately uniformly distributed on the wafer 10 . Partially curing is optional during in-situ molding if the pre-molded adhesive 200 is in a solid form.
- the adhesive molded on the wafer can be cooled to a second temperature level and removed from the mold 100 .
- the second temperature level which is lower than the first temperature level, typically reduces the tackiness.
- a film 140 can be positioned between the plate 120 and the pre-molded adhesive 200 .
- the film 140 can assist in molding the adhesive by easing release of the plate 120 following the in-situ molding.
- the film can be positioned in any suitable location, e.g., between the wafer 10 and the mold 100 , to ease releasing the wafer with the adhesive layer from the mold 100 .
- Methods of in-situ molding an adhesive onto a wafer enable the use of a precise amount of solvent-free adhesive to cover only one face of a wafer. Accordingly, little or no adhesive is wasted and, as compared to solvent-based adhesives, potentially adverse environmental impacts are reduced or eliminated. Additionally, the target thickness of the adhesive is applied uniformly over the face of the wafer. According to other embodiments of the present disclosure, different forms of adhesives, e.g., liquids or powders, different types of heat sources, and different heating routines enable flexibility in molding and curing the adhesive on a wafer. Die attach adhesives with higher filler loading can be molded onto a wafer according to still other embodiments of the present disclosure.
- suitable filler materials can include silica, aluminum trihydroxide, aluminum borate, calcium borate, calcium carbonate, lanthanum borite (LaB 6 ), indium tin oxide, carbon black, and/or any suitable material in a particle or particulate form.
- FIG. 5 is a schematic cross-section view showing a wafer 1000 including a molded adhesive 1200 in accordance with embodiments of the present disclosure. More specifically, the wafer 1000 includes the molded adhesive 1200 positioned on the first face 20 of the wafer 10 and extending outwardly only to the edge 40 of the wafer 10 . Accordingly, the entire first face 20 is covered with an approximately uniform thickness of the molded adhesive 1200 and little or none of the pre-molded adhesive has been lost or wasted.
- FIG. 6 is a schematic cross-section view showing the wafer 1000 including the molded adhesive 1200 mounted on dicing film 1300 in accordance with embodiments of the present disclosure.
- the wafer 1000 can be flipped over and the molded adhesive 1200 mounted on the dicing film 1300 .
- the dicing film 1300 can be mounted on the molded adhesive 1200 included on the wafer 1000 and then the combination can be flipped over as necessary for subsequent processing. Any suitable technique can be used for coupling the dicing film 1300 and the wafer 1000 including the molded adhesive 1200 .
- FIG. 7 is a schematic cross-section view showing the adhesive molded wafer 1000 singulated in accordance with embodiments of the present disclosure.
- the adhesive molded wafer 1000 can be singulated into portions 1010 (e.g., individual portions 1010 a to 1010 e are shown in FIG. 7 ) that can each include an individual die (not shown).
- the singulated wafer portions 1010 can be separated from the dicing film 1300 by any suitable technique for subsequent processing.
- FIG. 8 is a schematic elevation view showing a microelectronic device 2000 including a singulated wafer portion 1010 adhesively coupled to a substrate 1400 in accordance with embodiments of the present disclosure.
- the wafer portion 1010 can be adhesively coupled to the substrate 1400 by heating the wafer portion 1010 to a third temperature level that changes the molded adhesive 1200 to a tacky state. Accordingly, the molded adhesive 1200 can adhere the wafer portion 1010 to the substrate 1400 .
- the third temperature level is greater than the second temperature level, but may be less than, equal to, or greater than the first temperature level.
- the substrate 1400 can include another singulated wafer portion, a die, a stack of dies, or any combination thereof.
- the microelectronic device 2000 can include an individual die 1012 electrically coupled to the substrate 1400 by electrical connectors 1014 (e.g., wire bonds).
- the microelectronic device 2000 can be packaged in an encapsulant 1500 and heated to a fourth temperature level to fully cure the molded adhesive 1200 .
- the fourth temperature level can be at least as great as the first temperature level.
- the molded adhesive 1200 can be heated to the fourth temperature level to fully cure the molded adhesive 1200 separately from encapsulating the microelectronic device 2000 .
- the molded adhesive 1200 can be fully cured by a different thermal treatment, e.g., heating at a lower temperature for a longer period, by ultraviolet radiation, by microwave radiation, or by any suitable curing technique.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Adhesives Or Adhesive Processes (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
Claims (9)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/323,926 US7851266B2 (en) | 2008-11-26 | 2008-11-26 | Microelectronic device wafers including an in-situ molded adhesive, molds for in-situ molding adhesives on microelectronic device wafers, and methods of molding adhesives on microelectronic device wafers |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/323,926 US7851266B2 (en) | 2008-11-26 | 2008-11-26 | Microelectronic device wafers including an in-situ molded adhesive, molds for in-situ molding adhesives on microelectronic device wafers, and methods of molding adhesives on microelectronic device wafers |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| US20100127409A1 US20100127409A1 (en) | 2010-05-27 |
| US7851266B2 true US7851266B2 (en) | 2010-12-14 |
Family
ID=42195490
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US12/323,926 Active US7851266B2 (en) | 2008-11-26 | 2008-11-26 | Microelectronic device wafers including an in-situ molded adhesive, molds for in-situ molding adhesives on microelectronic device wafers, and methods of molding adhesives on microelectronic device wafers |
Country Status (1)
| Country | Link |
|---|---|
| US (1) | US7851266B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9117813B2 (en) | 2012-06-15 | 2015-08-25 | General Electric Company | Integrated circuit package and method of making same |
| US9209046B2 (en) * | 2013-10-02 | 2015-12-08 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and manufacturing method thereof |
| TWI575779B (en) * | 2014-03-31 | 2017-03-21 | 精材科技股份有限公司 | Chip package and method for forming the same |
| US12230511B2 (en) | 2020-08-24 | 2025-02-18 | Stmicroelectronics S.R.L. | Method of manufacturing semiconductor devices and corresponding device |
Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5160462A (en) * | 1986-02-14 | 1992-11-03 | Canon Kabushiki Kaisha | Preparing optical memory medium by laminating a thermoplastic resin layer on a thermosetting resin sheet |
| US5492586A (en) | 1993-10-29 | 1996-02-20 | Martin Marietta Corporation | Method for fabricating encased molded multi-chip module substrate |
| US5650915A (en) | 1994-05-25 | 1997-07-22 | Texas Instruments Incorporated | Thermally enhanced molded cavity package having a parallel lid |
| US5997786A (en) | 1995-10-02 | 1999-12-07 | Dow Corning Corporation | Method for bonding rigid substrates |
| US6184064B1 (en) | 2000-01-12 | 2001-02-06 | Micron Technology, Inc. | Semiconductor die back side surface and method of fabrication |
| US20020197770A1 (en) * | 2001-06-26 | 2002-12-26 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing semiconductor chips |
| US6703075B1 (en) | 2002-12-24 | 2004-03-09 | Chipmos Technologies (Bermuda) Ltd. | Wafer treating method for making adhesive dies |
| US6723583B2 (en) * | 2000-12-20 | 2004-04-20 | Renesas Technology Corp. | Method of manufacturing a semiconductor device using a mold |
| US20040235271A1 (en) * | 2000-07-03 | 2004-11-25 | Fujitsu Limited | Manufacture of wafer level semiconductor device with quality markings on the sealing resin |
| US20050048693A1 (en) * | 2003-08-28 | 2005-03-03 | Tae-Sung Yoon | Method of manufacturing wafer-level chip-size package and molding apparatus used in the method |
| US20060102987A1 (en) * | 2004-11-12 | 2006-05-18 | Lintec Corporation | Marking method and sheet for both protective film forming and dicing |
| US20060189036A1 (en) * | 2005-02-08 | 2006-08-24 | Micron Technology, Inc. | Methods and systems for adhering microfeature workpieces to support members |
| US20070126129A1 (en) | 2005-12-06 | 2007-06-07 | Ace Industries Co., Ltd. | Die bonding adhesive tape |
| US7312534B2 (en) | 2002-06-17 | 2007-12-25 | Henkel Corporation | Interlayer dielectric and pre-applied die attach adhesive materials |
-
2008
- 2008-11-26 US US12/323,926 patent/US7851266B2/en active Active
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5160462A (en) * | 1986-02-14 | 1992-11-03 | Canon Kabushiki Kaisha | Preparing optical memory medium by laminating a thermoplastic resin layer on a thermosetting resin sheet |
| US5492586A (en) | 1993-10-29 | 1996-02-20 | Martin Marietta Corporation | Method for fabricating encased molded multi-chip module substrate |
| US5650915A (en) | 1994-05-25 | 1997-07-22 | Texas Instruments Incorporated | Thermally enhanced molded cavity package having a parallel lid |
| US5997786A (en) | 1995-10-02 | 1999-12-07 | Dow Corning Corporation | Method for bonding rigid substrates |
| US6184064B1 (en) | 2000-01-12 | 2001-02-06 | Micron Technology, Inc. | Semiconductor die back side surface and method of fabrication |
| US20040235271A1 (en) * | 2000-07-03 | 2004-11-25 | Fujitsu Limited | Manufacture of wafer level semiconductor device with quality markings on the sealing resin |
| US6723583B2 (en) * | 2000-12-20 | 2004-04-20 | Renesas Technology Corp. | Method of manufacturing a semiconductor device using a mold |
| US20020197770A1 (en) * | 2001-06-26 | 2002-12-26 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing semiconductor chips |
| US7312534B2 (en) | 2002-06-17 | 2007-12-25 | Henkel Corporation | Interlayer dielectric and pre-applied die attach adhesive materials |
| US6703075B1 (en) | 2002-12-24 | 2004-03-09 | Chipmos Technologies (Bermuda) Ltd. | Wafer treating method for making adhesive dies |
| US20050048693A1 (en) * | 2003-08-28 | 2005-03-03 | Tae-Sung Yoon | Method of manufacturing wafer-level chip-size package and molding apparatus used in the method |
| US20060102987A1 (en) * | 2004-11-12 | 2006-05-18 | Lintec Corporation | Marking method and sheet for both protective film forming and dicing |
| US20060189036A1 (en) * | 2005-02-08 | 2006-08-24 | Micron Technology, Inc. | Methods and systems for adhering microfeature workpieces to support members |
| US20070126129A1 (en) | 2005-12-06 | 2007-06-07 | Ace Industries Co., Ltd. | Die bonding adhesive tape |
Non-Patent Citations (4)
| Title |
|---|
| ‘Adhesive’ definition from dictionary.com. * |
| ‘Resin’ definition from dictionary.com. * |
| 'Adhesive' definition from dictionary.com. * |
| 'Resin' definition from dictionary.com. * |
Also Published As
| Publication number | Publication date |
|---|---|
| US20100127409A1 (en) | 2010-05-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7776648B2 (en) | High thermal performance packaging for circuit dies | |
| CN106415823B (en) | The manufacturing method of semiconductor device, stack-up type semiconductor device, sealing back-set bed type semiconductor device and these devices | |
| US20090221114A1 (en) | Packaging an integrated circuit die using compression molding | |
| TW201007858A (en) | Packaging an integrated circuit die with backside metallization | |
| US8729714B1 (en) | Flip-chip wafer level package and methods thereof | |
| US20100224983A1 (en) | Semiconductor package structure and manufacturing method thereof | |
| US20080182363A1 (en) | Method for forming a microelectronic assembly including encapsulating a die using a sacrificial layer | |
| US7851266B2 (en) | Microelectronic device wafers including an in-situ molded adhesive, molds for in-situ molding adhesives on microelectronic device wafers, and methods of molding adhesives on microelectronic device wafers | |
| TW200531189A (en) | Die encapsulation using a porous carrier | |
| TW201201288A (en) | Chip-sized package and fabrication method thereof | |
| KR101968428B1 (en) | Method of manufacturing semiconductor device, and semiconductor device | |
| KR102773215B1 (en) | Coplanar control for film-type thermal interface | |
| JP6467689B2 (en) | Hollow structure electronic components | |
| Yim et al. | Ultra thin PoP top package using compression mold: Its warpage control | |
| US20150303130A1 (en) | Semiconductor Package and Method of Manufacturing the Same | |
| TW201521165A (en) | COF type semiconductor package and manufacturing method thereof | |
| WO2024051238A1 (en) | Chip packaging structure and preparation method | |
| CN101388367B (en) | Wafer level packaging method and its packaging structure | |
| TW201606037A (en) | Enhanced pressure sensitive adhesive for thermal management applications | |
| TW202032674A (en) | Method of manufacturing semiconductor device, film-like adhesive, and dicing/die-bonding integrated film | |
| Braun et al. | Challenges and opportunities for fan-out panel level packing (FOPLP) | |
| JP2006196705A (en) | Method for forming circuit element and multilayer circuit element | |
| TW201543587A (en) | Method of packaging semiconductor devices and apparatus for performing the same | |
| CN101689514B (en) | Method for packaging semiconductor | |
| US20130087951A1 (en) | Molding Chamber Apparatus and Curing Method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| AS | Assignment |
Owner name: MICRON TECHNOLOGY, INC., IDAHO Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:JIANG, TONGBI;LUO, SHIJIAN;REEL/FRAME:021895/0742 Effective date: 20081125 |
|
| FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
| STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
| FPAY | Fee payment |
Year of fee payment: 4 |
|
| AS | Assignment |
Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT, CALIFORNIA Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001 Effective date: 20160426 Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001 Effective date: 20160426 |
|
| AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT, MARYLAND Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001 Effective date: 20160426 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001 Effective date: 20160426 |
|
| AS | Assignment |
Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT, CALIFORNIA Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:043079/0001 Effective date: 20160426 Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:043079/0001 Effective date: 20160426 |
|
| MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552) Year of fee payment: 8 |
|
| AS | Assignment |
Owner name: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT, ILLINOIS Free format text: SECURITY INTEREST;ASSIGNORS:MICRON TECHNOLOGY, INC.;MICRON SEMICONDUCTOR PRODUCTS, INC.;REEL/FRAME:047540/0001 Effective date: 20180703 Owner name: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT, IL Free format text: SECURITY INTEREST;ASSIGNORS:MICRON TECHNOLOGY, INC.;MICRON SEMICONDUCTOR PRODUCTS, INC.;REEL/FRAME:047540/0001 Effective date: 20180703 |
|
| AS | Assignment |
Owner name: MICRON TECHNOLOGY, INC., IDAHO Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT;REEL/FRAME:047243/0001 Effective date: 20180629 |
|
| AS | Assignment |
Owner name: MICRON TECHNOLOGY, INC., IDAHO Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT;REEL/FRAME:050937/0001 Effective date: 20190731 |
|
| AS | Assignment |
Owner name: MICRON SEMICONDUCTOR PRODUCTS, INC., IDAHO Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:051028/0001 Effective date: 20190731 Owner name: MICRON TECHNOLOGY, INC., IDAHO Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:051028/0001 Effective date: 20190731 |
|
| MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 12 |