US7776514B2 - Pattern forming method, semiconductor device manufacturing method and phase shift photomask having dummy gate patterns - Google Patents
Pattern forming method, semiconductor device manufacturing method and phase shift photomask having dummy gate patterns Download PDFInfo
- Publication number
- US7776514B2 US7776514B2 US11/374,009 US37400906A US7776514B2 US 7776514 B2 US7776514 B2 US 7776514B2 US 37400906 A US37400906 A US 37400906A US 7776514 B2 US7776514 B2 US 7776514B2
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- US
- United States
- Prior art keywords
- gate patterns
- dummy gate
- photoresist layer
- patterns
- gate
- Prior art date
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
- G03F1/70—Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/26—Phase shift masks [PSM]; PSM blanks; Preparation thereof
Abstract
Description
-
- A. A method for forming a plurality of gate patterns in parallel with each other on a photoresist layer within one circuit block, comprising:
- forming extension gate patterns on both ends of said gate patterns and said dummy gate pattern reaching an edge of said circuit block; and
- performing a first photolithography process upon said photoresist layer by using a phase shift photomask having first and second openings whose difference in phase is π, said first and second openings alternating between said gate patterns including said extension gate patterns to form phase edges therein.
- B. The method as set forth in claim A, further comprising performing a second photolithography process upon said photoresist layer by using a trim photomask having trim openings corresponding to said said extension gate patterns to remove a portion of said photoresist layer corresponding to said extension gate patterns, after said first photolithography process is performed.
- C. A method for manufacturing a semiconductor device having a plurality of gate patterns in parallel with each other within one circuit block, comprising:
- forming extension gate patterns on both ends of said gate patterns and said dummy gate pattern reaching an edge of said circuit block;
- performing a first photolithography process upon a photoresist layer within said circuit block by using a phase shift photomask having first and second openings whose difference in phase is π, said first and second openings alternating between said gate patterns including said extension gate patterns to form phase edges therein;
- performing a second photolithography process upon said photoresist layer by using a trim photomask having at least one trim opening corresponding to said extension gate patterns to remove a portion of said photoresist layer corresponding to said extension gate patterns, after said first photolithography process is performed; and
- performing an etching process upon a conductive layer by using said photoresist layer subjected to said first and second photolithography processes as a mask.
- D. A method for manufacturing a semiconductor device having a plurality of gate patterns in parallel with each other within one circuit block, comprising:
- forming extension gate patterns on both ends of said gate patterns and said dummy gate pattern reaching an edge of said circuit block,
- performing a first photolithography process upon a first photoresist layer within said circuit block by using a phase shift photomask having first and second openings whose difference in phase is π, said first and second openings alternating between said gate patterns including said extension gate patterns to form phase edges therein;
- performing a first etching process upon a conductive layer by using said first photoresist layer subjected to said first photolithography process as a mask;
- removing said first photoresist layer and coating a second photoresist layer on said conductive layer after said first etching process is performed;
- performing a second photolithography process upon said second photoresist layer by using a trim photomask having at least one trim opening corresponding to said extension gate patterns to remove a portion of said photoresist layer corresponding to said extension gate patterns; and
- performing a second etching process upon said conductive layer by using said second photoresist layer subjected to said second photolithography process as a mask.
- E. A phase shift photomask for a plurality of gate patterns in parallel with each other within one circuit block, comprising:
- a light screen section corresponding to said gate patterns and extension gate patterns on both ends of said gate patterns reaching an edge of said circuit block; and
- first and second opening sections whose difference in phase is π, said first and second opening sections alternating between said gate patterns including extension gate patterns to form phase edges therein.
- A. A method for forming a plurality of gate patterns in parallel with each other on a photoresist layer within one circuit block, comprising:
1.3≦MAX/MIN≦1.7 (1)
1.3≦MAX/MIN≦1.4 (2)
0.9·λ/NA≦MAX≦1.3·λ/NA (3)
0.9·λ/NA≦MAX≦1.0·λ/NA (4)
Claims (16)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/801,424 US8192919B2 (en) | 2005-03-17 | 2010-06-08 | Pattern forming method, semiconductor device manufacturing method and phase shift photomask having dummy gate patterns |
US13/484,966 US8617797B2 (en) | 2005-03-17 | 2012-05-31 | Pattern forming method, semiconductor device manufacturing method and phase shift photomask having dummy gate patterns |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005078125A JP4598575B2 (en) | 2005-03-17 | 2005-03-17 | Pattern formation method, semiconductor device manufacturing method, phase shift mask, and phase shift mask design method |
JP2005-078125 | 2005-03-17 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/801,424 Continuation US8192919B2 (en) | 2005-03-17 | 2010-06-08 | Pattern forming method, semiconductor device manufacturing method and phase shift photomask having dummy gate patterns |
Publications (2)
Publication Number | Publication Date |
---|---|
US20060210889A1 US20060210889A1 (en) | 2006-09-21 |
US7776514B2 true US7776514B2 (en) | 2010-08-17 |
Family
ID=37010751
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/374,009 Active 2027-12-11 US7776514B2 (en) | 2005-03-17 | 2006-03-14 | Pattern forming method, semiconductor device manufacturing method and phase shift photomask having dummy gate patterns |
US12/801,424 Expired - Fee Related US8192919B2 (en) | 2005-03-17 | 2010-06-08 | Pattern forming method, semiconductor device manufacturing method and phase shift photomask having dummy gate patterns |
US13/484,966 Active US8617797B2 (en) | 2005-03-17 | 2012-05-31 | Pattern forming method, semiconductor device manufacturing method and phase shift photomask having dummy gate patterns |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/801,424 Expired - Fee Related US8192919B2 (en) | 2005-03-17 | 2010-06-08 | Pattern forming method, semiconductor device manufacturing method and phase shift photomask having dummy gate patterns |
US13/484,966 Active US8617797B2 (en) | 2005-03-17 | 2012-05-31 | Pattern forming method, semiconductor device manufacturing method and phase shift photomask having dummy gate patterns |
Country Status (2)
Country | Link |
---|---|
US (3) | US7776514B2 (en) |
JP (1) | JP4598575B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100255423A1 (en) * | 2005-03-17 | 2010-10-07 | Nec Electronics Corporation | Pattern forming method, semiconductor device manufacturing method and phase shift photomask having dummy gate patterns |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100881130B1 (en) * | 2007-05-28 | 2009-02-02 | 주식회사 하이닉스반도체 | Method of forming gate patterns for peripheral circuitry and semiconductor device formed thereby |
US7984393B2 (en) * | 2007-11-14 | 2011-07-19 | Texas Instruments Incorporated | System and method for making photomasks |
Citations (5)
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JPS5762052A (en) | 1980-09-30 | 1982-04-14 | Nippon Kogaku Kk <Nikon> | Original plate to be projected for use in transmission |
JP2003168640A (en) | 2001-12-03 | 2003-06-13 | Hitachi Ltd | Method of manufacturing semiconductor device |
US6660462B1 (en) * | 1998-10-08 | 2003-12-09 | Hitachi, Ltd. | Semiconductor device and method of producing the same |
US20050164129A1 (en) * | 2003-02-27 | 2005-07-28 | Fujitsu Limited | Photomask and manufacturing method of semiconductor device |
US20050202321A1 (en) * | 2004-03-10 | 2005-09-15 | International Business Machines Corporation | Pliant sraf for improved performance and manufacturability |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5379233A (en) * | 1991-07-19 | 1995-01-03 | Lsi Logic Corporation | Method and structure for improving patterning design for processing |
JP3255476B2 (en) * | 1993-02-09 | 2002-02-12 | 三菱電機株式会社 | Circuit pattern |
US5573890A (en) * | 1994-07-18 | 1996-11-12 | Advanced Micro Devices, Inc. | Method of optical lithography using phase shift masking |
US5472814A (en) * | 1994-11-17 | 1995-12-05 | International Business Machines Corporation | Orthogonally separated phase shifted and unphase shifted mask patterns for image improvement |
JP3495869B2 (en) * | 1997-01-07 | 2004-02-09 | 株式会社東芝 | Method for manufacturing semiconductor device |
JP2000066372A (en) * | 1998-08-17 | 2000-03-03 | Seiko Epson Corp | Production of semiconductor device |
JP2001100390A (en) * | 1999-09-27 | 2001-04-13 | Toshiba Microelectronics Corp | Method for correcting pattern of mask for exposure |
TW512424B (en) * | 2000-05-01 | 2002-12-01 | Asml Masktools Bv | Hybrid phase-shift mask |
JP2002324743A (en) * | 2001-04-24 | 2002-11-08 | Canon Inc | Exposing method and equipment thereof |
JP2003017390A (en) * | 2001-06-29 | 2003-01-17 | Toshiba Corp | Pattern forming method and mask used for pattern formation |
JP3957504B2 (en) * | 2001-12-21 | 2007-08-15 | Necエレクトロニクス株式会社 | Photomask and semiconductor device manufacturing method |
JP3938694B2 (en) * | 2002-01-17 | 2007-06-27 | Necエレクトロニクス株式会社 | Pattern formation method |
JP4342767B2 (en) * | 2002-04-23 | 2009-10-14 | 富士通マイクロエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
JP4540327B2 (en) * | 2003-11-06 | 2010-09-08 | ルネサスエレクトロニクス株式会社 | Photomask pattern forming method |
JP2005201967A (en) * | 2004-01-13 | 2005-07-28 | Nec Electronics Corp | Photomask and its design method |
JP4598575B2 (en) * | 2005-03-17 | 2010-12-15 | ルネサスエレクトロニクス株式会社 | Pattern formation method, semiconductor device manufacturing method, phase shift mask, and phase shift mask design method |
-
2005
- 2005-03-17 JP JP2005078125A patent/JP4598575B2/en active Active
-
2006
- 2006-03-14 US US11/374,009 patent/US7776514B2/en active Active
-
2010
- 2010-06-08 US US12/801,424 patent/US8192919B2/en not_active Expired - Fee Related
-
2012
- 2012-05-31 US US13/484,966 patent/US8617797B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5762052A (en) | 1980-09-30 | 1982-04-14 | Nippon Kogaku Kk <Nikon> | Original plate to be projected for use in transmission |
US6660462B1 (en) * | 1998-10-08 | 2003-12-09 | Hitachi, Ltd. | Semiconductor device and method of producing the same |
JP2003168640A (en) | 2001-12-03 | 2003-06-13 | Hitachi Ltd | Method of manufacturing semiconductor device |
US20050164129A1 (en) * | 2003-02-27 | 2005-07-28 | Fujitsu Limited | Photomask and manufacturing method of semiconductor device |
US20050202321A1 (en) * | 2004-03-10 | 2005-09-15 | International Business Machines Corporation | Pliant sraf for improved performance and manufacturability |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100255423A1 (en) * | 2005-03-17 | 2010-10-07 | Nec Electronics Corporation | Pattern forming method, semiconductor device manufacturing method and phase shift photomask having dummy gate patterns |
US8192919B2 (en) * | 2005-03-17 | 2012-06-05 | Renesas Electronics Corporation | Pattern forming method, semiconductor device manufacturing method and phase shift photomask having dummy gate patterns |
US8617797B2 (en) | 2005-03-17 | 2013-12-31 | Renesas Electronics Corporation | Pattern forming method, semiconductor device manufacturing method and phase shift photomask having dummy gate patterns |
Also Published As
Publication number | Publication date |
---|---|
JP4598575B2 (en) | 2010-12-15 |
US8192919B2 (en) | 2012-06-05 |
US8617797B2 (en) | 2013-12-31 |
JP2006259381A (en) | 2006-09-28 |
US20120237879A1 (en) | 2012-09-20 |
US20060210889A1 (en) | 2006-09-21 |
US20100255423A1 (en) | 2010-10-07 |
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