US7657233B2 - Device for calculating FSM bits in the UMTS standard - Google Patents

Device for calculating FSM bits in the UMTS standard Download PDF

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US7657233B2
US7657233B2 US10/511,528 US51152805A US7657233B2 US 7657233 B2 US7657233 B2 US 7657233B2 US 51152805 A US51152805 A US 51152805A US 7657233 B2 US7657233 B2 US 7657233B2
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fsm
channel impulse
phasor
impulse responses
inputs
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US20060154614A1 (en
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Burkhard Becker
Christian Drewes
Jürgen Niederholz
Manfred Zimmermann
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Infineon Technologies AG
Intel Corp
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
    • H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
    • H04B7/06—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
    • H04B7/0613—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission
    • H04B7/0615—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission of weighted versions of same signal
    • H04B7/0619—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission of weighted versions of same signal using feedback from receiving side
    • H04B7/0621—Feedback content
    • H04B7/0634—Antenna weights or vector/matrix coefficients
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
    • H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
    • H04B7/06—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
    • H04B7/0613—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission
    • H04B7/0615—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission of weighted versions of same signal
    • H04B7/0619—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission of weighted versions of same signal using feedback from receiving side
    • H04B7/0636—Feedback format

Definitions

  • the invention relates to a device with the aid of which it is possible to calculate the FSM bits that determine the antenna weightings of a base station; particularly in the UMTS standard.
  • a fixed phase relationship is set up between the two transmission channels, which are to be assigned in each case to one of the antennas of the base station.
  • a so-called CLTD (Closed Loop Mode Transmit Diversity) function can be used to influence the relationship of the signals emitted by two antennas in order thereby to achieve constructive interference of the two transmission channels.
  • the CLTD function can be operated in a mode 1 and a mode 2.
  • the phase of one of the two antennas can be varied in mode 1.
  • the phase of the other antenna remains fixed.
  • the overall result is to vary the phase relationship between the two antennas.
  • mode 2 provides a variation in the amplitudes of the signals emitted from the antennas.
  • the amplitudes of both antennas can be varied in mode 2.
  • the CLTD function is described in the 3GPP TS 25.214 UMTS specification. This specification is referenced repeatedly below. All data refer in this case to the V4.2.0 (2001-09) version.
  • FSM Field Signalling Message
  • the channel impulse responses of both channels are always used in this case for an FSM data word.
  • the FSM data words include information specific to the base station and relating to the optimum phase relationship and, if appropriate, relating to the optimum amplitudes of the signals to be emitted from the two antennas.
  • the antenna weightings w 1 and w 2 that are applied to the signals which are to be emitted from the two antennas are formed in the base station from an FSM data word.
  • the antenna weightings w 1 and w 2 are selected with the aim of maximizing per slot the energy received by the mobile radio terminal while taking account of the weight quantization prescribed in the UMTS standard. This is equivalent to maximizing a proportionality factor P that is given by the following equation:
  • the indices 1 and 2 relate to two antennas i of a base station m.
  • ⁇ right arrow over (h) ⁇ m,i are complex (N m ⁇ 1) vectors that stand for the channel impulse responses estimated by the channel estimator with a channel depth N m .
  • the boundary conditions for the value ranges of the antenna weightings w 1 and w 2 are to be observed in this process.
  • w 1 1 2 ( 8 )
  • w 2 1 2 ⁇ e j ⁇ ⁇ ⁇ 2 ( 9 ) ⁇ 2 ⁇ ⁇ 0 , ⁇ 2 , ⁇ , - ⁇ 2 ⁇ ( 10 )
  • w 1 E 1 ( 11 )
  • w 2 E 2 ⁇ e j ⁇ ⁇ ⁇ 2 ( 12 )
  • E 1 + E 2 1 ( 14 ) ⁇ 2 ⁇ ⁇ 0 , ⁇ 4 , ⁇ 2 , 3 ⁇ ⁇ 4 , ⁇ , - ⁇ 4 , - ⁇ 2 , - 3 ⁇ ⁇ 4 ⁇ ( 15 )
  • Mode 2 is described in more detail in section 7.3 of the 3GPP TS 25.214 V4.2.0 UMTS specification.
  • the digital signal processor generates on the output side an FSM data word which consists of FSM bits and includes information relating to the optimum values for the phase angle ⁇ 2 (s) and, if appropriate, for the amplitudes E 1 (s) and E 2 (s).
  • a corresponding method for calculating the FSM bits is also to be specified.
  • the device according to the invention serves for calculating FSM bits by means of which the signals sent from two antennas of a base station are influenced with reference to their phase difference and/or their amplitudes.
  • the FSM bits are calculated with the aid of two estimated channel impulse responses.
  • a channel impulse response is related in each case to the channel belonging to one of the antennas.
  • the latter can carry out the required calculations substantially more efficiently than a digital signal processor. Furthermore, the device according to the invention is more favorable in terms of outlay than a digital signal processor.
  • the device advantageously has inputs, control inputs and an output. Components of the two channel impulse responses are applied to the inputs, and control signals are applied to the control inputs. This permits the device to calculate the FSM bit as a function of the components of the two channel impulse responses and the control signals.
  • the FSM bit can be tapped at the output of the device.
  • a preferred refinement of the invention provides that the device includes a logic unit and a processing unit that is connected downstream of the logic unit.
  • the logic unit preferably has an equal number of inputs and outputs.
  • the components of the two channel impulse responses are present at the inputs of the logic unit.
  • the inputs of the logic unit are connected to the outputs of the logic unit as a function of at least one control signal.
  • a multiplier stage, an adder, a weighting stage, an accumulator and a threshold value decision unit are arranged in series in the processing unit.
  • the multiplier stage includes two multipliers that in each case multiply by one another two values supplied by the logic unit.
  • the inputs of the multipliers are connected in each case to two outputs of the logic unit. The multiplication results for the two multipliers are added by the adder.
  • the sum formed by the adder is advantageously multiplied by a weighting factor in the weighting stage.
  • the weighting factor results from a control signal that is present at the weighting stage.
  • control signals are stored in the form of control bits in a read-only memory. This measure permits a calculating speed of the FSM bits that is higher by comparison with a digital signal processor.
  • the device according to the invention is, furthermore, designed with particular preference for the UMTS standard.
  • control signals are preferably a function both of the slot number of the FSM bit whose calculation is pending at this instant, and of the CLTD mode. Owing to this refinement, the device is designed with sufficient flexibility to be able to carry out different types of calculations for all combinations of slot number and CLTD mode.
  • the values of the control signals are a function of whether the slot number is an even or odd number.
  • the device according to the invention can be implemented with particular advantage in the associated mobile radio terminal.
  • FSM bits are calculated by means of the method according to the invention using two estimated channel impulse responses.
  • a complex phasor is produced from components of the two channel impulse responses.
  • this phasor is used to calculate an FSM bit by means of rotation, projection and, in particular, a threshold value decision.
  • the method according to the invention is distinguished by a particularly efficient and quick calculation of the FSM bit.
  • FIG. 1 shows a schematic block diagram of an exemplary embodiment of the device according to the invention
  • FIG. 2 shows a diagram of the mode of operation of the device according to the invention in the plane of complex numbers for mode 1;
  • FIG. 3 shows a diagram of the mode of operation of the device according to the invention in the plane of complex numbers for mode 2.
  • a circuit 1 is illustrated in FIG. 1 as an exemplary embodiment for the device according to the invention.
  • the circuit 1 comprises logic units 2 and 3 , multipliers 4 and 5 , an adder 6 , a weighting unit 7 , an accumulator 8 and a threshold value decision unit 9 .
  • the logic unit 2 has inputs In 1 , In 2 , In 3 and In 4 , configuration inputs Config 1 and Config 2 and outputs Out 1 , Out 2 , Out 3 and Out 4 .
  • the inputs In 1 , In 2 , In 3 and In 4 of the logic unit 2 are simultaneously inputs of the circuit 1 .
  • the logic unit 3 has inputs In 5 and In 6 , configuration inputs Config 3 , Config 4 and Config 5 and outputs Out 5 and Out 6 .
  • the multipliers 4 and 5 and the adder 6 each have two inputs and one output.
  • the weighting unit 7 , the accumulator 8 and the threshold value decision unit 9 respectively comprise an input and an output. Furthermore, the weighting unit 7 includes a configuration input Config 6 .
  • the output of the threshold value decision unit 9 constitutes the output of the circuit 1 .
  • the output Out 3 of the logic unit 2 is connected to the input In 5 of the logic unit 3 .
  • the output Out 4 of the logic unit 2 is connected to the input In 6 of the logic unit 3 .
  • One input of the multiplier 4 is coupled to the output Out 1 of the logic unit 2 .
  • the second input of the multiplier 4 is coupled to the output Out 5 of the logic unit 3 .
  • the outputs of the multipliers 4 and 5 feed the inputs of the adder 6 .
  • Connected downstream of the adder 6 are the weighting unit 7 , the accumulator 8 and the threshold value decision unit 9 in the prescribed sequence.
  • the circuit 1 is integrated in this case in a mobile radio terminal operating in accordance with the UMTS standard, and serves for generating FSM bits.
  • the FSM bits are subsequently transmitted to the associated base station in which antenna weightings are produced from the FSM bits.
  • the real and imaginary parts of the channel coefficients h 1,n and h 2,n are present at the inputs In 1 , In 2 , In 3 and In 4 of the circuit 1 .
  • the configuration bits C 1,k (s), C 2,k (s), . . . , C 6,k (s) are present at the configuration inputs Config 1 , Config 2 , . . . , Config 6 .
  • the slot index s runs from 1 to 15.
  • the path index n and the clock index k are in the ratio 1:2. This means that a channel coefficient h i,n is present two system clocks for processing on the circuit 1 .
  • the mode of operation of the circuit 1 is as follows.
  • the logic units 2 and 3 connect their inputs In 1 , . . . , In 6 to their outputs Out 1 , . . . , Out 6 as a function of the configuration bits C 1,k (s), . . . , C 5,k (s).
  • This produces a complex number a k +jb k at the outputs Out 1 and Out 2 , a complex number c k +jd k at the outputs Out 3 and Out 4 , and a complex number e k +jf k at the outputs Out 5 and Out 6 .
  • the multipliers 4 and 5 produce real numbers A k and B k , respectively, the adder 6 produces a real number S k , and the weighting unit 7 produces a real number R k as a function of the configuration bit C 6,k (s).
  • the accumulator 8 accumulates over twice the channel depth 2N, and produces a variable X(s) on the output side.
  • the configuration bit C 3,k (s) decides on the assignment of the outputs Out 5 and Out 6 of the logic unit 3 to the inputs In 5 and In 6 .
  • the input In 6 is applied to the output Out 6 .
  • the input In 6 is applied to the output Out 5 .
  • the configuration bit C 6,k (s) decides on the weighting that is applied to the number S k in the weighting unit 7 .
  • a value “X” in Table 1 for one of the conguration bits C 1,k (s), . . . , C 6,k (s) means that the block is not clocked and therefore does not produce a new output.
  • Table 2 which is set forth below and forms a relationship between the combination of CLTD mode and slot index s with the row numbers of Table 1.
  • FSM (s ⁇ 2) FSM (s ⁇ 1) No. from Table 1 0 0 7 0 1 8 1 0 6 1 1 5
  • one FSM data word consists of an FSM bit FSM(s), and in mode 2 it consists of four FSM bits FSM(s). Consequently, in mode 1 with progressive slot index s Nos. 1 and 2 from Table 1 are used alternately for configuring circuit 1 .
  • rows Nos. 3, 4, 5 to 8 and 9 are selected on the basis of the four FSM bits FSM(s) of the FSM data word with a periodicity of 4 with reference to the slot index s.
  • the entries in Tables 1 and 2 are preferably stored in a read-only memory and therefore need not be calculated during processing.
  • an FSM bit FSM(s) can be reduced to merely considering one or two elements Hij of the matrix from equation (3).
  • the elements Hij are subjected to the same processing in order to calculate an FSM bit FSM(s). This processing consists essentially of rotations and projections.
  • the matrix element H 21
  • e j ⁇ H 21 is considered for CLTD mode/slot combinations in which the FSM bit FSM(s) pronounces on the phase angle ⁇ 2 .
  • the matrix elements H 11 and H 22 are considered for CLTD mode/slot combinations in which the FSM bit FSM(s) pronounces on the moduli of the antenna weightings w 1 and w 2 .
  • the amplitudes E 1 (s) and E 2 (s) can assume only two values, this requires only that the difference
  • the specific processing operations for different CLTD mode/slot combinations differ from one another, in particular, in the rotation of the complex phasor, given by the matrix element H 21 , in the plane of complex numbers, and in its projection onto the real or imaginary axis.
  • the respective processing operation is controlled by means of the configuration bits C 1,k (s), . . . , C 6,k (s).
  • the 9 possible processing cases of circuit 1 are listed in Table 1.
  • Section 7.2 of the 3GPP TS 25.214 V4.2.0 UMTS specification stipulates that during normal operation of the CLTD function in mode 1, that is to say outwith an initialization or a so-called compressed mode, it is necessary to evaluate for an even slot index s whether the complex phasor H 21 in FIG. 2 lies in the bright complex half plane, that is to say in the 1 st or 4 th quadrant, or in the dark complex half plane, that is to say in the 2 nd or 3 rd quadrant.
  • the circuit 1 is to be described in the normal operating mode of the CLTD function in mode 2, that is to say outwith a so-called end of frame adjustment, an initialization or a compressed mode. It is described below how the four FSM bits FSM(s) of the FSM data word are obtained for a phasor H 21 with
  • Im ⁇ H 21 (s) ⁇ e j ⁇ /8 /cos( ⁇ /8) ⁇ specifying the variable X(s) is positive or negative.
  • This term clearly specifies that the phasor H 21 is rotated counterclockwise by the angle ⁇ /8 in the plane of complex numbers because of the multiplication by the factor e j ⁇ /8 , is stretched by the factor 1/cos( ⁇ /8), and is subsequently projected onto the imaginary axis.
  • An investigation is thereupon conducted as to whether this projection lies on the positive or the negative half straight line of the imaginary axis.
  • the rotation by the angle ⁇ /8 or ⁇ /8 is taken into account in the circuit 1 by using the weightings 1 and tan( ⁇ /8) in the weighting unit 7 .
  • the phasor H 21 is stretched by the factor 1/cos( ⁇ /8), but this is not significant for the statement relating to the angle.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Mobile Radio Communication Systems (AREA)
US10/511,528 2002-04-22 2003-03-28 Device for calculating FSM bits in the UMTS standard Expired - Fee Related US7657233B2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE10217853A DE10217853A1 (de) 2002-04-22 2002-04-22 Vorrichtung zur Berechnung von FSM-Bits im UMTS-Standard
DE10217853.4 2002-04-22
DE10217853 2002-04-22
PCT/DE2003/001036 WO2003090377A1 (de) 2002-04-22 2003-03-28 Vorrichtung zur berechnung von fsm-bits im umts-standard

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EP (1) EP1497930B1 (de)
DE (2) DE10217853A1 (de)
WO (1) WO2003090377A1 (de)

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US20110305284A1 (en) * 2010-06-10 2011-12-15 Infineon Technologies Ag Method for Transmitting a Data Signal in a MIMO System

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110305284A1 (en) * 2010-06-10 2011-12-15 Infineon Technologies Ag Method for Transmitting a Data Signal in a MIMO System
US8401105B2 (en) * 2010-06-10 2013-03-19 Intel Mobile Communications GmbH Method for transmitting a data signal in a MIMO system
US8885753B2 (en) 2010-06-10 2014-11-11 Intel Mobile Communications GmbH Method for transmitting a data signal in a MIMO system
US9397739B2 (en) 2010-06-10 2016-07-19 Intel Deutschland Gmbh Method for transmitting a data signal in a MIMO system

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US20060154614A1 (en) 2006-07-13
WO2003090377A1 (de) 2003-10-30
EP1497930B1 (de) 2008-05-07
DE10217853A1 (de) 2003-11-13
EP1497930A1 (de) 2005-01-19
DE50309782D1 (de) 2008-06-19

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