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US7638842B2 - Lattice-mismatched semiconductor structures on insulators - Google Patents

Lattice-mismatched semiconductor structures on insulators Download PDF

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US7638842B2
US7638842B2 US11220482 US22048205A US7638842B2 US 7638842 B2 US7638842 B2 US 7638842B2 US 11220482 US11220482 US 11220482 US 22048205 A US22048205 A US 22048205A US 7638842 B2 US7638842 B2 US 7638842B2
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insulator
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US20070054465A1 (en )
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Matthew T. Currie
Anthony J. Lochtefeld
Zhiyuan Cheng
Thomas A. Langdo
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Taiwan Semiconductor Manufacturing Co (TSMC) Ltd
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AmberWave Systems Corp
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    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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Abstract

Monolithic lattice-mismatched semiconductor heterostructures are fabricated by bonding patterned substrates with alternative active-area materials formed thereon to a rigid dielectric platform and then removing the highly-defective interface areas along with the underlying substrates to produce alternative active-area regions disposed over the insulator and substantially exhausted of misfit and threading dislocations.

Description

FIELD OF THE INVENTION

This invention relates generally to lattice-mismatched semiconductor heterostructures and, specifically, to methods and materials for formation of integrated structures including alternative active-area materials on insulators.

BACKGROUND OF THE INVENTION

The increasing operating speeds and computing power of microelectronic devices have recently given rise to the need for an increase in the complexity and functionality of the semiconductor structures from which these devices are fabricated. Hetero-integration of dissimilar semiconductor materials, for example, III-V materials, such as gallium arsenide, gallium nitride, indium aluminum arsenide, and/or germanium with silicon, silicon-on-insulator, or silicon-germanium substrates, is an attractive path for increasing the functionality and performance of the CMOS platform. Specifically, as geometric scaling of Si-based MOSFET technology becomes more challenging, the heterointegration of alternative area materials becomes an attractive option for increasing the innate carrier mobility of MOSFET channels. For many applications, it is desirable to incorporate alternative active-area materials having a low density of dislocation defects onto an insulator platform. As used herein, the term “alternative materials” refers to either a non-silicon semiconductor, or silicon with a different surface or rotational orientation compared to the underlying substrate. Such areas are suitable for use as active areas for MOSFETs or other electronic or opto-electronic devices.

Heterointegration of alternative materials has thus far been typically limited to the addition of SiGe alloys of small Ge content for use as source-drain contact materials or heterojunction bipolar transistor base layers. Since such layers are only slightly lattice-mismatched to Si, and since most modern Si MOSFET processes are compatible with these dilute SiGe alloys, few disruptions in the Si MOSFET integration sequence have been necessary. The drive for increased carrier mobility—and concomitant device drive current—will soon, however, necessitate the use of other, more highly lattice-mismatched materials for historically Si-based devices, requiring more disruptive changes to the traditional device integration flow.

In particular, heteroepitaxial growth can be used to fabricate many modern semiconductor devices where lattice-matched substrates are not commercially available or to potentially achieve monolithic integration with silicon microelectronics. Performance and, ultimately, the utility of devices fabricated using a combination of dissimilar semiconductor materials, however, depends on the quality of the resulting structure. Specifically, a low level of dislocation defects is important in a wide variety of semiconductor devices and processes, because dislocation defects partition an otherwise monolithic crystal structure and introduce unwanted and abrupt changes in electrical and optical properties. These, in turn, result in poor material quality and limited performance. In addition, the threading dislocation segments can degrade physical properties of the device material and can lead to a premature device failure.

As mentioned above, dislocation defects typically arise in efforts to epitaxially grow one kind of crystalline material on a substrate of a different kind of material—often referred to as a “heterostructure”—due to different crystalline lattice sizes of the two materials. This lattice mismatch between the starting substrate and subsequent layer(s) creates stress during material deposition that generates dislocation defects in the semiconductor structure. The stress field associated with misfit dislocations under certain conditions may cause formation of linear agglomerations of threading dislocations, termed a “dislocation pile-up.” This is generally defined as an area comprising at least three threading dislocations, with a threading dislocation density greater than 5×106 cm−2, and with threading dislocations substantially aligned along a slip direction such that the linear density of dislocations within the pile-up and along a slip direction is greater than 2000/cm. For example, the slip directions in SiGe materials are in-plane <110> directions. A high localized threading dislocation density present in dislocation pile-ups has a potentially devastating impact on the yield of devices formed in these regions and may render these devices unusable. Inhibiting the formation of dislocation pile-ups is, therefore, desirable.

To minimize formation of dislocations and associated performance issues, as mentioned above, many semiconductor heterostructure devices known in the art have been limited to semiconductor layers that have very closely—e.g. within 0.1%—lattice-matched crystal structures. In such devices a thin layer is epitaxially grown on a mildly lattice-mismatched substrate. As long as the thickness of the epitaxial layer is kept below a critical thickness for defect formation, the substrate acts as a template for growth of the epitaxial layer, which elastically conforms to the substrate template. While lattice-matching and near-matching eliminate dislocations in a number of structures, there are relatively few lattice-matched systems with large energy band offsets, limiting the design options for new devices.

Accordingly, there is considerable interest in heterostructure devices involving greater epitaxial layer thickness and greater lattice misfit than known approaches would allow. One known technique termed “epitaxial necking” was demonstrated in connection with fabricating a Ge-on-Si heterostructure by Langdo et al. in “High Quality Ge on Si by Epitaxial Necking,” Applied Physics Letters, Vol. 76, No. 25, Apr. 2000. This approach offers process simplicity by utilizing a combination of selective epitaxial growth and defect crystallography to force defects to the sidewall of the opening in the patterning mask, without relying on increased lateral growth rates. This approach, however, generally requires relatively thick semiconductor layers, as well as relatively small lateral dimensions of the openings in the mask in order for the dislocations to terminate at its sidewalls, resulting in defect-free regions.

Several methods to fabricate non-Si semiconductors on insulator substrates have been previously reported, whereby transfer of SiGe material onto insulator substrate was achieved through bonding and splitting induced by hydrogen implantation and annealing. Generally, in these approaches, a relatively thick SiGe layer is deposited on a silicon substrate, which includes a graded SiGe buffer layer and a relaxed SiGe layer having a constant germanium concentration. Following surface planarization, hydrogen is implanted into the SiGe layer to facilitate wafer splitting. The Si/SiGe wafer is then bonded to an oxidized silicon substrate. The SiGe-on-oxide layers are separated from the rest of the couplet by thermal annealing, wherein splitting occurs along hydrogen-implantation-induced microcracks, which parallel the bonding interface.

A technique to form a SiGe-free strained silicon-on-insulator substrates has been also reported by T. A. Langdo and others in “Preparation of Novel SiGe-Free Strained Si on Insulator Substrates,” published in 2002 IEEE International SOI Conference Proceedings (Oct. 2002). This technique is similar to approaches described above, except that a thin layer of epitaxial silicon is deposited on the SiGe layer before wafer bonding. After bonding and wafer splitting, the SiGe layer is removed by oxidation and HF etching, enabling the formation of very thin and uniform strained silicon-on-oxide surface.

Thus, there is a need in the art for versatile and efficient methods of fabricating semiconductor heterostructures, including alternative active-area materials disposed over a common insulator platform, that would address formation of interface defects in a variety of lattice-mismatched materials systems. There is also a need in the art for semiconductor devices utilizing a combination of integrated lattice-mismatched materials with reduced levels of substrate interface defects for improved functionality and performance.

SUMMARY OF THE INVENTION

Heterointegration of alternative materials is desirable for various electronic and optoelectronic applications. For example, the heterointegration of III-V, II-VI materials and/or Ge with Si is an attractive path for increasing the functionality and performance of the CMOS platform. An economical solution to heterointegration could enable new fields and applications, such as replacing Si in CMOS transistors, particularly for critical-path logic devices. Heterointegration could significantly lower (a) channel resistance, due to the ultra-high mobility and saturation velocity afforded by various non-Si semiconductors, and (b) source/drain resistance, due both to high mobility and to the narrower bandgap of many non-Si semiconductors, with the narrower bandgap leading to a lower electrical resistance between the metal (or metal-alloy) contact and the semiconductor. Another new application could be the combination of Si CMOS logic with ultra-high speed RF devices, such as InP- or GaAs-based high electron-mobility transistor (HEMT) or heterojunction bipolar transistor (HBT) devices similar to those utilized for high-frequency applications today. Yet another application may be the combination of Si CMOS logic with opto-electronic devices, since many non-Si semiconductors have light emission and detection performance superior to Si.

Selective epitaxy is an attractive path for hetero-materials integration for several reasons. First, it facilitates adding the non-Si semiconductor material only where it is needed, and so is only marginally disruptive to a Si CMOS process performed on the same wafer. Also, selective epitaxy may allow multiple new materials to be combined on a common wafer, e.g., Ge for PMOS and InGaAs for NMOS. Furthermore, it is likely to be more economical than key alternative paths, e.g., layer transfer of global hetero-epitaxial films, especially for integrating materials with large lattice mismatch. In order to achieve integration of lattice-mismatched materials on an insulator, selective epitaxy can be supplemented by techniques employing ion implantation and bonding.

Accordingly, it is an object of the present invention to provide on-insulator semiconductor heterostructures with significantly minimized dislocation defects, and methods for their fabrication employing selective epitaxy and bonding.

As mentioned above, dislocation defects typically arise during epitaxial growth of one kind of crystal material on a substrate of a different kind of material due to differences in crystalline lattice sizes. This lattice mismatch between the starting substrate and subsequent layer(s) creates stress during material deposition that generates dislocation defects in the semiconductor structure. One known technique to control threading dislocation densities (“TDD”) in highly-mismatched epitaxial layers involves substrate patterning, which exploits the fact that the threading dislocations are constrained by geometry (i.e. that a dislocation cannot end in a crystal). If the free edge is brought closer to another free edge by patterning the substrate into growth areas, then it is possible to generally confine threading dislocations to a portion of the epitaxial layer proximate to its interface with the starting substrate, thereby minimizing the TDD in the remainder of the epitaxial layer.

Generally, in its various embodiments, the invention disclosed herein focuses on bonding patterned substrates with alternative active-area materials epitaxially formed thereon to a rigid platform, such as, for example, an insulator disposed over a handle wafer, and then removing the highly-defective interface areas along with the underlying substrates to produce alternative active-area regions disposed over the insulator and substantially exhausted of misfit and threading dislocations. As a result, the invention contemplates fabrication of semiconductor devices based on monolithic lattice-mismatched heterostructures on insulators long sought in the art but heretofore impractical due to dislocation defects.

In general, in one aspect, the invention disclosed herein features methods for forming a structure, including providing a first substrate including, or consisting essentially of, a first crystalline semiconductor material. A first insulator layer is formed over the first substrate, and at least one opening is defined in the first insulator layer extending to the first substrate. The opening is filled, at least partially, with an active-area material by, for example, selective epitaxy to form an active-area region surrounded by an insulator region. The method further includes forming a cleave area at a predetermined distance in relation to the interface between the first substrate and the active-area regions by, for example, implanting gaseous material into the active-area and the insulator regions. The active-area and the insulator regions are then bonded to a rigid platform, for example, a structure including a second insulator layer disposed over a second substrate including, or consisting essentially of, a second crystalline semiconductor material. The method further includes causing the bonded structure to split at least along the cleave area into a first portion and a second portion, the second portion including at least a portion of the active-area region bonded to the second insulator layer.

In various embodiments, the split within the bonded structure is caused by thermal annealing, e.g. at a temperature ranging from about 350° C. to 700° C. Optionally, a surface of the active-area region is planarized prior to implantation and bonding such that its surface is substantially coplanar with a surface of the insulator region. Also, following the split, an exposed surface of the second portion can be planarized to remove cleave-induced surface roughness and, if desired, reduce a thickness of the active-area region in the second portion to a desired value. In some embodiments, the second portion is annealed after the split at a temperature ranging from about 600° C. to about 900° C.

In some embodiments, the cleave area at least partially lies within the active-area and the insulator regions substantially parallel to the interface between the first substrate and the active-area region at a first predetermined distance therefrom, such that, following the split, the first portion includes portions of the active-area and the insulator regions disposed over the first substrate. In some implementations of these embodiments, a strained region is formed within the active-area region, such that the cleave area at least partially includes the strained region. In other embodiments, the cleave area at least partially lies within the first substrate substantially parallel to the interface between the first substrate and the active-area region at a second predetermined distance therefrom, such that, after causing the bonded structure to split into the first portion and the second portion, the second portion of the bonded structure includes a portion of the first substrate. Optionally, the remaining first crystalline semiconductor material is removed from the active-area and the insulator regions by post-annealing planarization and/or etching. In yet another embodiment of this aspect of the invention, the active-area material is epitaxially grown over the first substrate in a bottom portion of the opening, and then a third insulator layer is deposited in a top portion of the opening over the active-area material. The surface of the third insulator layer can be planarized prior to implantation and bonding such that the surface is substantially coplanar with a surface of the insulator region. In still other embodiments, the cleave area substantially coincides with or is proximate to the interface between the active-area material and the first substrate, such that the cleave area at least partially includes the interface between the first substrate and the active-area region.

Optionally, a strained semiconductor layer is deposited over the surface of the active-area region. Also, in some embodiments, prior to implantation and bonding, a dielectric material is deposited over the active-area material in the opening to form a buffer region above the active-area region. A surface of the buffer region extends at least to a surface of the first insulator layer. The surface of the buffer region is or can be made co-planar with the surface of the first insulator layer.

In this and other aspects of the invention, the rigid platform may include one or more layers of glass, quartz, plastic, polymer, or other dielectric material, either self-supporting or disposed over another layer. For example, the rigid platform can be a substrate including a second insulator layer disposed over a second substrate including, or consisting essentially of, a second crystalline semiconductor material. The first semiconductor and/or second semiconductor materials include, or consist essentially of, single-crystal silicon, germanium, a silicon-germanium alloy, and/or a III-V material. The first and second substrates may be, for example, a bulk silicon wafer, a bulk germanium wafer, a bulk III-V wafer such as gallium arsenide or indium phosphide, a semiconductor-on-insulator (SOI) substrate, or a strained semiconductor-on-insulator (SSOI) substrate. Also, the first and second insulator layers may include, or consist essentially of, silicon dioxide, aluminum oxide, silicon nitride, silicon carbide, and/or diamond, and may have a thickness of, e.g., 50-1000 nanometers. The third insulator layer can include, or consist essentially of, either the same material as the first and second insulator layers, or include a different material, such as, for example, a low-K dielectric material. Generally, the active-area material is a crystalline semiconductor material, such as a group IV element or compound, a III-V compound, and/or a II-VI compound. The group IV element may be carbon, germanium, and/or silicon, e.g., (110) silicon. The group IV compound may include silicon, germanium, tin, and/or carbon, e.g., silicon germanium (SiGe). The III-V compound may be, e.g., gallium arsenide (GaAs), indium arsenide (InAs), indium gallium arsenide (InGaAs), indium phosphide (InP), or indium antimonide (InSb), gallium nitride (GaN), and/or indium nitride (InN). The II-VI compound may be, e.g., zinc telluride (ZnTe), cadmium selenide (CdSe), cadmium telluride (CdTe), zinc sulfide (ZnS), and/or zinc selenide (ZnSe). Also, the first crystalline semiconductor material may have a first crystalline orientation and the active-area material comprises a third crystalline semiconductor material having a second crystalline orientation different from the first crystalline orientation. For example, the first crystalline semiconductor material may be (100) silicon and the active-area material may be (110) silicon. The gaseous material may include ions of hydrogen, helium, argon, krypton, and/or neon.

In general, in another aspect, the invention relates to a semiconductor structure that includes a substrate and, thereover, a patterned insulator layer defining at least one opening. The substrate can be a rigid platform that includes one or more layers of glass, quartz, plastic, polymer, or other dielectric material, either self-supporting or disposed over another layer, for example, including, or consisting essentially of, a crystalline semiconductor material. The structure further includes an active-area region formed in the opening and bonded to the substrate. The active-area region includes, or consists essentially of, an active-area material substantially exhausted of misfit and threading dislocations.

Various embodiments of this and other aspects of the invention include one or more of the following features. The substrate may include a base insulator layer disposed over the crystalline semiconductor material underneath the patterned insulator layer. The active-area region may have a buffer region that includes, or consists essentially of, a dielectric material and is disposed in the opening between the substrate and the active-area material. The active-area region may also have a strained semiconductor layer disposed over the active-area material. A dislocation pile-up density in the active-area material does not exceed about 1/cm, for example, is less than about 0.01/cm. Also, a threading dislocation density in the active-area material does not exceed about 103 cm−2, for example, is less than about 102 cm−2.

In general, in other aspects, one or more electronic devices, such as, for example, a field-effect transistor (FET), such as a complementary metal-oxide-semiconductor FET (CMOSFET) or a metal-semiconductor FET (MESFET), or a non-FET device such as a diode, are defined including at least a portion of one or more of the active-area regions.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, like reference characters generally refer to the same parts throughout the different views. Also, the drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments of the present invention are described with reference to the following drawings, in which FIGS. 1A-1D, 2A-2C, 3A-3D, 4A-4B, and 5A-5C depict schematic cross-sectional side views illustrating formation of semiconductor structures including alternative active-area materials, and FIG. 6A-6B depict schematic cross-sectional side views of electronic devices fabricated over the semiconductor structures formed as illustrated in the preceding figures.

DETAILED DESCRIPTION

In accordance with its various embodiments, the invention disclosed herein contemplates fabrication of monolithic lattice-mismatched semiconductor heterostructures disposed over an insulator platform with limited-area regions substantially exhausted of misfit and threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.

Referring to FIGS. 1A-1C, planar isolation regions may be utilized for the selective epitaxy of active-area materials. In one embodiment, a substrate 100 includes a crystalline semiconductor material. The substrate may be, for example, a bulk silicon wafer, a bulk germanium wafer, a bulk III-V wafer such as gallium arsenide or indium phosphide, a SOI substrate, or a SSOI substrate. An insulator layer 110 is formed over the substrate, as shown in FIG. 1A. The insulator layer may be, for example, silicon dioxide, aluminum oxide, silicon nitride, silicon carbide, or diamond, and may have a thickness of, e.g., 50-1000 nanometers (nm). The insulator layer may be formed by a deposition method, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD).

A mask (not shown), such as a photoresist mask, is formed over the insulator layer 110. The mask is patterned to expose at least a portion of the insulator layer. The exposed portion of the insulator layer is removed by, e.g., reactive ion etching (RIE), to define openings 120A and 120B and expose areas 130A and 130B of a top surface of the substrate 100, as shown in FIG. 1B. Each of the openings may have a width of, e.g., 50 nm-10 micrometers (μm) and a length of, e.g., 50 nm-10 μm. The height of the openings equals the thickness of the insulator layer. The openings correspond to the active areas of electronic or opto-electronic device(s) and the dimensions are selected accordingly.

Referring to FIGS. 1B-1C, in some embodiments, the openings 120A and 120B are filled with active-area materials by selective epitaxy, thereby forming active-area regions 140A and 140B surrounded by insulator regions of the insulator layer 110. Selective epitaxy may be performed by a deposition method such as atomic layer deposition (ALD) or CVD, for example, PECVD, LPCVD, ultra-high vacuum CVD, reduced-pressure CVD, or metalorganic CVD. Various deposition methods for forming active-area regions 140A and 140B may utilize techniques described in co-pending provisional application Ser. No. 60/681,940, incorporated herein by reference.

In many embodiments of the invention, the active-area regions 140A and 140B are formed selectively, i.e., the materials are deposited over the areas 130A, 130B of the crystalline semiconductor material of substrate 100 exposed by the openings, but are not substantially deposited or formed on the insulator layer 110. The active-area materials are crystalline semiconductor material, such as a group IV element or compound, a III-V compound, or a II-VI compound. The group IV element may be carbon, germanium, or silicon, e.g., (110) silicon. The group IV compound may include silicon, germanium, tin, or carbon, e.g., SiGe. The III-V compound may be, e.g., GaAs, InAs, InGaAs, InP, InSb, GaN, InN, or mixtures thereof. The II-VI compound may be, e.g., ZnTe, CdSe, CdTe, ZnS, and/or ZnSe. The active-area regions 140A and 140B may include, or consist essentially of, the same or different materials. Also, in some embodiments, one or more of the active-area regions may include, or consist essentially of, silicon. The lattice mismatch (or difference in equilibrium lattice constants) between the active-area materials and the crystalline semiconductor material of substrate 100 may, in some embodiments, exceed approximately 4%. In a particular embodiment, the lattice mismatch between the active-area materials and the crystalline semiconductor material of substrate is greater than approximately 8%. The density of misfit dislocations, which typically form as the active-area material relaxes to its equilibrium lattice constant and are present near the interface between the active-area material and the substrate, can exceed 1×106 cm−2, even exceeding 2×106 cm−2 or 4×106 cm−2 in some embodiments. These misfit dislocation defects are linear defects generally lying parallel to the interface and generally confined to a thin region near the interface.

Referring to FIG. 1C, after the openings 120A and 120B are filled with the active-area materials, portions 150A and 150B of the active-area materials may extend above a top surface 160 of the insulator layer 110 for various reasons, thereby forming a non-planar top surface. For instance, facets may form at a vertical interface between the semiconductor active area material and the insulator. Even without facets, a top surface of the active-area regions 140A and 140B may not be co-planar with a top surface of the insulator material, because of the difficulty of stopping the selective epitaxy precisely at the point that the openings are filled with the active-area materials. A non-planar surface may present subsequent processing difficulties, for example, compromise bondability of the active-area regions. Referring now to FIG. 1D, to address these potential difficulties, the portions 150A, 150B of the active area regions extending above the top surface of the insulator layer may be removed by, for example, planarization, so that surface 170 of the active-area regions is substantially coplanar with the top surface of the insulator layer. The active area material surface may be planarized by, for example, a chemical-mechanical polishing (CMP) step that is selective with respect to the insulator layer.

Referring now to FIG. 2A, in various embodiments, gaseous species 205 are introduced into the active-area regions 140A and 140B and the regions of the insulator layer 110 surrounding the active-area regions by, for example, ion implantation. The gaseous species may include, or consist essentially of, ions of hydrogen, helium, argon, krypton, and/or neon. In a particular embodiment, the gaseous species consist essentially of H+ ions. Implantation of the gaseous species is controlled such that the species penetrate the active-area and the insulator regions, forming a narrow cleave area 210 at a predetermined distance from the coplanar top surfaces 160, 170 of these regions. In one embodiment, the cleave area lies within the active-area and the insulator regions at a distance D1 above and substantially parallel to the interface between the substrate 100 and the active-area regions. The insulator regions may have smaller cross-sectional areas than the active-area regions 140A and 140B, and thus the cleaving behavior of the insulator regions will be substantially similar to that of the active-area regions. Additionally, after the split induced along the cleave area discussed in detail below, the insulator regions may function as isolation regions, e.g., shallow trench isolation regions, for devices subsequently formed in the active-area regions. The thickness of the cleave area depends on the parameters of the ion implantation, and, in many embodiments, is carefully controlled such that the cleave area is about 10-50% of the thickness of insulator layer 110. For example, for a thickness of insulator layer 110 of about 100 nm, the cleave area can be approximately 10-50 nm thick. In some embodiments, the implantation of the gaseous species to form cleave area 210 can be replaced or supplemented by another method of introducing gaseous species, such as diffusion or plasma-assisted gasification, e.g., plasma hydrogenation. As skilled artisans will appreciate, dislocation defects induced by the lattice mismatch between the crystalline semiconductor material of the substrate and the active-area material are generally concentrated in the active-area region proximate to the interface with the substrate. The heights of these highly-defective zones 220A, 220B of the active-area regions above the interface with the substrate 100 depends on, e.g., the degree of lattice mismatch between the materials, as well as epitaxial deposition conditions. By selecting the distance D1 to exceed the height of highly-defective zones 220A, 220B, portions 230A, 230B of the active-area region above the cleave area are substantially exhausted of misfit and threading dislocations. In one embodiment, portions 230A, 230B have a TDD at least three orders of magnitude lower than a TDD in the cleave area and/or highly-defective zones 220A, 220B. In another embodiment, portions 230A, 230B have a TDD at least five orders of magnitude lower than a TDD in the cleave area and/or the highly-defective zones. As skilled artisans readily appreciate, reduction in dislocation density of a semiconductor structure reduces leakage currents that contribute to the off-state current of a device formed thereon. Thus, as used herein, the active-area region being “substantially exhausted of misfit and threading dislocations” refers either to a complete absence of dislocations in this region or to the level thereof being sufficiently low so as not to meaningfully affect the performance of electronic device(s) at least partially incorporating this region. For example, in various embodiments of the invention, the off-state current of these devices is less than about 106 A/μm, preferably, less than about 10−8 A/μm, and more preferably 10−10 A/μm.

Referring to FIG. 2B, following ion implantation, top surfaces 160 and 170 of the active-area and the insulator regions are bonded to a surface 240 of an insulator layer 250 disposed over a semiconductor substrate 260 utilizing methods known in the art, e.g. as described in U.S. Pat. No. 6,602,613, incorporated herein by reference, thereby forming a structure 270. In one embodiment, to facilitate bonding, the surface 240 of the insulator layer and/or top surfaces 160, 170 is cleaned by a wet chemical cleaning process, e.g. by a hydrophilic surface preparation process. A suitable cleaning procedure for the prebonding surface preparation employs a modified megasonic RCA SC1 clean that includes application of a cleaning mixture including ammonium hydroxide, hydrogen peroxide, and water (NH4OH:H2O2:H2O) at a ratio of 1:4:20 at 60° C. for 10 minutes, followed by a deionized (DI) water rinse and spin dry. The wafer-bonding energy should be strong enough to sustain the subsequent layer transfer, as discussed below. In some embodiments, to increase the bond strength, top surfaces 160, 170 and/or the surface 240 of the insulator layer 250 are plasma-treated, either before, after, or instead of a wet clean. The plasma environment may include at least one of the following species: oxygen, ammonia, argon, nitrogen, diborane, and phosphine. After an appropriate cleaning step, top surfaces 160, 170 and the surface 240 are bonded together by bringing them in contact with each other at room temperature. The bond strength may be greater than 1000 mJ/m2, achieved at a low temperature, such as, for example, less than 600° C. As skilled artisans will readily appreciate, bonding of top surfaces 160, 170 of the active-area and the insulator regions with the surface 240 of the insulator layer 250 generally requires that the root mean square surface roughness of these surfaces not exceed about 1 nm. Accordingly, in many embodiments, to improve bondability, the surfaces are planarized by CMP. In various embodiments, the insulator layer includes, or consists essentially of, silicon dioxide, aluminum oxide, silicon nitride, silicon carbide, or diamond, and may have a thickness of, e.g., 50-1000 nanometers (nm). The semiconductor substrate 260 may be, for example, a bulk silicon wafer, a bulk germanium wafer, a bulk III-V wafer such as gallium arsenide or indium phosphide, or a SOI substrate. In some embodiments, as mentioned above, semiconductor substrate 260 and insulator layer 250 may be replaced by another type of rigid platform, including but not limited to self-supporting substrates including or consisting essentially of glass, quartz, plastic, polymer, or any of the dielectrics discussed above in reference to insulator layer 250. The lattice mismatch between the active-area materials and the crystalline semiconductor material of substrate 260 may exceed approximately 4%. In a particular embodiment, the lattice mismatch between the active-area materials and the crystalline semiconductor material of substrate 260 exceeds approximately 8%.

In some embodiments, a top insulator layer (not shown) may be formed over the top surfaces 160, 170 of the active-area and insulator regions, resulting in insulator-on-insulator bonding. This top insulator layer may include, or consist essentially of, silicon dioxide, aluminum oxide, silicon nitride, silicon carbide, or diamond, and may have a thickness of, e.g., 50-1000 nm. In certain implementations of these embodiments, the top insulator layer is bonded directly to the substrate 260, without providing the insulator layer 250 therebetween.

In various embodiments, the structure 270 is then subjected to thermal annealing at a temperature ranging from about 350° C. to 700° C. for a period of time from about five minutes to about four hours. Referring to FIG. 2C, the thermal annealing induces a split in the structure 270 along the cleave area 210, separating the substrate 100 with portions of the insulator layer 110, and the active-area regions 140A, 140B having thickness D1 thereon from the portions 230A, 230B of the active-area regions surrounded by the insulator regions and bonded to the insulator layer 250. In some embodiments, a mechanical force and/or a jet of gas or liquid may be applied to the structure 270 in addition to or instead of the thermal annealing to induce the split. Following the split, in many embodiments, exposed surfaces 280 of the active-area regions are planarized or smoothed, e.g. using CMP, to remove cleave-induced surface roughness and, if desired, reduce a thickness of the active-area regions to a desired value. In various embodiments, a root mean square surface roughness of the surface 280 does not exceed about 1 nm. Thus, alternative active-area regions 230A and 230B disposed over the common insulator are obtained.

As mentioned above, in various embodiments of the invention, the alternative active-area regions 230A and 230B are substantially exhausted of misfit and threading dislocations. Defect densities can be measured using a standard chromic acid-based Schimmel etch as outlined, for example, in Journal of the Electrochemical Society 126:479 (1979), and an optical microscope operated in differential interference contrast (Nomarski) mode. TDDs can be calculated by counting the number of etch pits per unit area located away from dislocation pile-ups, yielding units of inverse area (cm−2). Dislocation pile-up densities can be calculated by measuring the total length of dislocation pile-ups per unit area, yielding units of inverse length (cm−1). Defect densities may also preferably be confirmed by the use of a complementary characterization technique such as plan-view transmission electron microscopy. In various embodiments, a dislocation pile-up density in these active-area regions does not exceed about 20/cm, for example, is less than about 5/cm, preferably ranges from 0 to about 1/cm, and, more preferably, is less than about 0.01/cm. Also, TDD in these regions is less than about 105 cm−2, for example, less than about 103 cm−2, and, preferably, ranges between 0 and about 102 cm−2.

In some embodiments, the structure 270 is further annealed at a temperature ranging from 600-900° C., e.g., at a temperature greater than about 800° C., to strengthen the bond between the surfaces 160, 170 and the surface 240.

Referring now to FIGS. 3A-3D, in an alternative embodiment, co-planar active-area regions 340A and 340B and the regions of the insulator layer 310 surrounding the active-area regions are formed over the substrate 300 as described above in connection with FIGS. 1A-1C. Gaseous species 305, e.g. including, or consisting essentially of, ions of hydrogen, helium, argon, krypton, and/or neon, are introduced into the active-area and the insulator regions by, for example, ion implantation. In contrast with the embodiments described in connection with FIGS. 2A-2C, however, implantation of the gaseous species is controlled such that the species penetrate the substrate 300 through the active-area and the insulator regions, forming a narrow cleave area 325 at a predetermined distance D2 below the interface between the substrate and the active-area regions. The distance D2 may range, for example, from about 10 nm to about 1000 nm. As a result, the cleave area is disposed within a homogeneous zone of the crystalline material of the substrate 300. Following bonding and thermal annealing steps described above, the structure 370 is split along the cleave area 325, separating the substrate from a portion 375 thereof having the thickness D2 (and disposed over the active-area regions surrounded by the insulator regions) and bonded to an insulator layer 380, which itself, in turn, is disposed over a semiconductor substrate 390. As with the embodiments described above, the substrate 390 may be, for example, a bulk silicon wafer, a bulk germanium wafer, a bulk III-V wafer such as gallium arsenide or indium phosphide, or a SOI substrate. Then, the portion 375 of the substrate, as well as portions of the active-area and insulator regions disposed thereon, are removed by, for example, CMP to eliminate a highly-defective region proximate to the interface between the substrate and the active-area regions, as well as to obtain a desired thickness of the active-area regions. As a result, alternative active-area regions 330A and 330B disposed over the common insulator and substantially exhausted of misfit and threading dislocations are obtained. In many embodiments, a TDD of the alternative active-area regions is at least three (and, preferably, at least five) orders of magnitude lower than that present in the removed portion of the active-area material. In particular, in various embodiments, a dislocation pile-up density in these active-area regions does not exceed about 20/cm, for example, is less than about 1/cm, or, preferably, ranges from 0 to about 1/cm, and, more preferably, is less than about 0.01/cm. Also, TDD in these regions is less than about 105 cm−2, for example, less than about 103 cm−2, and, preferably, ranges from 0 to about 102 cm−2.

Referring to FIGS. 4A-4B, in other alternative embodiments, co-planar active-area regions 440A and 440B and the regions of the insulator layer 410 surrounding the active-area regions are formed over the substrate 400, as described above in connection with FIGS. 1A-1C. Gaseous species 405, e.g. including, or consisting essentially of, ions of hydrogen, helium, argon, krypton, and/or neon, are introduced into the active-area and the insulator regions by, for example, ion implantation. In contrast with the embodiments described in connection with FIGS. 2A-2C, however, in one embodiment, implantation of the gaseous species is controlled such that the species penetrate through the active-area and the insulator regions to an interface 430 between the substrate and the active-area regions, forming a narrow cleave area 425 that substantially coincides with the interface, as shown in FIG. 4A. Following bonding and thermal annealing steps described above, the resulting structure is split along the cleave area, separating the substrate from the active-area regions surrounded by the insulator regions and bonded to an insulator layer, which itself, in turn, is disposed over a semiconductor substrate. In one embodiment, in order to promote formation of the narrow cleave area 425 substantially coincident with the interface 430, a mild thermal anneal is performed after implantation of gaseous species 405. This anneal promotes diffusion of gaseous species 405 to interface 430 and any crystalline defects that may be present there. The anneal may be performed at, for example, 100-300° C. for a period of 1-30 minutes.

Referring now to FIG. 4B, in another embodiment, strained layers 435A and 435B are formed within the active-area regions during epitaxial deposition. For example, a layer of a semiconductor material that is lattice-mismatched to the active-area material can be selectively deposited over a portion of the active-area material to a thickness below the critical thickness of such lattice-mismatched material, and then the rest of the active-area material is deposited over the lattice-mismatched material. Preferably, the strained layer is tensilely, rather than compressively, strained to better accommodate implanted ions within its crystalline lattice. Implantation of the gaseous species is controlled such that the species penetrate through the active-area and the insulator regions to the strained layers, forming a narrow cleave area 425 that substantially coincides with the strained layers in the active-area regions. Following bonding and thermal annealing steps described above, the resulting structure is split along the cleave area, separating the substrate from a portion thereof disposed over the active-area regions surrounded by the insulator regions and bonded to an insulator layer, which itself, in turn, is disposed over a semiconductor substrate.

Following the split, exposed surfaces of the active-area regions can be planarized or smoothed, e.g. using CMP, to remove cleave-induced surface roughness and, if desired, reduce a thickness of the active-area regions to a desired value. As a result, alternative active-area regions disposed over the insulator and substantially exhausted of misfit and threading dislocations are obtained. Notably, in these embodiments, employing the interface area between the substrate and the active-area regions or the deliberately-introduced strained layer as a target height for the cleave area improves control over penetration of the implanted ions and associated thickness of the active-area regions. Also, because of the high concentration of dislocation defects in the interface area and the strained layer, a lesser concentration of implanted ions and/or a more efficient (e.g., lower) thermal budget is needed to effect cleave-induced split within the bonded structure. In addition, any portion of strained layers 435A, 435B remaining after splitting and planarization may be used in subsequently formed devices, as, for example, transistor channel regions with enhanced mobility.

Referring to FIGS. 5A-5C, in certain implementations of the embodiments described above with reference to FIGS. 1B-1C, the epitaxially deposited active area material(s) only partially fill openings 520A and 520B defined in an insulator layer 510 and extending to the substrate 500. Thus, top surfaces of active-area regions 540A and 540B do not reach to the top surface 560 of the insulator layer. The remaining space in the openings can be left empty, or, as shown in FIG. 5B, filled with a dielectric material forming buffer regions 550A and 550B over the active-area regions. The dielectric material may be deposited over the entire surface of active-area regions 540A, 540B and top surface 560 of the insulator layer. The structure may then be planarized such that any dielectric material formed over top surface 560 of the insulator layer is removed, and the dielectric material remains only over active-area regions 540A, 540B. Should any dielectric material remain over top surface 560 of the insulator layer, it will at least be co-planar with a top surface of buffer regions 550A, 550B. The dielectric material may include, or consist essentially of, silicon dioxide, aluminum oxide, silicon nitride, and/or silicon carbide, and can be the same material used for the insulator layer 510, or a different material. In some embodiments, the dielectric material is a low-K dielectric with a lower dielectric constant than that of silicon dioxide; such materials are particularly suitable for subsequent manufacturing of FDSOI devices. The dielectric material can be deposited, such as by CVD or ALD, or spun on from a solution. Suitable thicknesses for the dielectric material range from 10 to 200 nm. Examples of suitable low-K dielectrics include silsequioxane-based polycyclic oligomers or polymers such as hydroxyl silsequioxane (HSQ) or methyl silsequioxane (MSQ); Black Diamond, available from Applied Materials, Inc. of Santa Clara, Calif.; CORAL, available from Novellus Systems Inc. of San Jose, Calif.; other organosilicate glasses or carbon doped oxides (SiCOH); SiLK, available from Dow Chemical Co. of Midland, Mich.; benzocyclobutene (BCB); porous silica; polymer foams; and GX-3, HOSP, and NANOGLASS, available from Honeywell International Inc. of Sunnyvale, Calif.

Still referring to FIG. 5B, following deposition of the dielectric material in the openings 520A and 520B, top surface 565 of the dielectric buffer regions is optionally planarized for improved bondability. Then, with reference to FIG. 5C, the steps of forming a cleave area by ion implantation, bonding, and annealing with optional post-annealing planarization of the active-area regions are performed in a manner similar to that described above in connection with FIGS. 2A-2C, 3A-3D, and 4A-4B, forming the active-area regions of desired thickness disposed over the dielectric regions 550. The dielectric buffer regions are bonded to a handle wafer 570, including a semiconductor substrate 590 having an optional insulating layer 580 thereover. Thus, in the implementations described with reference to FIGS. 5A-5C, a final thickness of the active-area regions is established prior to the bonding steps. Also, in some versions, having dielectric buffer regions of the active-area regions generally facilitates bondability to the insulator layer 590.

In many applications, various electronic devices can be formed in the on-insulator portions of the active-area regions. Referring to FIG. 6A, in some embodiments, active area regions 640A, 640B are formed over a common insulator layer 680 disposed over a semiconductor wafer 690, as described above in connection with FIGS. 2A-2C, 3A-3C, or 4A-4B. Then, an n-MOS transistor 615A and a p-MOS transistor 615B are formed, having source regions 618A, 618B, drain regions 620A, 620B, and channel regions 622A, 622B disposed in the active-area material(s). The insulator regions 610 function as isolation regions, e.g., shallow trench isolation regions, for transistor 615A, 615B.

Additional semiconductor layers may be formed above the active areas on the insulator. For example, referring to FIG. 6B, in some embodiments, thin strained semiconductor layers 645A, 645B are formed atop the active areas and can be subsequently used as channels for transistors. In one embodiment, the layers 645A, 645B are tensilely strained and formed of silicon. In this embodiment, these layers may be formed in a dedicated chamber of a deposition tool that is not exposed to the source gases for the epitaxial growth of the active-area material, thereby avoiding cross-contamination and improving the quality of the interface between the strained layers and the active-area regions. Furthermore, strained layers 645A, 645B may be formed from one or more isotopically pure precursors. Isotopically pure materials have better thermal conductivity than conventional materials consisting of mixtures of different isotopes. Higher thermal conductivity may help dissipate heat from devices subsequently formed on these strained layers, thereby maintaining the enhanced carrier mobilities these layers provide. In other embodiments, the strained layers may be formed of SiGe, or at least one group II, group III, group V, and/or group VI element. In various embodiments, the strained layers have a thickness of, for example, 50-500 Å, preferably below 300 Å.

Further processing steps may include the formation of gate dielectric layers 635A, 635B, the deposition of gate electrode materials 625A, 625B, and the definition of gates by, e.g., dry etching, such that spacers 642A, 642B are formed adjacent to the gate dielectric and gate electrode layers. The source and drain regions may be defined by an ion implantation step. Interlayer dielectrics may be formed over gate, source, and drain, and contact holes may be defined. Metal layers may be deposited in the contact holes and over the structure. In some embodiments, the interlayer dielectrics, for example, including or consisting essentially of, silicon nitride, are used to induce strain on at least one of channel regions 622A, 622B.

Suitable methods for fabrication of CMOS devices, e.g. those having different n- and p-active areas, are described in co-pending provisional application Ser. No. 60/702,363, incorporated herein by reference. The resulting transistors may be, for example, a field-effect transistor (FET), such as a complementary metal-oxide-semiconductor FET (CMOSFET) or a metal-semiconductor FET (MESFET). In an alternative embodiment, the device is a non-FET device such as a diode. The diode device could be a light detecting device (photodiode), or a light emitting device (either a light-emitting diode, or a laser diode). In an alternative application, the device is a bipolar junction transistor.

Other embodiments incorporating the concepts disclosed herein may be used without departing from the spirit of the essential characteristics of the invention or the scope thereof. The foregoing embodiments are therefore to be considered in all respects as only illustrative rather than restrictive of the invention described herein. Therefore, it is intended that the scope of the invention be only limited by the following claims.

Claims (41)

1. A semiconductor device structure comprising:
a substrate comprising a base insulator layer disposed over a base semiconductor layer comprising a first crystalline semiconductor material;
a patterned insulator layer disposed over the substrate, the patterned insulator layer defining a first opening and a second opening exposing portions of the base insulator layer;
a first active-area region formed in the first opening, the first active-area region comprising a first active-area material having a threading dislocation density less than approximately 105 cm−2 and disposed over and in contact with the base insulator layer;
a second active-area region formed in the second opening, the second active-area region comprising a second active-area material having a threading dislocation density less than approximately 105 cm−2 and disposed over and in contact with the base insulator layer;
a p-type metal-oxide-semiconductor (PMOS) transistor disposed over and including at least a portion of the first active-area region, the PMOS transistor including:
a first gate dielectric region disposed over the first active-area region,
a first gate disposed over the first gate dielectric region, the first gate comprising a first conducting layer,
a first source and a first drain regions formed in the first active-area region proximate the first gate dielectric region, the first source and first drain region including p-type dopants; and
an n-type metal-oxide-semiconductor (NMOS) transistor disposed over and including at least a portion of the second active-area region, the NMOS transistor including:
a second gate dielectric region disposed over the second active-area region,
a second gate disposed over the second gate dielectric region, the second gate comprising a second conducting layer,
a second source and a second drain regions formed in the second active-area region proximate the second gate dielectric region, the second source and second drain including n-type dopants,
wherein both the first active-area material and the second active-area material are different from the first crystalline semiconductor material, and the first active-area material is different from the second active-area material.
2. The structure of claim 1 further comprising a strained semiconductor layer disposed over at least one of the first active-area material or the second active-area material.
3. The structure of claim 1 wherein the first active area-material and the second active-area material are substantially free of misfit dislocations.
4. The structure of claim 1 wherein the first active-area material and the second active-area material are substantially free of threading dislocations.
5. The structure of claim 1 wherein the first active-area material is substantially relaxed to its equilibrium lattice constant and the second active-area material is substantially relaxed to its equilibrium lattice constant.
6. The structure of claim 1 wherein the first crystalline semiconductor material comprises silicon, the first active-area material comprises germanium, and the second active-area material comprises a III-V compound.
7. The structure of claim 6 wherein the first crystalline semiconductor material consists essentially of silicon, the first active-area material consists essentially of germanium, and the second active-area material consists essentially of the III-V compound.
8. The structure of claim 1 wherein, during operation, an off-state current of the PMOS transistor and an off-state current of the NMOS transistor are both less than about 10−8 A/μm.
9. The structure of claim 1 wherein a lattice mismatch between the first active-area material and the first crystalline semiconductor material and a lattice mismatch between the second active-area material and the first crystalline semiconductor material both exceed approximately 4%.
10. The structure of claim 9 wherein the lattice mismatch between the first active-area material and the first crystalline semiconductor material and the lattice mismatch between the second active-area material and the first crystalline semiconductor material both exceed approximately 8%.
11. The structure of claim 1 further comprising a strained semiconductor layer disposed between the first active-area material and the first gate dielectric region.
12. The structure of claim 1 further comprising a strained semiconductor layer disposed between the second active-area material and the second gate dielectric region.
13. The structure of claim 1 wherein a dislocation pile-up density of the first active-area material and a dislocation pile-up density of the second active-area material are both less than about 1/cm.
14. The structure of claim 1 wherein the base insulator layer consists essentially of at least one of silicon dioxide or silicon nitride.
15. A semiconductor structure comprising:
a substrate comprising a base insulator layer disposed over a base semiconductor layer comprising a first crystalline semiconductor material;
a patterned insulator layer disposed over and in direct contact with the base insulator layer, the patterned insulator layer defining a first opening and a second opening;
a first active-area region formed in the first opening and in contact with the substrate, the first active-area region comprising a first active-area material having a threading dislocation density less than approximately 105 cm−2; and
a second active-area region formed in the second opening and in contact with the substrate, the second active-area region comprising a second active-area material having a threading dislocation density less than approximately 105 cm−2,
wherein the first active-area material is different from the second active-area material, the first active-area material is disposed over and in contact with the base insulator layer, and the second active-area material is disposed over and in contact with the base insulator layer, the first crystalline semiconductor material comprises silicon, the first active-area material comprises germanium, and the second active-area material comprises a III-V compound.
16. The semiconductor structure of claim 15 further comprising:
a p-type metal-oxide-semiconductor transistor disposed over and including at least a portion of the first active-area region; and
an n-type metal-oxide-semiconductor transistor disposed over and including at least a portion of the second active-area region.
17. The structure of claim 16 wherein, during operation, an off-state current of the p-type metal-oxide-semiconductor transistor and an off-state current of the n-type metal-oxide-semiconductor transistor are both less than about 10−8 A/μm.
18. The structure of claim 15 wherein the first active area-material and the second active-area material are substantially free of misfit dislocations.
19. The structure of claim 15 wherein the first active-area material and the second active-area material are substantially free of threading dislocations.
20. The structure of claim 15 wherein the first active-area material is substantially relaxed to its equilibrium lattice constant and the second active-area material is substantially relaxed to its equilibrium lattice constant.
21. The structure of claim 15 wherein the first crystalline semiconductor material consists essentially of silicon, the first active-area material consists essentially of germanium, and the second active-area material consists essentially of the III-V compound.
22. The structure of claim 15 wherein a dislocation pile-up density of the first active-area material and a dislocation pile-up density of the second active-area material are both less than about 1/cm.
23. The structure of claim 15 wherein the base insulator layer consists essentially of at least one of silicon dioxide or silicon nitride.
24. The structure of claim 15, further comprising a strained semiconductor layer disposed over the first active-area material.
25. The structure of claim 24 further comprising a second strained semiconductor layer disposed over the second active-area material.
26. The structure of claim 15 further comprising a strained semiconductor layer disposed over the second active-area material.
27. A semiconductor structure comprising:
a substrate comprising a base insulator layer disposed over a base semiconductor layer comprising a first crystalline semiconductor material;
a patterned insulator layer disposed over and in direct contact with the base insulator layer, the patterned insulator layer defining a first opening and a second opening;
a first active-area region formed in the first opening and in contact with the substrate, the first active-area region comprising a first active-area material having a threading dislocation density less than approximately 105 cm−2;
a second active-area region formed in the second opening and in contact with the substrate, the second active-area region comprising a second active-area material having a threading dislocation density less than approximately 105 cm−2; and
a strained semiconductor layer disposed over the first active-area material,
wherein the first active-area material is different from the second active-area material, the first active-area material is disposed over and in contact with the base insulator layer, and the second active-area material is disposed over and in contact with the base insulator layer.
28. The semiconductor structure of claim 27 wherein both the first active-area material and the second active-area material are different from the first crystalline semiconductor material.
29. The structure of claim 27 wherein a lattice mismatch between the first active-area material and the first crystalline semiconductor material and a lattice mismatch between the second active-area material and the first crystalline semiconductor material both exceed approximately 4%.
30. The structure of claim 29 wherein the lattice mismatch between the first active-area material and the first crystalline semiconductor material and the lattice mismatch between the second active-area material and the first crystalline semiconductor material both exceed approximately 8%.
31. The structure of claim 27 further comprising a second strained semiconductor layer disposed over the second active-area material.
32. The structure of claim 27 further comprising:
a p-type metal-oxide-semiconductor transistor disposed over and including at least a portion of the first active-area region; and
an n-type metal-oxide-semiconductor transistor disposed over and including at least a portion of the second active-area region.
33. The structure of claim 32 wherein, during operation, an off-state current of the p-type metal-oxide-semiconductor transistor and an off-state current of the n-type metal-oxide-semiconductor transistor are both less than about 10−8 A/μm.
34. The structure of claim 32 wherein the first active area-material and the second active-area material are substantially free of misfit dislocations.
35. The structure of claim 32 wherein the first active-area material and the second active-area material are substantially free of threading dislocations.
36. The structure of claim 32 wherein the first active-area material is substantially relaxed to its equilibrium lattice constant and the second active-area material is substantially relaxed to its equilibrium lattice constant.
37. The structure of claim 32 wherein a dislocation pile-up density of the first active-area material and a dislocation pile-up density of the second active-area material are both less than about 1/cm.
38. The structure of claim 32 wherein the base insulator layer consists essentially of at least one of silicon dioxide or silicon nitride.
39. A semiconductor structure comprising;
a substrate comprising a base insulator layer disposed over a base semiconductor layer comprising a first crystalline semiconductor material;
a patterned insulator layer disposed over and in direct contact with the base insulator layer, the patterned insulator layer defining a first opening and a second opening;
a first active-area region formed in the first opening and in contact with the substrate, the first active-area region comprising a first active-area material having a threading dislocation density less than approximately 105 cm−2;
a second active-area region formed in the second opening and in contact with the substrate, the second active-area region comprising a second active-area material having a threading dislocation density less than approximately 105 cm−2; and
a strained semiconductor layer disposed over the second active-area material,
wherein the first active-area material is different from the second active-area material, the first active-area material is disposed over and in contact with the base insulator layer, and the second active-area material is disposed over and in contact with the base insulator layer.
40. The structure of claim 39 further comprising:
a p-type metal-oxide-semiconductor transistor disposed over and including at least a portion of the first active-area region; and
an n-type metal-oxide-semiconductor transistor disposed over and including at least a portion of the second active-area region.
41. The structure of claim 40 wherein, during operation, an off-state current of the p-type metal-oxide-semiconductor transistor and an off-state current of the n-type metal-oxide-semiconductor transistor are both less than about 10−8 A/μm.
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