US7615845B1 - Active shielding of conductors in MEMS devices - Google Patents
Active shielding of conductors in MEMS devices Download PDFInfo
- Publication number
- US7615845B1 US7615845B1 US12/146,144 US14614408A US7615845B1 US 7615845 B1 US7615845 B1 US 7615845B1 US 14614408 A US14614408 A US 14614408A US 7615845 B1 US7615845 B1 US 7615845B1
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- US
- United States
- Prior art keywords
- soi substrate
- embedded conductor
- conductor
- dielectric layer
- embedded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B3/00—Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
- B81B3/0064—Constitution or structural means for improving or controlling the physical properties of a device
- B81B3/0086—Electrical characteristics, e.g. reducing driving voltage, improving resistance to peak voltage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2207/00—Microstructural systems or auxiliary parts thereof
- B81B2207/07—Interconnects
Definitions
- the present invention relates to micro-electromechanical system (MEMS) devices, manufactured on a semiconductor substrate and including both mechanical and electrical structures.
- MEMS micro-electromechanical system
- the present invention relates to the reduction of parasitic capacitance that is present within such devices.
- MEMS devices for example pressure sensors, pump actuators and electrical or optical circuit elements, such as RF inductors, optical switches and resonators, to name but a few.
- MEMS devices use capacitive circuit elements to perform an intended function.
- the capacitive circuit elements of such MEMS device are connected by conductors to electronic circuits, which may be placed on the same substrate as the MEMS device, or on a separate integrated circuit. In either case, capacitance associated with the conductors will be present. This capacitance, which is often called parasitic capacitance, will be electrically in parallel with the capacitive circuit elements of the MEMS device.
- capacitive MEMS devices sometimes need to have signals routed via diffused conductors, instead of via metal conductors.
- An example might be when wafer-scale packaging is used, whereby a top wafer is bonded to the sensor wafer by one of several techniques, such as anodic bonding or direct silicon wafer bonding. Conductors are then required to cross the bonding area below the wafer surface, since a flat wafer surface without metal conductors is required for successful bonding.
- Another example would be conductors on thin membranes, where using a metal could cause hysteresis.
- the capacitance of the back-biased junction which is generally employed to isolate the conductor from the substrate, appears as parasitic capacitance in parallel with the sensing capacitance, impairing performance.
- MEMS devices which use resistive or inductive circuit elements to perform their intended function, may also have their performance impaired by the parasitic capacitance. This is because the parasitic capacitance causes reduced sensitivity, increased noise gain and/or reduced sensor bandwidth. It is therefore desirable to reduce the parasitic capacitance present in a MEMS device.
- the mechanical dimensions of the MEMS device are often determined by factors other than the electrical parameters, and this restricts the possibility to reduce conductor area.
- One example of particular relevance is the use of anodic bonding in MEMS devices. This technique requires a bonding area of a certain width, which must be crossed by conductors which carry electrical signals from the hermetically sealed MEMS device to outside electrical contacts.
- circuit topologies such as those provided on an electronic amplifier, can differ in their sensitivity to parasitic capacitance, and although several circuits have been suggested as being improvements in this respect, in many cases parasitic capacitance remains detrimental to system performance.
- an apparatus for reducing, in use, parasitic capacitance in a conductor in a micro-electro mechanical system (MEMS) device comprises: a silicon-on-insulator (SOI) substrate having a buried oxide layer; a dielectric layer formed on the surface of the SOI substrate; a conductor embedded in the SOI substrate and disposed between the dielectric layer and the buried oxide layer, the embedded conductor having a first end and a second end; one or more surface conductors deposited on top of the dielectric layer and in contact with the first end and second end of the embedded conductor, respectively; a boundary region surrounding the embedded conductor and separating an inner region and an outer region of SOI substrate, the boundary extending through the SOI substrate to the buried oxide layer and providing a p-n junction between the boundary region and the outer region of SOI substrate which is, in use, reverse biased to electrically isolate the inner region from the outer region of SOI substrate; and an amplifier having an input connected to the first end of the
- a method of reducing, in use, parasitic capacitance in a conductor in a micro-electro mechanical system (MEMS) device comprises: providing a silicon-on-insulator (SOI) substrate having a buried oxide layer; forming a dielectric layer on the surface of the SOI substrate; embedding a conductor in the SOI substrate, the embedded conductor being disposed between the dielectric layer and the buried oxide layer and having a first end and a second end; depositing one or more surface conductors on top of the dielectric layer, the surface conductors being in contact with the first end and second end of the embedded conductor, respectively; forming a boundary region, which surrounds the embedded conductor and separates an inner region and an outer region of SOI substrate, the boundary region extending through the SOI substrate to the oxide layer and providing a p-n junction between the boundary region and the outer region of SOI substrate, which is reverse biased, in use, to electrically isolate the inner region from the outer region
- SOI silicon-on-insulator
- the present invention provides an apparatus and method of reducing the parasitic capacitance in conductors used in MEMS devices, which are manufactured on silicon-on-insulator (SOI) substrates.
- SOI substrates are silicon substrates that have a buried layer of silicon oxide below the surface. This sort of substrate is often used for MEMS devices, as it aids in the processing of the micromechanical structures.
- the region surrounding the conductor can be electrically isolated from the rest of the silicon. It is then possible to bias this region to a voltage equal to, or very close to, the voltage of the conductor. The effect of this is that it reduces the charge on the parasitic capacitor and, to the surrounding circuits, it appears that the parasitic capacitance has been reduced.
- FIG. 1 is a cross-section of an example of a hermetically sealed MEMS device manufactured using a wafer bonding technique
- FIG. 2 is a cross-section showing a embedded conductor crossing a bonding area according to the present invention.
- FIG. 3 shows a top view of the bonding area and surrounding substrate of FIG. 2 .
- a micro-mechanical structure 5 is manufactured from a semiconductor substrate 2 , which may comprise silicon and may be doped.
- a bonding area 4 separates the micro-mechanical structure 5 from a bonding pad 3 .
- a wafer bonding technique such as anodic bonding
- a top wafer 1 is bonded to the silicon to form a hermetic cavity 6 about the micro-mechanical structure 5 .
- an electrical conductor (not shown) must cross the bonding area 4 .
- the method of bonding is not essential to the invention, although it is a requirement that a insulating (dielectric) layer (not shown) is present in the bonding area 4 .
- An insulating layer is present in most bonding technologies, and typically consists of glass or silicon oxide.
- FIG. 2 shows an example of a substrate having an embedded conductor 22 according to the present invention.
- a dielectric layer 25 which may be made of silicon oxide, is formed on the surface of a Silicon-on-Insulator (SOI) substrate 2 and a conductor 22 is embedded in the SOI substrate 2 .
- SOI Silicon-on-Insulator
- the conductor is embedded in the SOI substrate 2 underneath a bonding area 4 provided on the surface of the dielectric layer 25 , the bonding area 4 being located in between the ends of the embedded conductor 22 .
- a small area of dielectric layer 25 may be etched away at selected locations so that contacts can be formed with the SOI substrate 2 or the embedded conductor 22 . These openings in the dielectric layer 25 are generally called contact holes.
- a top wafer 1 is mounted onto the bonding area 4 of the SOI substrate 2 to create a hermetically sealed cavity 6 containing a MEMS structure (not shown) and hence separating the ends of the embedded conductor 22 .
- the top wafer 1 is preferably glass, although other suitable materials may also be used.
- Surface conductors 3 , 21 which are preferably metallic, are provided on the surface of the dielectric layer 25 for connecting to the ends of the embedded conductor 22 .
- a surface conductor 21 connects an end of the embedded conductor 22 to the MEMS structure sealed inside the cavity 6 .
- Another surface connector 3 connects to the other end of the embedded conductor 22 .
- the surface conductors 3 , 21 connect to the embedded conductor 22 via the contact holes formed in the dielectric layer 25 and are isolated from the rest of the SOI substrate 2 by the dielectric layer 25 .
- a signal may be carried across the embedded conductor 22 , in this example, underneath a bonding area 4 .
- the embedded conductor 22 is buried in the SOI substrate 2 , such as in the example shown in FIG. 2 , contact between the embedded conductor 22 and the surface conductors 3 , 21 (or other connection means) may be facilitated by the provision of contact diffusions 23 , which extend through the SOI substrate 2 from the ends of the embedded conductor 22 to the surface of the SOI substrate 2 where the contact holes are provided.
- the conductor 22 is embedded within the SOI substrate 2 , it should be recognized that the present invention could also be realized with a conductor located at the surface of the SOI substrate 2 , directly underneath and in physical contact with the dielectric layer 25 .
- the volumes of the embedded conductor 22 and contact diffusions 23 have the opposite doping polarity of the SOI substrate 2 , so that electrical isolation can be provided by reverse biasing of the p-n junction thus created.
- this p-n junction is also a source of parasitic capacitance.
- a diffusion boundary 31 which extends from the surface of the SOI substrate 2 down to a buried oxide layer 24 in the SOI substrate, surrounds the embedded conductor 22 and contact diffusions 23 , separating an inner region 2 a of SOI substrate 2 , which contains the embedded conductor 22 , and an outer region 2 b of SOI substrate 2 .
- a contact hole is provided through the dielectric layer 25 directly above a portion of the diffused boundary 31 that is not inside the sealed cavity 6 .
- the p-n junction that is created between the diffusion boundary 31 and the SOI substrate 2 can be reverse biased, thereby electrically isolating the inner region 2 a of the SOI substrate from the outer region 2 b of the SOI substrate 2 .
- An amplifier 32 can then be employed to sense the voltage of the embedded conductor 22 , preferably via the conductor 3 connected to the contact diffusion 23 .
- the amplifier 32 then reproduces this voltage, or a close approximation to it, at an output that is connected to the inner region 2 a of SOI substrate 2 .
- a contact hole is provided through the dielectric layer 25 to the surface of the SOI substrate 2 at a point inside the inner region 2 a and a substrate contact 35 is provided for the amplifier 32 output to connect to.
- the inner region 2 a of SOI substrate 2 can be biased to a voltage close to the voltage of the conductor 22 .
- the effect of this is that the charge on the parasitic capacitor is reduced and, to the surrounding circuits, it appears that the parasitic capacitance has been reduced. This effectively reduces the parasitic capacitance between the conductor 22 and the SOI substrate 2 .
- the location of the amplifier 32 is not essential to the present invention.
- it can be located on the same SOI substrate 2 as the MEMS structure 5 , or it can be placed off chip and connected via bonding pads (not shown).
- FIG. 3 shows a top schematic view of the present invention, where a diffusion boundary 31 surrounds the embedded contact 22 , thereby creating an inner region 2 a of SOI substrate 2 and an outer region 2 b of SOI substrate 2 . It can also be seen how a bias voltage 33 may be applied to the diffusion boundary 31 . Furthermore, it can be seen how the amplifier 32 has an input at the first end of the embedded conductor 22 and an output located on the inner region 2 a of SOI substrate 2 , in this example the output being connected via the substrate contact 35 .
- both the amplifier 32 and the bias voltage are connected to the inner region 2 a of the SOI substrate 2 and the diffusion boundary 31 at locations outside of the area that would be hermetically sealed by the bonding of a top wafer 1 onto a bonding area 4 of the SOI substrate 2 .
Abstract
Description
Claims (14)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/146,144 US7615845B1 (en) | 2008-06-25 | 2008-06-25 | Active shielding of conductors in MEMS devices |
DE102009030281A DE102009030281B4 (en) | 2008-06-25 | 2009-06-24 | Apparatus and method for actively shielding conductors in MEMS devices |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/146,144 US7615845B1 (en) | 2008-06-25 | 2008-06-25 | Active shielding of conductors in MEMS devices |
Publications (1)
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US7615845B1 true US7615845B1 (en) | 2009-11-10 |
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US12/146,144 Expired - Fee Related US7615845B1 (en) | 2008-06-25 | 2008-06-25 | Active shielding of conductors in MEMS devices |
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US (1) | US7615845B1 (en) |
DE (1) | DE102009030281B4 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8546240B2 (en) | 2011-11-11 | 2013-10-01 | International Business Machines Corporation | Methods of manufacturing integrated semiconductor devices with single crystalline beam |
US8629036B2 (en) | 2011-11-11 | 2014-01-14 | International Business Machines Corporation | Integrated semiconductor devices with amorphous silicon beam, methods of manufacture and design structure |
WO2014064273A1 (en) | 2012-10-26 | 2014-05-01 | Commissariat à l'énergie atomique et aux énergies alternatives | Connection network for nems, having an improved arrangement |
US20150035387A1 (en) * | 2013-07-31 | 2015-02-05 | Analog Devices Technology | Mems switch device and method of fabrication |
US9105751B2 (en) | 2011-11-11 | 2015-08-11 | International Business Machines Corporation | Integrated semiconductor devices with single crystalline beam, methods of manufacture and design structure |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9659717B2 (en) * | 2014-02-18 | 2017-05-23 | Analog Devices Global | MEMS device with constant capacitance |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6611168B1 (en) * | 2001-12-19 | 2003-08-26 | Analog Devices, Inc. | Differential parametric amplifier with physically-coupled electrically-isolated micromachined structures |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102007013329B4 (en) * | 2007-03-20 | 2011-01-27 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Method for producing a micromechanical component with a partial protective layer |
-
2008
- 2008-06-25 US US12/146,144 patent/US7615845B1/en not_active Expired - Fee Related
-
2009
- 2009-06-24 DE DE102009030281A patent/DE102009030281B4/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6611168B1 (en) * | 2001-12-19 | 2003-08-26 | Analog Devices, Inc. | Differential parametric amplifier with physically-coupled electrically-isolated micromachined structures |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8546240B2 (en) | 2011-11-11 | 2013-10-01 | International Business Machines Corporation | Methods of manufacturing integrated semiconductor devices with single crystalline beam |
US8629036B2 (en) | 2011-11-11 | 2014-01-14 | International Business Machines Corporation | Integrated semiconductor devices with amorphous silicon beam, methods of manufacture and design structure |
US8921201B2 (en) | 2011-11-11 | 2014-12-30 | International Business Machines Corporation | Integrated semiconductor devices with amorphous silicon beam, methods of manufacture and design structure |
US9059396B2 (en) | 2011-11-11 | 2015-06-16 | International Business Machines Corporation | Integrated semiconductor devices with single crystalline beam, methods of manufacture and design structure |
US9105751B2 (en) | 2011-11-11 | 2015-08-11 | International Business Machines Corporation | Integrated semiconductor devices with single crystalline beam, methods of manufacture and design structure |
US9172025B2 (en) | 2011-11-11 | 2015-10-27 | Globalfoundries U.S. 2 Llc | Integrated semiconductor devices with single crystalline beam, methods of manufacture and design structure |
US9758365B2 (en) | 2011-11-11 | 2017-09-12 | Globalfoundries Inc. | Integrated semiconductor devices with single crystalline beam, methods of manufacture and design structure |
WO2014064273A1 (en) | 2012-10-26 | 2014-05-01 | Commissariat à l'énergie atomique et aux énergies alternatives | Connection network for nems, having an improved arrangement |
FR2997555A1 (en) * | 2012-10-26 | 2014-05-02 | Commissariat Energie Atomique | CONNECTION NETWORK FOR NEMS WITH IMPROVED ARRANGEMENT |
US20150035387A1 (en) * | 2013-07-31 | 2015-02-05 | Analog Devices Technology | Mems switch device and method of fabrication |
US9911563B2 (en) * | 2013-07-31 | 2018-03-06 | Analog Devices Global | MEMS switch device and method of fabrication |
Also Published As
Publication number | Publication date |
---|---|
DE102009030281A1 (en) | 2010-01-28 |
DE102009030281B4 (en) | 2012-01-19 |
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