US7525133B2 - Trench-gate MOS transistor composed of multiple conductors - Google Patents

Trench-gate MOS transistor composed of multiple conductors Download PDF

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US7525133B2
US7525133B2 US11/616,603 US61660306A US7525133B2 US 7525133 B2 US7525133 B2 US 7525133B2 US 61660306 A US61660306 A US 61660306A US 7525133 B2 US7525133 B2 US 7525133B2
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semiconductor
conductor film
layer
trench
film
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US20070145416A1 (en
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Tsuyoshi Ohta
Bungo Tanaka
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Toshiba Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/665—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum
    • H10D64/666—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum the conductor further comprising additional layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs

Definitions

  • the present invention relates to a semiconductor device, and more particularly to a trench-gate semiconductor device.
  • Known power semiconductor elements capable of achieving a low on resistance include a trench-gate MOS transistor and an insulated-gate bipolar transistor (IGBT).
  • IGBT insulated-gate bipolar transistor
  • a trench-gate, n-channel MOS transistor for example, includes trenches formed in stripes or mesh such that they extend from an n-type source layer through a p-type base layer located below the source layer.
  • a film of conductor such as polysilicon is buried with a gate insulator on a trench wall to form a gate electrode.
  • Such the structure produces a power semiconductor element with a lower on resistance than that of the so-called planar gate type that includes a gate electrode formed on a gate insulator formed over a surface of the base layer.
  • an anisotropic etching is applied to the trench bottom to round the trench bottom to form an almost reverse-tapered (flask-shaped) trench having an enlarged radius of curvature (see JP2001/244325A, paragraphs 0019-0022, FIG. 1 and so forth).
  • This shape relieves the electric field at the trench bottom to improve the breakdown voltage and enables the drift layer to be thinned to the extent to reduce the drift resistance and thus reduce the on resistance.
  • a void may easily arise in the conductor film, or polysilicon film, configuring the gate electrode.
  • the void causes no problem so long as it exists in the polysilicon film at the center. Rather, it reduces stresses due to fine pattering and contributes to prevention of occurrences of D-S leakage current.
  • the void may migrate and come into contact with the gate insulator possibly. In this case, in the p-type base layer opposite to the void brought into contact with the gate insulator, an inverted layer is hardly formed even though the gate voltage is applied.
  • Such the migration of the void may cause the following two problems associated with the reliability of the gate electrode.
  • One is a problem found in a gate ruggedness test because an electric field concentrates on the gate insulator at a void edge (a boundary between the void and the polysilicon). Accordingly, the breakdown ruggedness lowers and reduces TDDB and ESD ruggedness.
  • Another is a problem related to the above electric field concentration that facilitates charges to flow through the gate insulator. This causes a threshold voltage fluctuation due to a charge trap in the insulator in a high-temperature gate bias test.
  • the present invention provides a semiconductor device, which comprises a first semiconductor layer of the first conduction type; a second semiconductor layer of the first conduction type formed on a surface of the first semiconductor layer; a semiconductor base layer of the second conduction type formed on the second semiconductor layer; a semiconductor diffusion layer of the first conduction type formed on a surface of the semiconductor base layer; a trench formed from the surface of the semiconductor diffusion layer to a depth reaching the second semiconductor layer; a gate electrode formed of a conductor film buried in the trench with a gate insulator interposed therebetween; a first main electrode brought into contact with the semiconductor diffusion layer and the semiconductor base layer; and a second main electrode formed on the rear surface of the first semiconductor layer, wherein the conductor film includes a first conductor film formed along the gate electrode to have a recess inside the trench and a second conductor film formed to fill the recess.
  • FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view taken along A-A′ of FIG. 1 .
  • FIG. 3 is an enlarged view of the bottom of a trench 15 shown in FIG. 2 .
  • FIG. 4 shows prior art and a problem thereof.
  • FIG. 5 shows a semiconductor device according to a second embodiment of the present invention.
  • FIG. 6 shows a semiconductor device according to a third embodiment of the present invention.
  • FIG. 7 shows a semiconductor device according to a variation of the embodiment of the present invention.
  • FIG. 1 shows a plan view of a semiconductor device according to a first embodiment of the present invention
  • FIG. 2 shows an A-A′ cross-sectional view thereof.
  • FIG. 1 shows a plan view in a state where a later-described source electrode 33 is removed.
  • the first and second conduction types exemplified as the n-type and p-type
  • an n-channel MOS transistor having a p-type base layer is shown.
  • the n-channel MOS transistor comprises an n + -type silicon substrate 11 .
  • the n + -type silicon substrate 11 serves as a drain layer connected to a drain electrode 31 on the rear surface.
  • Formed on the silicon substrate 11 is an n-type drift layer 12 having a lower impurity concentration and a higher resistance than those of the silicon substrate 11 , and a p-type base layer 13 is formed thereon.
  • An n + -type diffused source layer 14 is formed on a surface of the p-type base layer 13 .
  • a source electrode 33 is connected to both the source layer 14 and the p-type base layer 13 .
  • Trenches 15 are formed from the surface of the n + -type source layer 14 through the p-type base layer 13 to a depth reaching the drift layer 12 .
  • the trenches 15 in this example are formed in stripes as shown in FIG. 1 (stripes extending in the direction perpendicular to the page of FIG. 2 ).
  • the trenches 15 may be formed in mesh instead of stripes.
  • the trench 15 is reverse-tapered such that a width at a certain position on the bottom is made broader than a width at a higher portion.
  • a first gate electrode 17 A and a second gate electrode 19 A are buried in the trench 15 via a gate insulator 16 , and these two configure a gate electrode of the MOS transistor.
  • An interlayer insulator film 32 is formed at an upper end of the trench 15 to electrically isolate the source electrode 33 from the gate electrode.
  • the first gate electrode 17 A and the second gate electrode 19 A are formed of the same material such as a silicon-based conductor film, specifically polysilicon or a metal silicide (such as tungsten silicide), for example.
  • the first gate electrode 17 A is formed along the inner wall of the trench 15 , leaving a recess inside. To fill the recess, the second gate electrode 19 A is buried therein.
  • An interlayer insulator film 18 is formed between the first gate electrode 17 A and the second gate electrode 19 A.
  • the interlayer insulator film 18 may be formed through deposition of a silicon oxide film in the recess in the gate electrode 17 A using a process of CVD or the like after formation of the gate electrode 17 A. Alternatively, a silicon oxide film formed through natural oxidation of polysilicon after formation of the gate electrode 17 A may be used as the interlayer insulator film 18 .
  • a conductive film such as a tungsten silicide film may be used instead of the interlayer insulator film 18 .
  • an available film may be of either a material different from or a material same as that used in the first gate electrode 17 A and the second gate electrode 19 A if the material is distinctive and can serve as an interlayer film.
  • the trench 15 is reverse-tapered as shown in FIG. 3 , and a void B may arise near the bottom of the gate electrode 19 in many instances.
  • the void B may be formed in the vicinity of the center of the trench 15 in many instances immediately after deposition of polysilicon for formation of the second gate electrode 19 A.
  • the void B causes no problem so long as it exists in the polysilicon film at the center. Rather, it reduces stresses due to fine pattering and contributes to prevention of occurrences of D-S leakage current.
  • the void B may migrate toward the sidewall in the trench 15 .
  • the gate electrode includes the first gate electrode 17 A and the second gate electrode 19 A, and the interlayer insulator film 18 formed between both. Therefore, even if the void B arises and migrates, the migration is halted at the position of the interlayer insulator film 18 . Accordingly, the migration of the void B causes no deterioration of properties of the MOS transistor (such as an increase in on resistance and a reduction in breakdown voltage). If the void B can not migrate even after it arises, the void B can contribute to reduction in stress due to fine pattering and can contribute to prevention of occurrences of D-S leakage current.
  • the gate electrode is composed only of a single gate electrode as shown in FIG. 4 . Even though a void B arises in such the structure, there is no problem if the void B locates near the center of a trench 15 . If the void B migrates during a heat treatment step as shown on the lower side in FIG. 4 and comes in contact with a gate insulator 16 , though, it may cause an increase in on resistance, a reduction in breakdown voltage, and a variation in threshold voltage possibly. With this regard, this embodiment does not cause such the situation because it is provided with the interlayer insulator film 18 between the gate electrodes 17 A and 19 A.
  • FIG. 5 shows a MOS transistor according to a second embodiment of the present invention.
  • This embodiment is same in plan view as the first embodiment ( FIG. 1 ) and also same in cross-sectional view as a whole ( FIG. 2 ) and is omitted from the following detailed description.
  • the gate electrode is different in structure from that in the first embodiment.
  • the gate electrode in this embodiment is formed of two parts including a first gate electrode 17 B and a second gate electrode 19 B.
  • the former is a film of metal such as tungsten (W), copper (Cu) and titanium (Ti) while the latter is formed of a silicon-based conductor film, for example, polysilicon or a metal silicide (such as tungsten silicide).
  • both are different in material from each other.
  • the first gate electrode 17 B is formed of a different material, for example, a film of metal such as tungsten, copper and titanium. Therefore, even if the void B arises and migrates, the migration of the void B halts at the interface between the gate electrodes 17 B and 19 B. Therefore, the void B is prevented from coming into contact with the gate insulator 16 to bring an event in which the properties of the MOS transistor deteriorate.
  • the first gate electrode 17 B formed of a metal film can make the gate resistance lower than that formed of only polysilicon.
  • the example described in FIG. 5 includes no interlayer insulator ( 18 ) between the first gate electrode 17 B and the second gate electrode 19 B as in the first embodiment though such the interlayer insulator may be formed, needless to say.
  • FIG. 6 shows a MOS transistor according to a third embodiment of the present invention.
  • the gate electrode is formed of two parts including a first gate electrode 17 C and a second gate electrode 19 C like the above embodiment.
  • the former is formed of a silicon-based conductor film, for example, polysilicon or a metal silicide (such as tungsten silicide) while the latter is formed of a film of metal such as tungsten, copper and titanium in contrast to the second embodiment.
  • the migration of the void B can halt at the interface between the gate electrodes 17 C, 19 C to exert the same effect as in the above embodiment.
  • the second gate electrode 19 C formed of a metal film can make the gate resistance lower than that formed of only polysilicon.
  • the example described in FIG. 6 includes no interlayer insulator ( 18 ) between the first gate electrode 17 C and the second gate electrode 19 C as in the first embodiment though such the interlayer insulator may be formed, needless to say.
  • the MOS transistor is exemplified as the semiconductor device though the present invention is also applicable to an IGBT and a Schottky barrier diode.
  • the trench is described as reverse-tapered though the present invention is not limited to this shape and is also effective to trench-gates in all shapes and effectively operates when a void arises in such the trench-gates.
  • the present invention is also effective to a semiconductor device including a trench having a sidewall tapered at an angle of almost near 90°.
  • the description of the above embodiment is given to the effect when the void arises specifically.
  • the present invention is not limited to the semiconductor device in which the void arises. It is also effective to a semiconductor device in which no void arises actually, from the viewpoint of prevention of deterioration of the properties when a void arises.
  • the first gate electrode 17 A and the second gate electrode 19 A are made of the same material and the interlayer insulator film 18 is formed therebetween to halt the migration of the void.
  • the interlayer film may be omitted as shown in FIG. 7 for the reason that the first gate electrode 17 A and the second gate electrode 19 A are different in crystal grain from each other, for example, and the migration of the void can halt at the interface between both.

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Abstract

A semiconductor device comprises on a surface of a first semiconductor layer of the first conduction type a second semiconductor layer of the first conduction type. A semiconductor base layer of the second conduction type is formed on the second semiconductor layer, and a semiconductor diffusion layer of the first conduction type is formed on a surface of the semiconductor base layer. A trench is formed from the surface of the semiconductor diffusion layer to a depth reaching the second semiconductor layer. A gate electrode is formed of a conductor film buried in the trench with a gate insulator interposed therebetween. The conductor film includes a first conductor film formed along the gate electrode to have a recess and a second conductor film formed to fill the recess.

Description

CROSS REFERENCE TO RELATED APPLICATION
This application is based on and claims the benefit of priority from prior Japanese Patent Application No. 2005-377841, filed on Dec. 28, 2005, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a trench-gate semiconductor device.
2. Description of the Related Art
Known power semiconductor elements capable of achieving a low on resistance include a trench-gate MOS transistor and an insulated-gate bipolar transistor (IGBT).
A trench-gate, n-channel MOS transistor, for example, includes trenches formed in stripes or mesh such that they extend from an n-type source layer through a p-type base layer located below the source layer. A film of conductor such as polysilicon is buried with a gate insulator on a trench wall to form a gate electrode. Such the structure produces a power semiconductor element with a lower on resistance than that of the so-called planar gate type that includes a gate electrode formed on a gate insulator formed over a surface of the base layer.
In such the trench-gate structure, electric field concentration may easily arise at a corner of the bottom of the trench and this may cause deterioration of the breakdown voltage as a problem. When the trench width is reduced as fine patterning proceeds, the radius of curvature at the trench corner further decreases, and the degree of electric field concentration increases at the trench corner of the trench bottom. If the radius of curvature at the trench corner is small, current flows in a drift layer not uniformly, thereby increasing the drift resistance, resulting in increases in on resistance and power consumption in the element as a problem. Therefore, an anisotropic etching is applied to the trench bottom to round the trench bottom to form an almost reverse-tapered (flask-shaped) trench having an enlarged radius of curvature (see JP2001/244325A, paragraphs 0019-0022, FIG. 1 and so forth). This shape relieves the electric field at the trench bottom to improve the breakdown voltage and enables the drift layer to be thinned to the extent to reduce the drift resistance and thus reduce the on resistance.
When such the reverse-tapered trench is formed, a void may easily arise in the conductor film, or polysilicon film, configuring the gate electrode. The void causes no problem so long as it exists in the polysilicon film at the center. Rather, it reduces stresses due to fine pattering and contributes to prevention of occurrences of D-S leakage current. During crystallization of polysilicon proceeding in a heat treatment step executed after the formation of polysilicon, however, the void may migrate and come into contact with the gate insulator possibly. In this case, in the p-type base layer opposite to the void brought into contact with the gate insulator, an inverted layer is hardly formed even though the gate voltage is applied. In addition, in the drift layer below the base layer, an accumulation layer is hardly formed. Accordingly, this causes an increase in on resistance as a problem. The void easily occurs in the reverse-tapered trench though the same problem arises if a void occurs regardless of the trench shape.
Such the migration of the void may cause the following two problems associated with the reliability of the gate electrode. One is a problem found in a gate ruggedness test because an electric field concentrates on the gate insulator at a void edge (a boundary between the void and the polysilicon). Accordingly, the breakdown ruggedness lowers and reduces TDDB and ESD ruggedness. Another is a problem related to the above electric field concentration that facilitates charges to flow through the gate insulator. This causes a threshold voltage fluctuation due to a charge trap in the insulator in a high-temperature gate bias test.
SUMMARY OF THE INVENTION
In an aspect the present invention provides a semiconductor device, which comprises a first semiconductor layer of the first conduction type; a second semiconductor layer of the first conduction type formed on a surface of the first semiconductor layer; a semiconductor base layer of the second conduction type formed on the second semiconductor layer; a semiconductor diffusion layer of the first conduction type formed on a surface of the semiconductor base layer; a trench formed from the surface of the semiconductor diffusion layer to a depth reaching the second semiconductor layer; a gate electrode formed of a conductor film buried in the trench with a gate insulator interposed therebetween; a first main electrode brought into contact with the semiconductor diffusion layer and the semiconductor base layer; and a second main electrode formed on the rear surface of the first semiconductor layer, wherein the conductor film includes a first conductor film formed along the gate electrode to have a recess inside the trench and a second conductor film formed to fill the recess.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view taken along A-A′ of FIG. 1.
FIG. 3 is an enlarged view of the bottom of a trench 15 shown in FIG. 2.
FIG. 4 shows prior art and a problem thereof.
FIG. 5 shows a semiconductor device according to a second embodiment of the present invention.
FIG. 6 shows a semiconductor device according to a third embodiment of the present invention.
FIG. 7 shows a semiconductor device according to a variation of the embodiment of the present invention.
 DETAILED DESCRIPTION OF THE EMBODIMENTS
Semiconductor devices according to the embodiments of the present invention will now be described next in detail with reference to the drawings. FIG. 1 shows a plan view of a semiconductor device according to a first embodiment of the present invention, and FIG. 2 shows an A-A′ cross-sectional view thereof. FIG. 1 shows a plan view in a state where a later-described source electrode 33 is removed. In the following embodiments, with the first and second conduction types exemplified as the n-type and p-type, an n-channel MOS transistor having a p-type base layer is shown.
As shown in FIG. 2, the n-channel MOS transistor comprises an n+-type silicon substrate 11. The n+-type silicon substrate 11 serves as a drain layer connected to a drain electrode 31 on the rear surface. Formed on the silicon substrate 11 is an n-type drift layer 12 having a lower impurity concentration and a higher resistance than those of the silicon substrate 11, and a p-type base layer 13 is formed thereon. An n+-type diffused source layer 14 is formed on a surface of the p-type base layer 13. A source electrode 33 is connected to both the source layer 14 and the p-type base layer 13.
Trenches 15 are formed from the surface of the n+-type source layer 14 through the p-type base layer 13 to a depth reaching the drift layer 12. The trenches 15 in this example are formed in stripes as shown in FIG. 1 (stripes extending in the direction perpendicular to the page of FIG. 2). The trenches 15 may be formed in mesh instead of stripes.
To relieve electric field concentration at an edge of the bottom, the trench 15 is reverse-tapered such that a width at a certain position on the bottom is made broader than a width at a higher portion. A first gate electrode 17A and a second gate electrode 19A are buried in the trench 15 via a gate insulator 16, and these two configure a gate electrode of the MOS transistor. An interlayer insulator film 32 is formed at an upper end of the trench 15 to electrically isolate the source electrode 33 from the gate electrode. The first gate electrode 17A and the second gate electrode 19A are formed of the same material such as a silicon-based conductor film, specifically polysilicon or a metal silicide (such as tungsten silicide), for example. The first gate electrode 17A is formed along the inner wall of the trench 15, leaving a recess inside. To fill the recess, the second gate electrode 19A is buried therein. An interlayer insulator film 18 is formed between the first gate electrode 17A and the second gate electrode 19A. The interlayer insulator film 18 may be formed through deposition of a silicon oxide film in the recess in the gate electrode 17A using a process of CVD or the like after formation of the gate electrode 17A. Alternatively, a silicon oxide film formed through natural oxidation of polysilicon after formation of the gate electrode 17A may be used as the interlayer insulator film 18. As the interlayer film, a conductive film such as a tungsten silicide film may be used instead of the interlayer insulator film 18. In a word, an available film may be of either a material different from or a material same as that used in the first gate electrode 17A and the second gate electrode 19A if the material is distinctive and can serve as an interlayer film.
The trench 15 is reverse-tapered as shown in FIG. 3, and a void B may arise near the bottom of the gate electrode 19 in many instances. The void B may be formed in the vicinity of the center of the trench 15 in many instances immediately after deposition of polysilicon for formation of the second gate electrode 19A. The void B causes no problem so long as it exists in the polysilicon film at the center. Rather, it reduces stresses due to fine pattering and contributes to prevention of occurrences of D-S leakage current. During crystallization of polysilicon proceeding in a heat treatment step executed after the formation of polysilicon, however, the void B may migrate toward the sidewall in the trench 15. In the semiconductor device of this embodiment, the gate electrode includes the first gate electrode 17A and the second gate electrode 19A, and the interlayer insulator film 18 formed between both. Therefore, even if the void B arises and migrates, the migration is halted at the position of the interlayer insulator film 18. Accordingly, the migration of the void B causes no deterioration of properties of the MOS transistor (such as an increase in on resistance and a reduction in breakdown voltage). If the void B can not migrate even after it arises, the void B can contribute to reduction in stress due to fine pattering and can contribute to prevention of occurrences of D-S leakage current.
In a conventional trench-gate MOS transistor, the gate electrode is composed only of a single gate electrode as shown in FIG. 4. Even though a void B arises in such the structure, there is no problem if the void B locates near the center of a trench 15. If the void B migrates during a heat treatment step as shown on the lower side in FIG. 4 and comes in contact with a gate insulator 16, though, it may cause an increase in on resistance, a reduction in breakdown voltage, and a variation in threshold voltage possibly. With this regard, this embodiment does not cause such the situation because it is provided with the interlayer insulator film 18 between the gate electrodes 17A and 19A.
FIG. 5 shows a MOS transistor according to a second embodiment of the present invention. This embodiment is same in plan view as the first embodiment (FIG. 1) and also same in cross-sectional view as a whole (FIG. 2) and is omitted from the following detailed description. As shown in FIG. 5, the gate electrode is different in structure from that in the first embodiment. In a word, the gate electrode in this embodiment is formed of two parts including a first gate electrode 17B and a second gate electrode 19B. The former is a film of metal such as tungsten (W), copper (Cu) and titanium (Ti) while the latter is formed of a silicon-based conductor film, for example, polysilicon or a metal silicide (such as tungsten silicide). Thus, both are different in material from each other. In this structure, if the trench 15 is reverse-tapered, a void B easily arises in the second gate electrode 19B as in the first embodiment, and the void B may migrate possibly during a heat treatment step. In this embodiment, however, the first gate electrode 17B is formed of a different material, for example, a film of metal such as tungsten, copper and titanium. Therefore, even if the void B arises and migrates, the migration of the void B halts at the interface between the gate electrodes 17B and 19B. Therefore, the void B is prevented from coming into contact with the gate insulator 16 to bring an event in which the properties of the MOS transistor deteriorate. If the void B can not migrate even after the void B arises, it can contribute to reduce stresses due to fine pattering and contributes to prevention of occurrences of D-S leakage current. The first gate electrode 17B formed of a metal film can make the gate resistance lower than that formed of only polysilicon. The example described in FIG. 5 includes no interlayer insulator (18) between the first gate electrode 17B and the second gate electrode 19B as in the first embodiment though such the interlayer insulator may be formed, needless to say.
FIG. 6 shows a MOS transistor according to a third embodiment of the present invention. In this embodiment the gate electrode is formed of two parts including a first gate electrode 17C and a second gate electrode 19C like the above embodiment. The former is formed of a silicon-based conductor film, for example, polysilicon or a metal silicide (such as tungsten silicide) while the latter is formed of a film of metal such as tungsten, copper and titanium in contrast to the second embodiment. Also in this case, the migration of the void B can halt at the interface between the gate electrodes 17C, 19C to exert the same effect as in the above embodiment. The second gate electrode 19C formed of a metal film can make the gate resistance lower than that formed of only polysilicon. The example described in FIG. 6 includes no interlayer insulator (18) between the first gate electrode 17C and the second gate electrode 19C as in the first embodiment though such the interlayer insulator may be formed, needless to say.
The embodiments of the invention have been described above though the present invention is not limited to these embodiments but rather may be given various variations and additions without departing from the scope of the invention. For example, in the embodiments, the MOS transistor is exemplified as the semiconductor device though the present invention is also applicable to an IGBT and a Schottky barrier diode. In the above embodiments the trench is described as reverse-tapered though the present invention is not limited to this shape and is also effective to trench-gates in all shapes and effectively operates when a void arises in such the trench-gates. For example, the present invention is also effective to a semiconductor device including a trench having a sidewall tapered at an angle of almost near 90°. The description of the above embodiment is given to the effect when the void arises specifically. The present invention is not limited to the semiconductor device in which the void arises. It is also effective to a semiconductor device in which no void arises actually, from the viewpoint of prevention of deterioration of the properties when a void arises.
In the above first embodiment, the first gate electrode 17A and the second gate electrode 19A are made of the same material and the interlayer insulator film 18 is formed therebetween to halt the migration of the void. The interlayer film may be omitted as shown in FIG. 7 for the reason that the first gate electrode 17A and the second gate electrode 19A are different in crystal grain from each other, for example, and the migration of the void can halt at the interface between both.

Claims (12)

1. A semiconductor device, comprising:
a first semiconductor layer of a first conduction type;
a second semiconductor layer of the first conduction type formed on a surface of said first semiconductor layer;
a semiconductor base layer of a second conduction type formed on said second semiconductor layer;
a semiconductor diffusion layer of the first conduction type formed on a surface of said semiconductor base layer;
a trench formed from a surface of said semiconductor diffusion layer to a depth reaching said second semiconductor layer;
a gate electrode formed of a conductor film buried in said trench with a gate insulator interposed therebetween;
a first main electrode brought into contact with said semiconductor diffusion layer and said semiconductor base layer; and
a second main electrode formed on a rear surface of said first semiconductor layer,
wherein said conductor film includes a first conductor film formed along an inner wall of said trench covering the trench at its bottom and side to have a recess inside said trench, the recess formed to reach the second semiconductor layer, and a second conductor film formed to fill said recess,
said first and second conductor films being composed of the same material but being different in crystal grain.
2. The semiconductor device according to claim 1, wherein one of said first conductor film and said second conductor film is formed of a silicon-based conductor film.
3. The semiconductor device according to claim 1, wherein one of said first conductor film and said second conductor film is formed of polysilicon.
4. The semiconductor device according to claim 1, wherein one of said first conductor film and said second conductor film is formed of a metal silicide.
5. The semiconductor device according to claim 1, wherein said second conductor film contains a void therein.
6. A semiconductor device comprising:
a first semiconductor layer of a first conduction type;
a second semiconductor layer of the first conduction type formed on a surface of said first semiconductor layer;
a semiconductor base layer of a second conduction type formed on said second semiconductor layer;
a semiconductor diffusion layer of the first conduction type formed on a surface of said semiconductor base layer;
a trench formed from a surface of said semiconductor diffusion layer to a depth reaching said second semiconductor layer;
a gate electrode formed of a conductor film buried in said trench with a gate insulator interposed therebetween;
a first main electrode brought into contact with said semiconductor diffusion layer and said semiconductor base layer; and
a second main electrode formed on a rear surface of said first semiconductor layer,
wherein said conductor film includes a first conductor film formed along an inner wall of said trench covering its bottom and side to have a recess inside said trench, the recess formed to reach the second semiconductor layer, and a second conductor film formed to fill said recess, with an interlayer film formed between said first conductor film and said second conductor film and along the surface of said recess in said first conductor film,
wherein the first and second semiconductor films are electrically connected to each other.
7. The semiconductor device according to claim 6, wherein said interlayer film is a silicon oxide film.
8. The semiconductor device according to claim 6, wherein said first conductor film is a silicon-based conductor film, wherein said interlayer film is a silicon oxide film formed through natural oxidation of said first conductor film.
9. A semiconductor device comprising:
a first semiconductor layer of a first conduction type;
a second semiconductor layer of the first conduction type formed on a surface of said first semiconductor layer;
a semiconductor base layer of a second conduction type formed on said second semiconductor layer;
a semiconductor diffusion layer of the first conduction type formed on a surface of said semiconductor base layer;
a trench formed from a surface of said semiconductor diffusion layer to a depth reaching said second semiconductor layer;
a gate electrode formed of a conductor film buried in said trench with a gate insulator interposed therebetween;
a first main electrode brought into contact with said semiconductor diffusion layer and said semiconductor base layer; and
a second main electrode formed on a rear surface of said first semiconductor layer,
wherein said conductor film includes a first conductor film formed along an inner wall of said trench covering the trench and its bottom and side to have a recess inside said trench, the recess formed to reach the second semiconductor layer, and a second conductor film formed to fill said recess,
wherein the first and second conductor films are electrically connected to one another, and
wherein one of said first conductor film and said second conductor film is a silicon-based conductor film, and the other one of said first conductor film and said second conductor film is a metal film.
10. The semiconductor device according to claim 9, further comprising an interlayer film formed between said first conductor film and said second conductor film and along the surface of said recess in said first conductor film.
11. The semiconductor device according to claim 6, wherein said second conductor film contains a void therein.
12. The semiconductor device according to claim 9, wherein said second conductor film contains a void therein.
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