US7519766B2 - Method and device for transmission of adjustment information for data interface drivers for a RAM module - Google Patents
Method and device for transmission of adjustment information for data interface drivers for a RAM module Download PDFInfo
- Publication number
- US7519766B2 US7519766B2 US11/384,811 US38481106A US7519766B2 US 7519766 B2 US7519766 B2 US 7519766B2 US 38481106 A US38481106 A US 38481106A US 7519766 B2 US7519766 B2 US 7519766B2
- Authority
- US
- United States
- Prior art keywords
- data
- control
- bits
- memory module
- adjustment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related, expires
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
-
- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61F—FILTERS IMPLANTABLE INTO BLOOD VESSELS; PROSTHESES; DEVICES PROVIDING PATENCY TO, OR PREVENTING COLLAPSING OF, TUBULAR STRUCTURES OF THE BODY, e.g. STENTS; ORTHOPAEDIC, NURSING OR CONTRACEPTIVE DEVICES; FOMENTATION; TREATMENT OR PROTECTION OF EYES OR EARS; BANDAGES, DRESSINGS OR ABSORBENT PADS; FIRST-AID KITS
- A61F13/00—Bandages or dressings; Absorbent pads
- A61F13/14—Bandages or dressings; Absorbent pads specially adapted for the breast or abdomen
- A61F13/148—Abdomen bandages or bandaging garments
-
- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61F—FILTERS IMPLANTABLE INTO BLOOD VESSELS; PROSTHESES; DEVICES PROVIDING PATENCY TO, OR PREVENTING COLLAPSING OF, TUBULAR STRUCTURES OF THE BODY, e.g. STENTS; ORTHOPAEDIC, NURSING OR CONTRACEPTIVE DEVICES; FOMENTATION; TREATMENT OR PROTECTION OF EYES OR EARS; BANDAGES, DRESSINGS OR ABSORBENT PADS; FIRST-AID KITS
- A61F5/00—Orthopaedic methods or devices for non-surgical treatment of bones or joints; Nursing devices; Anti-rape devices
- A61F5/01—Orthopaedic devices, e.g. splints, casts or braces
- A61F5/02—Orthopaedic corsets
- A61F5/028—Braces for providing support to the lower back, e.g. lumbo sacral supports
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
- G11C7/1027—Static column decode serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled bit line addresses
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2254—Calibration
Definitions
- the invention relates to a method for transmission of control information for the adjustment of operating parameters of drivers in the data interface of a RAM module by means of a controller.
- the invention also relates to a device for carrying out this method.
- Random Access Memory is a memory which can be written to and read from with the capability for direct random access to addressed memory cells.
- One preferred, but not exclusive, field of application of the invention is dynamic RAMs (DRAMS), in particular “synchronous” dynamic RAMs (SDRAMS), as are used as main memories or graphics memories in computers.
- DRAMS dynamic RAMs
- SDRAMS synchronous dynamic RAMs
- a RAM module is normally integrated on a semiconductor chip and contains a large number of memory cells, which are arranged in the form of a matrix in rows and columns and are generally distributed over a plurality of individually addressable banks.
- the chip has a plurality of external connections (also referred to in the following text as “pins”), including address pins for application of the information for the addressing of the respective memory cells to be addressed, data pins, including a strobe pin, for inputting and outputting the memory data to be written to and read from the addressed memory cells with an accompanying strobe signal, and instruction pins for application of instructions for controlling the operation of the memory.
- the RAM module is connected via the pins that have been mentioned and associated connecting lines to corresponding pins of a control module (“controller”), which sends the memory data to be written and receives the data that has been read, and also sends the address information as well as the control instructions.
- controller a control module
- the pins (data pins and strobe pin) which are used for data transmission are a component of a bidirectional “data interface” both at the controller and at the RAM module, which data interface also contains output drivers (Off-Chip Driver OCD) for amplification of the signals to be transmitted and reception drivers (Off-Chip Receiver OCR) for amplification of the received signals.
- output drivers Off-Chip Driver OCD
- reception drivers Off-Chip Receiver OCR
- the controller sends an instruction MRS (“Set Mode Register”) in the form of a specific pattern of parallel bits to the instruction connections of the RAM module, and at the same time sends the mode information, likewise as a pattern of parallel bits, to other existing connections of the module. Since no memory data is transmitted between the RAM module and the controller and no memory cells are addressed either during the mode setting interval, the address connections as well as the data connections can be used for inputting the mode information during this time.
- a specific set of address connections is normally selected in order to carry out the role of mode information connections during the mode setting interval.
- Each of these dedicated connections is connected to the data input of one, and only one, cell, which is associated with it, in the mode register, whose set input is triggered by the adjustment instruction MRS.
- the size of the mode register (the number of cells) is thus limited to the number of setting information connections. This restricts the adjustment capabilities, to be precise both in terms of the numbers of parameters which can be adjusted and in terms of the variation width or the fineness of the adjustment of the parameter values. For this reason, additional mode settings, which go beyond the capacity of the mode register, must be provided in a different way. It is thus advantageous, for example, for drivers in the data interface of the RAM module each to have the capability to set one or more operating parameters relatively finely. This applies in particular to the output drivers.
- One important parameter, for example, of the output drivers in the data interface of the RAM module is the current level which a driver such as this must apply for a defined output load in order to reverse the charge on the relevant connecting line from the previous logic potential to the other logic potential, within one period of the data clock rate when the binary value of the signal to be transmitted changes.
- this current level In systems with a high data rate (that is to say with a high data clock frequency), this current level must be matched to the system environment (line impedance, termination impedance) as a function of the data rate. Since the said current level also depends on the operating voltage and is also subject to various environmental influences, such as the temperature, it is necessary to adjust the output drivers from time to time. Similar adjustments may also be required for the reception drivers in the data interface of the RAM module.
- All of the drivers that have been mentioned normally each have a pull-up branch, which is switched on in response to the one binary value of the signal to be amplified, in order to connect the output node of the driver to the “high” logic potential H, and a pull-down branch, which is switched on in response to the other binary value of the data signal, in order to connect the output node of the driver to the “low” logic potential L.
- the current level of a driver can be increased or decreased by increasing or decreasing the driver impedance. Because of unavoidable asymmetries in the characteristics of the pull-up and pull-down transistors, it is expedient to adjust the pull-up driver impedance and the pull-down driver impedance separately, by variation of the effective on-state impedance in the branches. This can be achieved by varying the number of parallel-connected switching transistors or by special resistive elements in the branches.
- control information for adjustment of parameters of the output drivers in the data interface of a RAM module OCD parameters
- OCD parameters OCD parameters
- the connecting branches which pass via these lines between the controller and the RAM module are referred to here as a “data channel”.
- the control information is transmitted in serial form as a burst of control bits at the data clock rate.
- DDR2-JEDEC Standard for DRAMs This standard relates to a memory mode in which the data clock rate is twice as fast as the basic clock rate of the memory system (Double Data Rate “DDR”).
- the control bit burst contains 4 bits, which indicate which driver parameter (pull-up impedance or pull-down impedance) should be adjusted, and in which direction (increase by one step or reduce by one step).
- the adjustment is then carried out in the RAM module by means of a setting device which influences the stated parameter, by one step in the indicated direction.
- a test transmission of data is then sent via the output drivers of the RAM module to the controller using the parameter settings that have been applied, and the controller analyses the reception of this data. This action is repeated until the optimum settings are found for the OCD parameters.
- the conditioning of the RAM module for this adjustment mode is carried out by inputting a specific bit pattern into selected cells in the mode register. Once the optimum settings of the OCD parameters have been found, these settings are locked by inputting a different specific bit pattern into the said cells in the mode register.
- This known adjustment method has the disadvantage that the control bit burst sent via the data channel has a wider bandwidth the higher the data clock rate is. Since the bandwidth of the data channel is limited, there is thus a risk of the control bit burst being distorted, when the data clock rate is high, to such an extent that the binary values of the individual bits are no longer reliably identified in the RAM module.
- a method for transmission of control information for the adjustment of operating parameters of drivers in the data interface of a RAM module is provided by means of a controller which has instruction and address connections in order to send instruction and address bits via instruction and address lines to instruction and address connections of the RAM module, and which has further connections in order, in a write mode, to send data bits at a given data clock rate via a data channel to corresponding connections of the data interface of the RAM module and, in a read mode, to receive data bits which have been sent from the data interface of the RAM module via the data channel, and with control bits for adjustment of the drivers being sent during an adjustment mode by the controller as a burst of data bits at the predetermined data clock rate via the data channel to the RAM module.
- Each control bit which is sent via the data channel is represented by a sequence of n ⁇ 2 data bits, which have a binary value corresponding to the relevant control bit and follow one another at the given data clock rate. Futher, the binary value of each control bit sent via the data channel is determined in the RAM module by detection of the binary value within the relevant sequence at a time at which the m-th data bit in the sequence appears, where m>1.
- a method for transmission of control information for the adjustment of operating parameters of drivers in the data interface of a RAM module is provided by means of a controller which has instruction and address connections in order to send instruction and address bits via instruction and address lines to instruction and address connections of the RAM module, and which has further connections in order, in a write mode, to send data bits at a given data clock rate via a data channel to corresponding connections of the data interface of the RAM module and, in a read mode, to receive data bits which have been sent from the data interface of the RAM module via the data channel, and with control bits for adjustment of the drivers being sent during an adjustment mode by the controller as a burst of data bits at the predetermined data clock rate via the data channel to the RAM module.
- the control bits sent via the data channel are only a subset of the total set of control bits for adjustment of the drivers and the other control bits for the adjustment of the drivers are sent by the controller via address lines to the RAM module and are stored in a mode register there.
- a device for transmission of control information for the adjustment of operating parameters of drivers in the data interface of a RAM module is provided by means of a controller , which contains the instruction and address connections in order to send instruction and address bits via instruction and address lines to instruction and address connections of the RAM module, further connections in order, in a write mode, to send data bits at a given data clock rate via a data channel to corresponding connections of the data interface of the RAM module and, in a read mode, to receive data bits which have been sent via the data channel from the data interface of the RAM module, a control burst generator, which can be activated during an adjustment mode in order to send control bits for the adjustment of drivers of the data interface of the RAM module as a burst of data bits via the data channel to the RAM module.
- the control burst generator represents each control bit to be sent via the data channel as a sequence of n ⁇ 2 data bits in the burst, which have a binary value corresponding to the relevant control bit and follow one another at the given data clock rate.
- the RAM module contains a control bit detector, which, during the adjustment mode determines the binary value of each control bit received via the data channel by detection of the binary value within the relevant sequence at a time at which the m-th data bit in the sequence appears, where m ⁇ 2.
- a device for transmission of control information for the adjustment of operating parameters of drivers in the data interface of a RAM module is provided by means of a controller, which contains the instruction and address connections in order to send instruction and address bits via instruction and address lines to instruction and address connections of the RAM module, further connections in order, in a write mode, to send data bits at a given data clock rate via a data channel to corresponding connections of the data interface of the RAM module and, in a read mode, to receive data bits which have been sent via the data channel from the data interface of the RAM module, a control burst generator, which can be activated during an adjustment mode in order to send control bits for the adjustment of drivers of the data interface of the RAM module as a burst of data bits via the data channel to the RAM module.
- the control burst generator produces only a subset of the total set of control bits for the adjustment of the drivers.
- a further control signal transmitter is provided in the controller and applies the other control bits for the adjustment of the drivers to selected address connections.
- a mode register which is contained in the RAM module, is provided for storage of the other control bits which are received via the address connections of the RAM module.
- FIG. 1 shows a part of a RAM module and of an associated controller in a memory system having a device for carrying out the method according to the invention.
- FIG. 2 shows coded tables of the transmitted control bits for adjustment of the output drivers in the memory system shown in FIG. 1 .
- FIG. 3 illustrates the layout of the transmission according to the invention of control bits via the data channel.
- the invention provides a transmission of control information sent via the data channel in such a way that the risk of corruption by the restricted channel bandwidth is reduced.
- the invention also provides a method and a device for transmission of control information for the adjustment of operating parameters of drivers in the data interface of a RAM module by means of a controller.
- the RAM module has instruction and address connections in order to send instruction and address bits via instruction and address lines to instruction and address connections of the RAM module. Further connections allow, in a write mode, to send data bits at a given data clock rate via a data channel to corresponding connections of the data interface of the RAM module and, in a read mode, to receive data bits which have been sent from the data interface of the RAM module via the data channel. Control bits for adjustment of the drivers are sent during an adjustment mode by the controller as a burst of data bits at the predetermined data clock rate via the data channel to the RAM module.
- each control bit which is sent via the data channel is represented by a sequence of n ⁇ 2 data bits, which have a binary value corresponding to the relevant control bit and follow one another at the given data clock rate.
- the binary value of each control bit sent via the data channel is determined in the RAM module by detection of the binary value within the relevant sequence at a time at which the m-th data bit in the sequence appears, where m>1.
- each of the control bits sent via the data channel to the RAM module as a sequence of two or more identical data bits effectively “lengthens” these control bits such that the bandwidth of the transmitted control information is only a fraction of the bandwidth which is required for a control bit burst of a conventional type, in which the individual control bits follow one another at the data clock of the RAM module.
- the reduced bandwidth of the transmitted control information according to the invention makes it possible to reliably detect the binary values of the control bits in the RAM module, even when the data clock rate is high.
- the lengthening of the control bits according to the invention is, in fact, carried out without slowing down the data clock rate. Slowing down the data clock rate in the adjustment interval would admittedly likewise reduce the bandwidth of the control information, but would result in problems because it would be necessary to wait for a certain synchronization time (lock-in time) whenever the data clock frequency was changed, until the frequency and phase of the data clock had stabilized.
- the identification of the binary value at the reception end will become more reliable the further the bit sampled there is located from the first and last bit in the sequence.
- the further the sampled bit is away from the first bit of the sequence the less is the risk of identification errors resulting from the set characteristic of the receiver.
- the further the sampled bit is away from the last bit in the sequence the less is the risk of identification errors as a result of the hold characteristic of the receiver.
- the sequence should in each case preferably include at least one bit before and after that bit which is sampled for identification at the reception end.
- the number n of respectively identical data bits per control bit is preferably at least equal to 3, and the order number m of the respectively sampled burst bit within the respective sequence is preferably governed by the relationship 2 ⁇ m ⁇ n ⁇ 1.
- FIG. 1 shows elements of a RAM module 1 which is integrated on a chip and has a plurality of external connections, which are also referred to here as “pins” and which are connected to corresponding connections of a controller 2 , during operation, by connecting lines.
- the illustration shows: a “clock pin” for the system or basic clock signal CLK; four “instruction pins” for four parallel instruction bits C 0 : 3 , fifteen “address pins” for fifteen parallel address bits A 0 : 14 ; eight “data pins” for eight parallel data bit streams D 0 : 7 ; a “strobe pin” for a data clock signal (strobe signal) DS.
- the instruction bits C 0 : 3 which are sent from the controller 2 form a 4-bit parallel code word and are decoded in the RAM module 1 by means of an instruction decoder 10 , in order in each case to activate one of a plurality of instruction lines, depending on the bit pattern in the code word.
- the four instruction bits C 0 : 3 are normally referred to, for historical reasons, as CS, RAS, CAS, WE.
- the controller 2 sends some selected instruction code word, which is either an operation instruction which instructs that some operation be carried out in the RAM module, or a so-called “NOP” instruction, whose meaning is “no operation”.
- the operation instructions include, inter alia, the write instruction WR for activation of the writing of data, the read instruction RD for activation of the reading of data, and the already mentioned instruction “set mode register”, or MRS for short, for activation of a process for setting operating parameters for the RAM module.
- each data pin and the strobe pin as well on the RAM module 1 is connected to the input of an associated reception driver 18 and to the output of an associated output driver 19 .
- FIG. 1 shows only the drivers for the data bit stream D 0 .
- the totality of the strobe and data pins together with the respectively associated drivers 18 , 19 form the bidirectional data interface of the RAM module.
- All of the drivers 18 , 19 in the data interface have control connections in order to activate the reception drivers 18 in response to the write instruction WR, so that they pass the received data bit streams D 0 : 7 and the strobe signal to associated internal data lines and an internal strobe line, respectively.
- all the output drivers 19 are activated in order to send the data streams which have been read in the RAM module 1 via the internal data lines, as well as the accompanying strobe signal, to the controller 2 .
- the selection of the data memory cells to which the write data is intended to be written or from which the read data is intended to be read is made by means of the address bits, which are applied by the controller 2 at a suitable time.
- a specific subset of the address pins is used for bank addressing, and the other address pins are used for row and column addressing.
- the row and column address bits are decoded in row and column address decoders.
- the address decoders and their connections to the address pins are not shown in FIG. 1 , nor is the matrix of the memory cells and the internal control circuit for connecting the data transmission paths between the respective data drivers 18 and 19 and the respectively addressed memory cells. All of these elements may be of a conventional type, as is generally known in the field of RAM modules.
- the numbers of address pins and data pins shown in FIG. 1 are only one example.
- the illustrated case of eight data pins allows data words to be written and read using a parallel format with a word length of 8 bits, that is to say each address addresses a group of 8 memory cells in the memory matrix (so-called “ ⁇ 8 module”).
- RAM modules with 4 or 16 or even 32 data pins are also normally used at the moment, with the latter (that is to say ⁇ 32 modules) being used in particular as graphics memories.
- the required number of address bits depends on the one hand on the memory size (the total number of data memory cells), and on the other hand on the number of data pins being used.
- the number of address pins may accordingly also be less than or more than the number in the illustrated example.
- the address pins and the data pins can be used for inputting control information for adjustment of various operating parameters for the RAM module.
- the control information which is input via the address pins, and is also referred to as “mode information”, is normally transmitted to a so-called mode register, where it is stored.
- each of the 15 address pins is connected to the data input of a respectively associated example of 15 cells M 0 : 14 of a mode register 11 , whose trigger or set connection is connected to that instruction line of the instruction decoder 10 which is activated on reception of the “set mode register” instruction (MRS instruction).
- the 15-cell mode register 11 thus holds the mode information, which comprises 15 bits and is applied to the address pins at the time of the MRS instruction.
- the 15 outputs of the fifteen mode register cells M 0 : 14 thus provide an image of this information.
- FIG. 1 illustrates the situation in which three different parameters Pa, Pb and Pc can be set at each output driver 19 , to be precise the pull-up and pull-down impedances Pa and Pb which were mentioned above and govern the driver impedance, and, furthermore, the so-called duty ratio Pc of the transmitted data or strobe pulses.
- This last-mentioned parameter defines the ratio between the length of the pulses of different polarity, which represent the two different binary values in a bit stream that is transmitted at the data clock rate.
- This ratio should preferably be equal to unity, although it may differ from this value because of asymmetries in the drivers, to be precise as a function of environmental conditions, so that an adjustment capability is desirable.
- An adjustment such as this can be carried out, for example, by means of variable delay circuits for individually delaying the falling flank and rising flank of the pulses transmitted from the driver 19 .
- the setting devices for the driver parameters Pa, Pb, Pc are illustrated schematically as the blocks 19 a , 19 b , 19 c , adjacent to the driver 19 , in FIG. 1 .
- the values to be set for the parameters Pa, Pb, Pc are passed by associated counters 13 a , 13 b , 13 c as multiple bit counts in parallel form to the setting devices 19 a , 19 b , 19 c .
- the counters 13 a:c have an increment input INC and decrement input DEC, and can be switched on individually by activation of a capability signal at their activation input EN.
- the respectively activated example of the counters 13 a:c counts one counting step upward whenever an effective signal flank appears at the INC input, and counts one counting step downward whenever an effective signal flank appears at the DEC input. On reaching the maximum count, any further INC signal flanks have no effect, and on reaching the count zero, any further DEC signal flanks have no effect.
- the controller 2 sends the control information for adjustment of the parameters Pa, Pb, Pc partially via address lines and partially via the data channel.
- the information which is sent via the address connections is the “destination information” which indicates which of the three parameters Pa, Pb, Pc has been chosen for adjustment.
- the information which is sent via the data channel is the “setting information”, which indicates whether the selected parameter should be incremented or decremented.
- the control information in total comprises 4 control bits, with two control bits X 1 , X 2 representing the destination information, and two control bits Y 1 , Y 2 representing the setting information.
- the two control bits X 1 , X 2 for the destination information are supplied from a required bit coder 21 in the controller 2 and are transmitted via two selected address lines, in parallel form, to two associated cells in the mode register 11 in the RAM module 1 , when the controller sends the MRS instruction. In the illustrated case, these are the mode register cells M 4 and M 5 .
- the meanings of the various patterns of the 2-bit combination X 1 ;X 2 are listed in the upper table in FIG. 2 , and are decoded in the RAM module 1 by means of a 1-from-2 decoder 12 , which has four outputs a, b, c, d.
- the only effect of the a output of the decoder 12 is to switch on the counter 13 a for incrementing or decrementing the parameter Pa (pull-up driver impedance) when the destination information X 1 ;X 2 has the bit pattern “0;1”.
- the only effect of the b output of the decoder 12 is to switch on the counter 13 b for incrementing or decrementing the parameter Pb (pull-down driver impedance) when the destination information has the bit pattern “1;0”.
- the only effect of the c output of the decoder 12 is to switch on the counter 13 c for incrementing or decrementing the parameter Pc (duty ratio) when the destination information has the bit pattern “1;1”.
- the two control bits Y 1 and Y 2 for the setting information are supplied from a setting bit coder 22 in the controller 2 .
- the meanings of the various patterns of this 2-bit combination Y 1 ;Y 2 are listed in the lower table in FIG. 2 . Accordingly, the bit pattern “0;0” stipulates decrementing, and the bit pattern “1;0” stipulates incrementing.
- the other possible bit patterns have no meaning.
- the control bit pattern Y 1 ;Y 2 is converted by means of a burst generator 23 to a burst of serial data bits in which each control bit is represented by a sequence of n successive data bits, which all have the same binary value as the relevant control bit.
- the burst generator 23 receives the internal write clock signal WRS which determines the data clock rate, is derived from the clock signal CLK in the controller and, during normal useful operation of the memory system, controls the sampling of the write data as well as the generation of the strobe signal DS to be transmitted.
- This write clock signal WRS is shown in the top line of the diagram in FIG. 3 .
- SDR single data rate
- DDR double data rate
- the data sampling takes place both on each rising flank and on each falling flank of the write clock signal WRS. The example described here is based on DDR operation.
- the second line of the diagram in FIG. 3 shows the successive time blocks in which the associated data bits # 1 , # 2 , . . . are in each case valid when the binary values of these data bits are “0” and “1” alternately.
- the write instruction WR is produced at the same time as the adjustment operating signal in the controller 2 .
- This signal is the negation of the destination information “no adjustment”.
- the burst generator 23 first of all samples the control bit Y 1 , then the control bit Y 2 , on each flank of the strobe signal DS, and in each case n-times successively, and sends the burst formed in this way via an associated output driver 29 of the controller 2 and via the data channel to the associated reception driver 18 in the RAM module 1 .
- each control bit in the setting information signal that is transmitted is represented by n identical data bits, each control bit appears to be lengthened over a plurality of data clock periods, so that it can be detected well in the RAM module even when the setting information signal is highly distorted because of the limited bandwidth of the transmission channel.
- the detection process is preferably carried out by sampling the received setting information signal as close as possible to the centre of each n-bit sequence of the data bit burst, that is to say at the n/2-th bit or at the (1+n/2)-th bit of the relevant sequence when n is an even number, and at the (n+1)2-th bit when n is an odd number. Sampling as close as possible to the centre of each n-bit sequence has the advantage that the detection of the relevant control bits is reliable not only if the set characteristic is poor but also in the case of a poor hold characteristic of the reception driver 18 .
- the sampling is carried out by means of corresponding flanks # 3 and # 6 of an internal read clock signal RDS, which is derived in the RAM module 1 from the clock signal CLK received there, with the same frequency and phase relationship as that with which the write clock signal WRS is derived in the controller 2 from the clock signal CLK there.
- the two control bits Y 1 and Y 2 which are detected in the RAM module 1 are decoded in order either to apply a decrement pulse to the DEC inputs or to apply an increment pulse to the INC inputs of the counters 13 a:c , depending on the pattern in the bit combination Y 1 ;Y 2 , as shown in the lower table in FIG. 2 .
- Any suitable logic circuit may be used for detection and decoding of the control bits Y 1 , Y 2 , and its implementation should not create any problem for a person skilled in the art.
- FIG. 1 shows one example of a circuit such as this.
- the internal read clock signal RDS is applied to the counting input of the counting circuit 15 .
- the adjustment operating signal which is produced by the inverter 14 is inactive, so that the counting circuit 15 which receives this signal at its activation input EN remains inactive, and remains reset at zero.
- the adjustment operating signal at the EN input of the counting circuit 15 becomes effective, and the counting circuit counts the flanks of the internal read clock signal RDS.
- the sample pulses which are produced for the counts “3” and “6” are used to clock a two-stage shift register 16 , whose data input receives the setting information signal.
- the shift register 16 is clocked for the first time with the count “3”, and the binary value of the setting information signal which exists at this time and represents the first control bit Y 1 is written as the first bit to the first stage of the register.
- the register is clocked for the second time, and the binary value of the setting information signal which exists at this time and represents the second control bit Y 2 is written to the first stage of the register 16 , with the first control bit Y 1 being shifted to the second stage.
- the outputs of the two register stages are connected to the two inputs of a 1:2 decoder 17 .
- the evaluation pulse which then appears activates the decoder 17 .
- the decoder 17 produces a pulse on a first output line, which leads to the DEC inputs of the counters 13 a:c . If the pattern of the control bits Y 1 ;Y 2 which are stored in the stages of the shift register 16 is equal to “1;0”, then the decoder 17 produces a pulse on a second output line, which leads to the INC inputs of the counters 13 a:c.
- the only counters 13 a:c which are effective are those whose EN input is activated by the destination information decoder 12 . It is therefore just those parameters Pa, Pb or Pc which are defined by the destination information X 1 ;X 2 in the mode register 11 which are decremented or incremented by one step, as a function of the setting information Y 1 ;Y 2 .
- a subsequent test mode in which the RAM module 1 sends a predefined test data pattern to the controller 2 , it is possible to use the data received there to check whether the new setting of the selected parameter is satisfactory. Depending on the result of this test, the adjustment may be repeated in order to increment or decrement the same parameter, or to adjust another parameter.
- a dedicated detection and adjustment circuit for parameter adjustment is preferably provided for each output driver 19 of the RAM module 1 , that is to say the group of elements 13 a:c , 16 , 17 , 19 a:c is provided more than once, with in each case one for each output driver 19 .
- a corresponding plurality of setting bit coders 22 and burst generators 23 are provided in the controller 2 , in each case one for each of the data channels which lead to the reception drivers 18 of the RAM module 1 . That parameter which is selected by the destination information X 1 ;X 2 can thus be adjusted simultaneously for all of the output drivers 19 , but individually for each output driver 19 , depending on the individually associated control bits Y 1 ;Y 2 .
- each parameter can be adjusted to the same extent for all the output drivers 19 . If, on the other hand, the aim is to be satisfied that each parameter can be adjusted to the same extent for all the output drivers 19 , then only a single common detection and adjustment circuit is required in the RAM module 1 , and is connected in parallel to all of the output drivers 19 . In a similar manner, a single setting bit coder 22 and a single burst generator 23 , which is connected in parallel to all of the controller output drivers 29 , is also then sufficient in the controller 2 .
- the reception drivers 18 can also be adjusted in a similar manner.
- a circuit arrangement in each case an individual circuit arrangement or one common circuit arrangement
- detection of the control bits and for adjustment of various driver parameters can likewise be provided for all of the reception drivers 18 , although this is not illustrated in FIG. 1 , for clarity reasons, and can be designed in precisely the same way as has been described above for the adjustment of the output drivers 19 .
- Other cells in the mode register can be used for the destination information, that is to say in order to indicate which of the parameters of the reception drivers 18 are intended to be adjusted.
- a test run can be carried out, during which the controller 2 sends a test data pattern which is written via the reception drivers 18 to the memory cells in the RAM module 1 , and is then read again and is sent back to the controller 2 via the (already adjusted) output drivers 19 .
- the controller 2 compares each of the test patterns to check whether the new setting of the selected parameter is satisfactory.
- the adjustment of the relative parameter can be repeated, for further incrementation or decrementation of the same parameter, or for adjustment of another parameter of the reception drivers.
- control bits which are in each case sent as a lengthened sequence via the data channel in the manner according to the invention can also include other control information than just the adjustment direction (“decrementing” or “incrementing”), for example a representation of the parameter value to be set and/or the destination information for selection of the parameter to be adjusted.
Landscapes
- Health & Medical Sciences (AREA)
- Vascular Medicine (AREA)
- Engineering & Computer Science (AREA)
- Biomedical Technology (AREA)
- Heart & Thoracic Surgery (AREA)
- Life Sciences & Earth Sciences (AREA)
- Animal Behavior & Ethology (AREA)
- General Health & Medical Sciences (AREA)
- Public Health (AREA)
- Veterinary Medicine (AREA)
- Orthopedic Medicine & Surgery (AREA)
- Nursing (AREA)
- Dram (AREA)
Abstract
Description
Claims (19)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102005013238.3 | 2005-03-22 | ||
DE102005013238.3A DE102005013238B4 (en) | 2005-03-22 | 2005-03-22 | Method and device for transferring adjustment information for data interface drivers of a RAM module |
Publications (2)
Publication Number | Publication Date |
---|---|
US20070064509A1 US20070064509A1 (en) | 2007-03-22 |
US7519766B2 true US7519766B2 (en) | 2009-04-14 |
Family
ID=36973567
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/384,811 Expired - Fee Related US7519766B2 (en) | 2005-03-22 | 2006-03-21 | Method and device for transmission of adjustment information for data interface drivers for a RAM module |
Country Status (4)
Country | Link |
---|---|
US (1) | US7519766B2 (en) |
KR (1) | KR100737503B1 (en) |
CN (1) | CN100561587C (en) |
DE (1) | DE102005013238B4 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9432439B1 (en) | 2007-01-26 | 2016-08-30 | Synchronoss Technologies, Inc. | System for and method of backing up content for use on a mobile device |
US9723460B1 (en) | 2003-07-21 | 2017-08-01 | Synchronoss Technologies, Inc. | Device message management system |
US20210327476A1 (en) * | 2018-05-25 | 2021-10-21 | Samsung Electronics Co., Ltd. | Memory device, memory system, and operation method of memory device |
US20220208236A1 (en) * | 2020-12-29 | 2022-06-30 | SK Hynix Inc. | Semiconductor device for setting options of i/o interface circuits |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080075057A1 (en) * | 2006-09-25 | 2008-03-27 | Mediatek Inc. | Frequency correction burst detection |
US8233336B2 (en) * | 2009-09-25 | 2012-07-31 | Infineon Technologies Ag | Memory controller comprising adjustable transmitter impedance |
US10423127B2 (en) | 2012-01-17 | 2019-09-24 | Fisher-Rosemount Systems, Inc. | Velocity based control in a non-periodically updated controller |
US11199824B2 (en) | 2012-01-17 | 2021-12-14 | Fisher-Rosemount Systems, Inc. | Reducing controller updates in a control loop |
JP6835589B2 (en) * | 2014-03-20 | 2021-02-24 | フィッシャー−ローズマウント システムズ,インコーポレイテッド | Reduced controller updates in control loops, how to control controlled devices, process control systems, process controllers |
US10127127B2 (en) * | 2015-06-04 | 2018-11-13 | Qualcomm Incorporated | Systems and methods for pre-warning a monitoring tool for a communication bus |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5311520A (en) | 1991-08-29 | 1994-05-10 | At&T Bell Laboratories | Method and apparatus for programmable memory control with error regulation and test functions |
US6643787B1 (en) | 1999-10-19 | 2003-11-04 | Rambus Inc. | Bus system optimization |
US20050251356A1 (en) * | 2004-05-10 | 2005-11-10 | Hynix Semiconductor, Inc. | Semiconductor memory device with ability to adjust impedance of data output driver |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06111010A (en) | 1992-09-29 | 1994-04-22 | Ricoh Co Ltd | Dram and controller |
JPH07129462A (en) * | 1993-10-28 | 1995-05-19 | Canon Inc | Memory controller |
DE69432455T2 (en) * | 1993-12-16 | 2003-11-20 | Fujitsu Ltd., Kawasaki | Variable latency output buffer and synchronizer for synchronous memory |
KR100459391B1 (en) * | 1997-10-24 | 2005-02-07 | 엘지전자 주식회사 | Device for controlling access timing of dram of different types using programmable wait cycle |
JP3468180B2 (en) | 1999-11-29 | 2003-11-17 | 日本電気株式会社 | Driving capability adjustment circuit and information processing device |
EP1291778B1 (en) | 2001-04-24 | 2007-06-27 | Rambus Inc. | Method and apparatus for coordinating memory operations among diversely-located memory components |
-
2005
- 2005-03-22 DE DE102005013238.3A patent/DE102005013238B4/en not_active Expired - Fee Related
-
2006
- 2006-03-21 US US11/384,811 patent/US7519766B2/en not_active Expired - Fee Related
- 2006-03-22 KR KR1020060026236A patent/KR100737503B1/en not_active IP Right Cessation
- 2006-03-22 CN CNB2006100682468A patent/CN100561587C/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5311520A (en) | 1991-08-29 | 1994-05-10 | At&T Bell Laboratories | Method and apparatus for programmable memory control with error regulation and test functions |
JPH06250938A (en) | 1991-08-29 | 1994-09-09 | American Teleph & Telegr Co <Att> | Circuit for performing test of ram array and control and its method |
US6643787B1 (en) | 1999-10-19 | 2003-11-04 | Rambus Inc. | Bus system optimization |
US20050251356A1 (en) * | 2004-05-10 | 2005-11-10 | Hynix Semiconductor, Inc. | Semiconductor memory device with ability to adjust impedance of data output driver |
Non-Patent Citations (3)
Title |
---|
English Translation of Indian Patent Office Examination Report. |
JEDEC Standard, DDR2 SDRAM Specifications; JESD79-2A (Revision of JESD79-2): JEDEC Solid State Technology Association, 2500 Wilson Boulevard, Arlington, VA 22201 3834, Jan. 2004: pp. 12-22 and 65. |
JEDEC Standard. (Jan. 2004). "DDR2 SDRAM Specification," JEDEC Standard No. 79-2A (JESD79-2A, Revision of JESD79-2). JEDEC Solid State Technology Association: Arlington, VA, pp. 12-22 and 65. |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9723460B1 (en) | 2003-07-21 | 2017-08-01 | Synchronoss Technologies, Inc. | Device message management system |
US9432439B1 (en) | 2007-01-26 | 2016-08-30 | Synchronoss Technologies, Inc. | System for and method of backing up content for use on a mobile device |
US20210327476A1 (en) * | 2018-05-25 | 2021-10-21 | Samsung Electronics Co., Ltd. | Memory device, memory system, and operation method of memory device |
US11508420B2 (en) * | 2018-05-25 | 2022-11-22 | Samsung Electronics Co., Ltd. | Memory device, memory system, and operation method of memory device |
US20220208236A1 (en) * | 2020-12-29 | 2022-06-30 | SK Hynix Inc. | Semiconductor device for setting options of i/o interface circuits |
US11551732B2 (en) * | 2020-12-29 | 2023-01-10 | SK Hynix Inc. | Semiconductor device for setting options of I/O interface circuits |
Also Published As
Publication number | Publication date |
---|---|
US20070064509A1 (en) | 2007-03-22 |
CN100561587C (en) | 2009-11-18 |
CN1838309A (en) | 2006-09-27 |
DE102005013238B4 (en) | 2015-07-16 |
KR100737503B1 (en) | 2007-07-09 |
DE102005013238A1 (en) | 2006-09-28 |
KR20060102530A (en) | 2006-09-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7519766B2 (en) | Method and device for transmission of adjustment information for data interface drivers for a RAM module | |
US20220121585A1 (en) | Apparatuses and methods for asymmetric bi-directional signaling incorporating multi-level encoding | |
US6834014B2 (en) | Semiconductor memory systems, methods, and devices for controlling active termination | |
US6317369B1 (en) | Semiconductor device allowing higher speed data transmission to and from external unit | |
US7804720B2 (en) | Integrated circuit memory devices including mode registers set using a data input/output bus | |
US6480946B1 (en) | Memory system for synchronized and high speed data transfer | |
US5844858A (en) | Semiconductor memory device and read and write methods thereof | |
US8286021B2 (en) | Flash memory devices with high data transmission rates and memory systems including such flash memory devices | |
CN111108561B (en) | System and method for improving write preambles in DDR memory devices | |
CN100543872C (en) | Regulate the apparatus and method of switching rate in the semiconductor memory system | |
US6777976B2 (en) | Interface circuit and semiconductor device with the same | |
US11625196B2 (en) | Semiconductor memory device and operating method thereof | |
US20230343383A1 (en) | Quadrature error correction circuit and semiconductor memory device including the same | |
US9406357B2 (en) | Data capture system and method, and memory controllers and devices | |
US6971039B2 (en) | DDR to SDR conversion that decodes read and write accesses and forwards delayed commands to first and second memory modules | |
US9478262B2 (en) | Semiconductor device including input/output circuit | |
CN113874940A (en) | Apparatus and method including multi-level command and address signals | |
US6842815B2 (en) | Output drivers preventing degradation of channel bus line in a memory module equipped with semiconductor memory devices including the output drivers | |
CN117153217B (en) | System and method for improving write preambles in DDR memory devices | |
CN115240727A (en) | Electronic device and electronic system related to executing terminal operation |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INFINEON TECHNOLOGIES AG, GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SCHAFER, ANDRE;REEL/FRAME:017998/0680 Effective date: 20060418 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: QIMONDA AG, GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INFINEON TECHNOLOGIES AG;REEL/FRAME:023806/0001 Effective date: 20060425 Owner name: QIMONDA AG,GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INFINEON TECHNOLOGIES AG;REEL/FRAME:023806/0001 Effective date: 20060425 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: INFINEON TECHNOLOGIES AG, GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:QIMONDA AG;REEL/FRAME:035623/0001 Effective date: 20141009 |
|
AS | Assignment |
Owner name: POLARIS INNOVATIONS LIMITED, IRELAND Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INFINEON TECHNOLOGIES AG;REEL/FRAME:036908/0923 Effective date: 20150708 |
|
REMI | Maintenance fee reminder mailed | ||
FPAY | Fee payment |
Year of fee payment: 8 |
|
SULP | Surcharge for late payment |
Year of fee payment: 7 |
|
FEPP | Fee payment procedure |
Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
LAPS | Lapse for failure to pay maintenance fees |
Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20210414 |