US7469273B2 - Multi-processor system verification circuitry - Google Patents

Multi-processor system verification circuitry Download PDF

Info

Publication number
US7469273B2
US7469273B2 US09/778,495 US77849501A US7469273B2 US 7469273 B2 US7469273 B2 US 7469273B2 US 77849501 A US77849501 A US 77849501A US 7469273 B2 US7469273 B2 US 7469273B2
Authority
US
United States
Prior art keywords
memory
interface
system memory
processing device
verification
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime, expires
Application number
US09/778,495
Other versions
US20020004823A1 (en
Inventor
Marquette John Anderson
Hakim Bederr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Assigned to TEXAS INSTRUMENTS INCORPORATED reassignment TEXAS INSTRUMENTS INCORPORATED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ANDERSON, MARQUETTE JOHN, BEDERR, HAKIM
Publication of US20020004823A1 publication Critical patent/US20020004823A1/en
Application granted granted Critical
Publication of US7469273B2 publication Critical patent/US7469273B2/en
Adjusted expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
    • G06F11/2242—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors in multi-processor systems, e.g. one processor becoming the test master
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors

Definitions

  • This invention relates in general to integrated circuits and, more particularly, to a multiprocessor system verification circuit.
  • Verifying the operation of an integrated circuit design is generally an extremely complicated procedure. This is especially true in the field of multi-processor designs, where a microprocessor unit is combined with other processor units, such as DSPs (digital signal processors), coprocessors or other microprocessor units.
  • DSPs digital signal processors
  • coprocessors or other microprocessor units.
  • Verifying the operation of an integrated circuit may take several forms.
  • One type of verification is generally referred to as “design debugging.” Debugging techniques are used to resolve weaknesses in the design of an integrated circuit.
  • Another type of verification is generally referred to as “production testing.” The objective of production testing is to identify product which does not meet performance requirements (or to sort product into one of several categories having different production requirements).
  • Functional testing looks for functional differences due to design defects. This type of testing is typically performed using ATPG (automatic test pattern generation) patterns or custom functional test patterns. Performance testing identifies parts that work at a specific speed rating.
  • the present invention provides a processing device comprising a master processor, a system memory and a slave processor subsystem.
  • the slave processor system includes a slave processor, a shared memory accessible by said master processor and said slave processor, and an external memory interface allowing said slave processor to access said system memory.
  • a verification interface passes system memory accesses to the system memory in a normal mode and passes system memory accesses to the shared memory in a verification mode.
  • the present invention provides significant advantages over the prior art.
  • debugging the slave processor subsystem may be performed without understanding the implementation of the master processor subsystem in which the slave processor subsystem is embedded.
  • extraneous interactions are isolated from the slave processor system during verification procedures.
  • the external memory interface can be production tested at operating speed in the same way as an application is actually executed in the field, thereby increasing the fault coverage and capability for performance testing of the slave subsystem.
  • FIG. 1 illustrates a block diagram of a prior art multiprocessor system
  • FIG. 2 illustrates a block diagram of a multiprocessor system with a verification interface
  • FIG. 3 illustrates a block diagram of a the verification interface
  • FIG. 4 illustrates a block diagram of a multiprocessor system using a master MPU, multiple slave DSP/Coprocessors and verification interface.
  • FIGS. 1-4 of the drawings like numerals being used for like elements of the various drawings.
  • FIG. 1 illustrates a basic diagram of a multiprocessor system 10 including an MPU subsystem 12 and a DSP/Coprocessor subsystem 14 .
  • MPU subsystem 12 includes a master MPU 16 , slave processor boot logic 18 and system memory 20 .
  • DSP/Coprocessor subsystem 14 includes an MPU interface 22 for interfacing with the MPU subsystem 12 , a shared memory 24 coupled to the MPU interface 22 , a slave DSP/Coprocessor 26 coupled to the shared memory 24 , a cache memory 28 , and an external memory interface 30 coupled to the system memory 20 and cache 28 .
  • An optional ROM 32 may be used to store programs or data on the DSP/ Coprocessor subsystem 14 for testing purposes.
  • FIG. 1 illustrates a general purpose multiprocessor system 10 , which could be used for a variety of applications, such as cellular phones, smart phones, personal digital assistants (PDAs), portable computers, and so on.
  • the DSP/Coprocessor subsystem 14 is used by the multiprocessor system 10 for performing certain tasks, such as voice recognition, handwriting recognition, text-to-speech conversion, to name a few.
  • the DSP/Coprocessor subsystem 14 is designed to execute certain tasks much more efficiently than a general-purpose processor.
  • the designer of a master MPU 16 may wish to combine the MPU subsystem 12 with a DSP/Coprocessor subsystem 14 in order to take advantage of faster execution of certain tasks.
  • it may be desirable to verify the operation of the operation of the multiprocessor system 10 including verifying operations of the DSP/ Coprocessor subsystem 14 .
  • programs for execution by the master MPU 16 are loaded into system memory 20 . These programs generally comprise code to allow the slave DSP/Coprocessor 26 to function.
  • code for the slave DSP/Coprocessor 26 is loaded into the system memory 20 .
  • the master MPU 16 executes the code, setting up the system memory for access by the external memory interface 30 and programming the slave processor boot logic 18 to control the slave processor(s).
  • the slave DSP/Coprocessor 26 programs the cache memory 28 and executes the code from the system memory. The results can be analyzed using traditional debugging techniques, such as setting breakpoints and observing memory locations.
  • the DSP/Coprocessor subsystem 14 can be difficult to debug within the multiprocessor system 10 , since the operation of the MPU subsystem 12 is generally unknown to the designers of the DSP/Coprocessor subsystem 14 . Further, the DSP/Coprocessor subsystem 14 is not isolated from extraneous system interactions, such as multiple buses and interfaces on the MPU subsystem 12 .
  • speed paths in the DSP/Coprocessor subsystem 14 are identified and code is written to activate the speed paths in the DSP/Coprocessor subsystem 14 .
  • Code for the master MPU 16 and test patterns and code for the slave DSP/Coprocessor 26 are stored in the system memory 20 .
  • the test patterns and slave DSP/Coprocessor code are transferred from the system memory 20 to the shared memory 24 .
  • the code is then executed by the slave DSP/Coprocessor 26 to test the external memory interface 30 and the cache 28 .
  • test pattern and code may be stored in a micro-code ROM 32 .
  • test execution may be initiated by booting to the first address in the micro-code ROM 32 .
  • This embodiment requires a high area overhead for the ROM 32 and has fixed fault coverage.
  • FIG. 2 illustrates a block diagram of a multiprocessor system 40 using a verification interface 42 to aid in debugging and testing.
  • the multiprocessor system 10 includes an MPU subsystem 12 and a DSP/Coprocessor subsystem 14 .
  • MPU subsystem 12 includes a master MPU 16 , slave processor boot logic 18 and system memory 20 .
  • DSP/Coprocessor subsystem 14 includes an MPU interface 22 for interfacing with the MPU subsystem 12 via the verification interface 42 , a shared memory 24 coupled to the MPU interface 22 , a slave DSP/Coprocessor 26 coupled to the shared memory 24 , a cache memory 28 , and an external memory interface 30 coupled to verification interface 42 and cache 28 .
  • Verification interface 42 is also coupled to system memory 20 .
  • the entire multiprocessor system 40 may be fabricated on a single integrated circuit.
  • the verification interface 42 In normal operation of the multiprocessor system 40 , the verification interface 42 is disabled. In this state, control and data signals pass between the system memory 20 and external memory interface 30 and between the master MPU 16 and the MPU Interface 22 as shown in FIG. 1 ; i.e., under normal operations, the verification interface 42 is transparent. However, when the verification interface 42 is enabled for verification purposes, requests from the external memory interface 30 to access system memory 20 are translated by the verification interface 42 such that the shared memory 24 is accessed instead. Hence, the MPU subsystem 12 can be completely isolated from the DSP/Coprocessor subsystem 14 during verification procedures.
  • the verification interface 42 may be implemented in a independent module of the DSP/Coprocessor subsystem 14 or, alternatively, the verification interface 42 may be implemented as part of the external memory interface 30 .
  • FIG. 3 illustrates a block diagram of the verification interface 42 .
  • Control signals from the external memory interface 30 to access the system memory 20 are received by demultiplexer 44 .
  • verification mode When verification mode is disabled, the signals are passed to the system memory 20 .
  • verification mode When verification mode is enabled, the signals are passed to protocol translator 46 .
  • Request multiplexer 46 translates the memory requests to a form acceptable by the MPU interface 22 .
  • the output of protocol translator 46 is received by multiplexer 48 , which also receives control signals from master MPU 16 .
  • the signals from the master MPU 16 are passed by multiplexer 48 to the MPU interface 22 .
  • multiplexer 48 passes the output of protocol translator 46 to the MPU interface 22 .
  • multiplexer 50 receives the data from shared memory 24 (via the MPU interface 22 ) and from system memory 20 .
  • verification mode When verification mode is disabled, data from the system memory is passed through multiplexer 50 to the external memory interface 30 .
  • verification mode is enabled, data from the shared memory 24 is passed through multiplexer 50 to the external memory interface 30 .
  • signals pass between the master MPU 16 and the MPU interface 22 and between system memory 20 and the external memory interface 30 , as shown in FIG. 1 .
  • the MPU subsystem 12 is isolated from the DSP/Coprocessor subsystem 14 .
  • Requests from the external memory interface 30 are translated to a form that is used by the MPU interface 22 to access shared memory 24 .
  • Data from the shared memory 24 pursuant to a system memory request is passed to the external memory interface 30 .
  • the protocol translator can translate between different protocol types used by the MPU interface 22 and the external memory interface 30 .
  • the external memory interface 30 generally uses a request-based protocol whereas the MPU interface may use a strobe-based protocol.
  • the protocol translator may translate a request signal to a strobe signal for accessing the shared memory 24 through the MPU interface 22 .
  • the verification interface 42 can be used to debug the DSP/Coprocessor subsystem 14 without knowledge of the MPU subsystem 12 and to isolate the DSP/Coprocessor subsystem 14 from extraneous system interaction with the MPU subsystem 12 .
  • the debug interface programs the external memory interface 30 and loads debug code and data into the shared memory.
  • the verification interface 42 is then enabled in verification mode and the DSP/Coprocessor subsystem 14 is reset.
  • the slave DSP/Coprocessor 26 programs the cache and executes the debug code from shared memory 24 .
  • Memory access signals from the external memory interface 30 to system memory are translated by the protocol translator 46 , such that the request is fulfilled by shared memory 24 .
  • Traditional debugging techniques can then be used to analyze the operation of the DSP/Coprocessor subsystem 14 .
  • patterns for activating and testing critical speed paths in the DSP/Coprocessor subsystem 14 can be generated and stored in the shared memory 24 .
  • the verification interface 42 is enabled and the external memory interface 30 and cache can be tested at speed to determine whether any of the paths fail.
  • system memory accesses by the external memory interface 30 are translated by the verification interface 42 and directed to the shared memory 24 via the MPU interface 22 .
  • the test pattern set can be modified at any time during design or silicon debug, as opposed to a fixed test pattern set encoded in ROM. Since the test pattern set can be changed even after silicon samples are produced, the initial test pattern generation can be easily modified to accommodate late changes in the chip design.
  • FIG. 4 illustrates an embodiment of the invention wherein multiple DSPs and/or coprocessors are implemented.
  • a system memory arbiter 52 is provided to arbitrate memory requests from the external memory interfaces 30 associated with the various cache memories 28 and slave DSP/Coprocessors 26 (individually referenced as external memory interfaces 30 1 through 30 n , cache memories 28 1 through 28 n and slave DSP/Coprocessors 26 1 through 26 n ).
  • the verification interface 42 is coupled between a system memory interface 56 , including the system memory arbiter 52 and the external memory interfaces 30 , and the system memory 20 and between the master MPU 16 and the MPU interface 22 . Accesses between various external memory interfaces 30 are resolved by the system memory arbiter 52 . Accesses to the shared memory 24 from the master MPU 16 and the slave DSP/Coprocessors 26 are resolved by shared memory interface 54 .
  • the verification interface 42 If the verification interface 42 is disabled, the requests from the system memory arbiter 52 will be passed to the system memory 20 . On the other hand, if the verification interface 42 is enabled for testing or debugging, requests from the system memory arbiter 52 will be translated and passed to the MPU interface 22 for accessing the shared memory 24 .
  • This architecture will support any number of slave DSP/Coprocessors 26 . Debugging the subsystem and performing critical path testing can be performed as described above in connection with a multiprocessor system 40 using a single slave DSP/Coprocessor 26 .
  • the present invention provides significant advantages over the prior art in both the debugging and testing of a processor device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Debugging And Monitoring (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

A multiprocessor system (40) includes a MPU subsystem (12), with master MPU (16) and shared memory (24), and a DSP/Coprocessor subsystem (14), with one or more slave DSP/Coprocessors (26). The system memory (20) is accessed by each DSP/Coprocessor subsystem (14) through a cache (28) and external memory interface (30). A verification interface (42) is used in verification mode to isolate the DSP/Coprocessor subsystem (14) from the MPU subsystem (12) and to translate system memory requests from the external memory interfaces (30) (through an arbiter (52), where multiple external memory interfaces are used) to a protocol which can be used to access the data from the shared memory (24).

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
Not Applicable
STATEMENT OF FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable
BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates in general to integrated circuits and, more particularly, to a multiprocessor system verification circuit.
2. Description of the Related Art
Verifying the operation of an integrated circuit design is generally an extremely complicated procedure. This is especially true in the field of multi-processor designs, where a microprocessor unit is combined with other processor units, such as DSPs (digital signal processors), coprocessors or other microprocessor units.
Verifying the operation of an integrated circuit may take several forms. One type of verification is generally referred to as “design debugging.” Debugging techniques are used to resolve weaknesses in the design of an integrated circuit. Another type of verification is generally referred to as “production testing.” The objective of production testing is to identify product which does not meet performance requirements (or to sort product into one of several categories having different production requirements). There are two types of production testing. Functional testing looks for functional differences due to design defects. This type of testing is typically performed using ATPG (automatic test pattern generation) patterns or custom functional test patterns. Performance testing identifies parts that work at a specific speed rating.
Matters are further complicated when design of one of the processor units is from a different source from other processor units on the integrated circuit. This can occur, for example, when a company wishes to combine its microprocessor design with DSPs or coprocessors from another company to provide a specialized integrated circuit. Generally speaking, neither company will want to provide detailed specifications to their designs. Accordingly, verifying the operation of each processor can become problematic.
Therefore, a need has arisen for a method and apparatus for verifying multiprocessor systems.
BRIEF SUMMARY OF THE INVENTION
The present invention provides a processing device comprising a master processor, a system memory and a slave processor subsystem. The slave processor system includes a slave processor, a shared memory accessible by said master processor and said slave processor, and an external memory interface allowing said slave processor to access said system memory. A verification interface passes system memory accesses to the system memory in a normal mode and passes system memory accesses to the shared memory in a verification mode.
The present invention provides significant advantages over the prior art. First, debugging the slave processor subsystem may be performed without understanding the implementation of the master processor subsystem in which the slave processor subsystem is embedded. Second, extraneous interactions are isolated from the slave processor system during verification procedures. Third, the external memory interface can be production tested at operating speed in the same way as an application is actually executed in the field, thereby increasing the fault coverage and capability for performance testing of the slave subsystem.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
FIG. 1 illustrates a block diagram of a prior art multiprocessor system;
FIG. 2 illustrates a block diagram of a multiprocessor system with a verification interface;
FIG. 3 illustrates a block diagram of a the verification interface; and
FIG. 4 illustrates a block diagram of a multiprocessor system using a master MPU, multiple slave DSP/Coprocessors and verification interface.
 DETAILED DESCRIPTION OF THE INVENTION
The present invention is best understood in relation to FIGS. 1-4 of the drawings, like numerals being used for like elements of the various drawings.
FIG. 1 illustrates a basic diagram of a multiprocessor system 10 including an MPU subsystem 12 and a DSP/Coprocessor subsystem 14. For purposes of illustration, it will be assumed that the MPU subsystem 12 and the DSP/Coprocessor subsystem 14 are proprietary designs by different companies, although this is not necessary for use of the present invention. MPU subsystem 12 includes a master MPU 16, slave processor boot logic 18 and system memory 20. DSP/Coprocessor subsystem 14 includes an MPU interface 22 for interfacing with the MPU subsystem 12, a shared memory 24 coupled to the MPU interface 22, a slave DSP/Coprocessor 26 coupled to the shared memory 24, a cache memory 28, and an external memory interface 30 coupled to the system memory 20 and cache 28. An optional ROM 32 may be used to store programs or data on the DSP/ Coprocessor subsystem 14 for testing purposes.
The block diagram shown in FIG. 1 illustrates a general purpose multiprocessor system 10, which could be used for a variety of applications, such as cellular phones, smart phones, personal digital assistants (PDAs), portable computers, and so on. Typically, the DSP/Coprocessor subsystem 14 is used by the multiprocessor system 10 for performing certain tasks, such as voice recognition, handwriting recognition, text-to-speech conversion, to name a few. The DSP/Coprocessor subsystem 14 is designed to execute certain tasks much more efficiently than a general-purpose processor.
Commonly, the designer of a master MPU 16 may wish to combine the MPU subsystem 12 with a DSP/Coprocessor subsystem 14 in order to take advantage of faster execution of certain tasks. During both the design and implementation stages, however, it may be desirable to verify the operation of the operation of the multiprocessor system 10, including verifying operations of the DSP/ Coprocessor subsystem 14.
To debug the DSP/Coprocessor subsystem 14, several steps are necessary. First, programs for execution by the master MPU 16 are loaded into system memory 20. These programs generally comprise code to allow the slave DSP/Coprocessor 26 to function. Second, code for the slave DSP/Coprocessor 26 is loaded into the system memory 20. The master MPU 16 executes the code, setting up the system memory for access by the external memory interface 30 and programming the slave processor boot logic 18 to control the slave processor(s). The slave DSP/Coprocessor 26 programs the cache memory 28 and executes the code from the system memory. The results can be analyzed using traditional debugging techniques, such as setting breakpoints and observing memory locations.
The DSP/Coprocessor subsystem 14 can be difficult to debug within the multiprocessor system 10, since the operation of the MPU subsystem 12 is generally unknown to the designers of the DSP/Coprocessor subsystem 14. Further, the DSP/Coprocessor subsystem 14 is not isolated from extraneous system interactions, such as multiple buses and interfaces on the MPU subsystem 12.
For production performance testing, speed paths in the DSP/Coprocessor subsystem 14 are identified and code is written to activate the speed paths in the DSP/Coprocessor subsystem 14. Code for the master MPU 16 and test patterns and code for the slave DSP/Coprocessor 26 are stored in the system memory 20. The test patterns and slave DSP/Coprocessor code are transferred from the system memory 20 to the shared memory 24. The code is then executed by the slave DSP/Coprocessor 26 to test the external memory interface 30 and the cache 28.
Once again, production testing of parts based on the speed paths in the DSP/Coprocessor subsystem 14 requires knowledge of the detailed operation of the MPU subsystem 12.
In an alternative embodiment, the test pattern and code may be stored in a micro-code ROM 32. In this case, test execution may be initiated by booting to the first address in the micro-code ROM 32.
This embodiment requires a high area overhead for the ROM 32 and has fixed fault coverage.
FIG. 2 illustrates a block diagram of a multiprocessor system 40 using a verification interface 42 to aid in debugging and testing. Once again, the multiprocessor system 10 includes an MPU subsystem 12 and a DSP/Coprocessor subsystem 14. MPU subsystem 12 includes a master MPU 16, slave processor boot logic 18 and system memory 20. DSP/Coprocessor subsystem 14 includes an MPU interface 22 for interfacing with the MPU subsystem 12 via the verification interface 42, a shared memory 24 coupled to the MPU interface 22, a slave DSP/Coprocessor 26 coupled to the shared memory 24, a cache memory 28, and an external memory interface 30 coupled to verification interface 42 and cache 28. Verification interface 42 is also coupled to system memory 20. The entire multiprocessor system 40 may be fabricated on a single integrated circuit.
In normal operation of the multiprocessor system 40, the verification interface 42 is disabled. In this state, control and data signals pass between the system memory 20 and external memory interface 30 and between the master MPU 16 and the MPU Interface 22 as shown in FIG. 1; i.e., under normal operations, the verification interface 42 is transparent. However, when the verification interface 42 is enabled for verification purposes, requests from the external memory interface 30 to access system memory 20 are translated by the verification interface 42 such that the shared memory 24 is accessed instead. Hence, the MPU subsystem 12 can be completely isolated from the DSP/Coprocessor subsystem 14 during verification procedures.
The verification interface 42 may be implemented in a independent module of the DSP/Coprocessor subsystem 14 or, alternatively, the verification interface 42 may be implemented as part of the external memory interface 30.
FIG. 3 illustrates a block diagram of the verification interface 42. Control signals from the external memory interface 30 to access the system memory 20 are received by demultiplexer 44. When verification mode is disabled, the signals are passed to the system memory 20. When verification mode is enabled, the signals are passed to protocol translator 46. Request multiplexer 46 translates the memory requests to a form acceptable by the MPU interface 22. The output of protocol translator 46 is received by multiplexer 48, which also receives control signals from master MPU 16. When verification mode is disabled, the signals from the master MPU 16 are passed by multiplexer 48 to the MPU interface 22. When verification mode is enabled, multiplexer 48 passes the output of protocol translator 46 to the MPU interface 22. Similarly, multiplexer 50 receives the data from shared memory 24 (via the MPU interface 22) and from system memory 20. When verification mode is disabled, data from the system memory is passed through multiplexer 50 to the external memory interface 30. When verification mode is enabled, data from the shared memory 24 is passed through multiplexer 50 to the external memory interface 30.
During normal operations (i.e., verification mode is disabled), signals pass between the master MPU 16 and the MPU interface 22 and between system memory 20 and the external memory interface 30, as shown in FIG. 1. In verification mode, however, the MPU subsystem 12 is isolated from the DSP/Coprocessor subsystem 14. Requests from the external memory interface 30 are translated to a form that is used by the MPU interface 22 to access shared memory 24. Data from the shared memory 24 pursuant to a system memory request is passed to the external memory interface 30.
The protocol translator can translate between different protocol types used by the MPU interface 22 and the external memory interface 30. For example, the external memory interface 30 generally uses a request-based protocol whereas the MPU interface may use a strobe-based protocol. Thus, the protocol translator may translate a request signal to a strobe signal for accessing the shared memory 24 through the MPU interface 22.
Accordingly, referring to FIGS. 2 and 3, the verification interface 42 can be used to debug the DSP/Coprocessor subsystem 14 without knowledge of the MPU subsystem 12 and to isolate the DSP/Coprocessor subsystem 14 from extraneous system interaction with the MPU subsystem 12. To debug the DSP/Coprocessor subsystem 14, the debug interface programs the external memory interface 30 and loads debug code and data into the shared memory. The verification interface 42 is then enabled in verification mode and the DSP/Coprocessor subsystem 14 is reset. The slave DSP/Coprocessor 26 programs the cache and executes the debug code from shared memory 24. Memory access signals from the external memory interface 30 to system memory are translated by the protocol translator 46, such that the request is fulfilled by shared memory 24. Traditional debugging techniques can then be used to analyze the operation of the DSP/Coprocessor subsystem 14.
For production testing using a critical path test, patterns for activating and testing critical speed paths in the DSP/Coprocessor subsystem 14 can be generated and stored in the shared memory 24. After loading the code in the shared memory 24, the verification interface 42 is enabled and the external memory interface 30 and cache can be tested at speed to determine whether any of the paths fail. Once again, system memory accesses by the external memory interface 30 are translated by the verification interface 42 and directed to the shared memory 24 via the MPU interface 22. This eliminates the need for a ROM for storing test patterns, saving chip area. Further, the test pattern set can be modified at any time during design or silicon debug, as opposed to a fixed test pattern set encoded in ROM. Since the test pattern set can be changed even after silicon samples are produced, the initial test pattern generation can be easily modified to accommodate late changes in the chip design.
FIG. 4 illustrates an embodiment of the invention wherein multiple DSPs and/or coprocessors are implemented. In this case, a system memory arbiter 52 is provided to arbitrate memory requests from the external memory interfaces 30 associated with the various cache memories 28 and slave DSP/Coprocessors 26 (individually referenced as external memory interfaces 30 1 through 30 n, cache memories 28 1 through 28 n and slave DSP/Coprocessors 26 1 through 26 n).
In this embodiment, the verification interface 42 is coupled between a system memory interface 56, including the system memory arbiter 52 and the external memory interfaces 30, and the system memory 20 and between the master MPU 16 and the MPU interface 22. Accesses between various external memory interfaces 30 are resolved by the system memory arbiter 52. Accesses to the shared memory 24 from the master MPU 16 and the slave DSP/Coprocessors 26 are resolved by shared memory interface 54.
If the verification interface 42 is disabled, the requests from the system memory arbiter 52 will be passed to the system memory 20. On the other hand, if the verification interface 42 is enabled for testing or debugging, requests from the system memory arbiter 52 will be translated and passed to the MPU interface 22 for accessing the shared memory 24. This architecture will support any number of slave DSP/Coprocessors 26. Debugging the subsystem and performing critical path testing can be performed as described above in connection with a multiprocessor system 40 using a single slave DSP/Coprocessor 26.
The present invention provides significant advantages over the prior art in both the debugging and testing of a processor device. First, it is not necessary to understand the implementation of the MPU subsystem 12 in which the DSP/Coprocessor subsystem 14 is embedded in order to debug the DSP/Coprocessor subsystem 14. Second, extraneous system interactions are isolated from the DSP/Coprocessor subsystem 14 during testing. Third, the external memory interface 30 and cache 28 can be production tested at operating speed in the same way as the application is actually executed in the field, thereby increasing the test coverage of the DSP/Coprocessor subsystem 14.
Although the Detailed Description of the invention has been directed to certain exemplary embodiments, various modifications of these embodiments, as well as alternative embodiments, will be suggested to those skilled in the art. The invention encompasses any modifications or alternative embodiments that fall within the scope of the claims.

Claims (15)

1. A processing device comprising:
a master processor;
a system memory;
a slave processor subsystem including:
a slave processor;
a shared memory accessible by said master processor and said slave processor;
an external memory interface allowing said slave processor to access said system memory;
circuitry for receiving a signal for specifying a normal mode for normal operation of the processing device or verification mode for testing the processing device; and
a verification interface for selectively passing system memory accesses either to the system memory or the shared memory responsive to the signal, wherein accesses directed towards the system memory access are passed to said system memory in a normal mode and wherein accesses directed towards the system memory are passed to said shared memory in a verification mode.
2. The processing device of claim 1 wherein said slave processor subsystem further includes a cache memory coupled to said external memory controller and said slave processor.
3. The processing device of claim 1 wherein said verification interface includes a protocol translator for translating between a first protocol associated with memory accesses of said system memory and a second protocol associated with memory accesses of said shared memory.
4. The processing device of claim 1 wherein said verification interface comprises multiplexing circuitry for passing data to said external memory interface from either said system memory or said shared memory responsive to whether said verification interface is in a normal mode or a verification mode.
5. The processing device of claim 4 and further comprising a control interface coupled between said master processor and said shared memory.
6. The processing device of claim 5 wherein said multiplexing circuitry comprises first multiplexing circuitry and further comprising second multiplexing circuitry for passing control signals to said control interface from either said master processor or said external memory interface responsive to whether said verification interface is in a normal mode or a verification mode.
7. The processing device of claim 6 and further comprising a protocol translator for translating between a first protocol associated with memory accesses of said system memory and a second protocol associated with memory accesses of said shared memory.
8. A processing device comprising:
a master processor;
a system memory;
a slave processor subsystem including:
one or more a slave processors;
a shared memory accessible by said master processor and said slave processor;
circuitry for receiving a signal for specifying a normal mode for normal operation of the processing device or verification mode for testing the processing device;
an system memory interface allowing said slave processors to access said system memory; and
a verification interface for selectively passing system memory accesses either to the system memory or the shared memory responsive to the signal, wherein accesses directed towards the system memory access are passed to said system memory in a normal mode and wherein accesses directed towards the system memory are passed to said shared memory in a verification mode.
9. The processing device of claim 8 wherein said system memory interface comprises:
respective external memory interfaces associated with each slave processor; and
a memory arbiter for arbiting between memory accesses generated by each of said external memory interfaces.
10. The processing device of claim 8 wherein said slave processor subsystem further includes cache memories associated with each of said slave processors.
11. The processing device of claim 8 wherein said verification interface includes a protocol translator for translating between a first protocol associated with memory accesses of said system memory and a second protocol associated with memory accesses of said shared memory.
12. The processing device of claim 8 wherein said verification interface comprises multiplexing circuitry for passing data to said system memory interface from either said system memory or said shared memory responsive to whether said verification interface is in a normal mode or a verification mode.
13. The processing device of claim 12 and further comprising a control interface coupled between said master processor and said shared memory.
14. The processing device of claim 13 wherein said multiplexing circuitry comprises first multiplexing circuitry and further comprising second multiplexing circuitry for passing control signals to said control interface from either said master processor or said system memory interface responsive to whether said verification interface is in a normal mode or a verification mode.
15. The processing device of claim 14 and further comprising a protocol translator for translating between a first protocol associated with memory accesses of said system memory and a second protocol associated with memory accesses of said shared memory.
US09/778,495 2000-07-06 2001-02-07 Multi-processor system verification circuitry Expired - Lifetime US7469273B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP00401957A EP1170665B1 (en) 2000-07-06 2000-07-06 Multi-processor system verification circuitry
FR00401957.6 2000-07-06

Publications (2)

Publication Number Publication Date
US20020004823A1 US20020004823A1 (en) 2002-01-10
US7469273B2 true US7469273B2 (en) 2008-12-23

Family

ID=8173761

Family Applications (1)

Application Number Title Priority Date Filing Date
US09/778,495 Expired - Lifetime US7469273B2 (en) 2000-07-06 2001-02-07 Multi-processor system verification circuitry

Country Status (4)

Country Link
US (1) US7469273B2 (en)
EP (1) EP1170665B1 (en)
AT (1) ATE259081T1 (en)
DE (1) DE60008088T2 (en)

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100036940A1 (en) * 2008-08-11 2010-02-11 International Business Machines Corporation Data Processing In A Hybrid Computing Environment
US20100058031A1 (en) * 2008-09-04 2010-03-04 International Business Machines Corporation Executing A Service Program For An Accelerator Application Program In A Hybrid Computing Environment
US20100058356A1 (en) * 2008-09-04 2010-03-04 International Business Machines Corporation Data Processing In A Hybrid Computing Environment
US20100064295A1 (en) * 2008-09-05 2010-03-11 International Business Machines Corporation Executing An Accelerator Application Program In A Hybrid Computing Environment
US20100191823A1 (en) * 2009-01-29 2010-07-29 International Business Machines Corporation Data Processing In A Hybrid Computing Environment
US20100191917A1 (en) * 2009-01-23 2010-07-29 International Business Machines Corporation Administering Registered Virtual Addresses In A Hybrid Computing Environment Including Maintaining A Watch List Of Currently Registered Virtual Addresses By An Operating System
US20100191822A1 (en) * 2009-01-29 2010-07-29 International Business Machines Corporation Broadcasting Data In A Hybrid Computing Environment
US20100191711A1 (en) * 2009-01-28 2010-07-29 International Business Machines Corporation Synchronizing Access To Resources In A Hybrid Computing Environment
US20100191909A1 (en) * 2009-01-26 2010-07-29 International Business Machines Corporation Administering Registered Virtual Addresses In A Hybrid Computing Environment Including Maintaining A Cache Of Ranges Of Currently Registered Virtual Addresses
US20100191923A1 (en) * 2009-01-29 2010-07-29 International Business Machines Corporation Data Processing In A Computing Environment
US20100198997A1 (en) * 2009-02-03 2010-08-05 International Business Machines Corporation Direct Memory Access In A Hybrid Computing Environment
US20100274868A1 (en) * 2009-04-23 2010-10-28 International Business Machines Corporation Direct Memory Access In A Hybrid Computing Environment
US20110035556A1 (en) * 2009-08-07 2011-02-10 International Business Machines Corporation Reducing Remote Reads Of Memory In A Hybrid Computing Environment By Maintaining Remote Memory Values Locally
US20110191785A1 (en) * 2010-02-03 2011-08-04 International Business Machines Corporation Terminating An Accelerator Application Program In A Hybrid Computing Environment
US20110239003A1 (en) * 2010-03-29 2011-09-29 International Business Machines Corporation Direct Injection of Data To Be Transferred In A Hybrid Computing Environment
US8607008B1 (en) 2006-11-01 2013-12-10 Nvidia Corporation System and method for independent invalidation on a per engine basis
US8843880B2 (en) 2009-01-27 2014-09-23 International Business Machines Corporation Software development for a hybrid computing environment
US9015443B2 (en) 2010-04-30 2015-04-21 International Business Machines Corporation Reducing remote reads of memory in a hybrid computing environment
USRE46021E1 (en) * 2007-12-12 2016-05-31 Infineon Technologies Ag System-on-chip with master/slave debug interface
US10592393B1 (en) * 2017-02-28 2020-03-17 American Megatrends International, Llc Firmware debug trace capture

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6789168B2 (en) * 2001-07-13 2004-09-07 Micron Technology, Inc. Embedded DRAM cache
DE10162986B4 (en) * 2001-12-20 2004-01-15 Siemens Ag Connection of networks with different protocols
US7788642B2 (en) * 2005-05-16 2010-08-31 Texas Instruments Incorporated Displaying cache information using mark-up techniques
US7991959B2 (en) * 2005-05-16 2011-08-02 Texas Instruments Incorporated Visualizing contents and states of hierarchical storage systems
US20060259695A1 (en) * 2005-05-16 2006-11-16 Texas Instruments Incorporated Visualizing contents and states of hierarchical storage systems across multiple cores
US7779206B2 (en) * 2005-05-16 2010-08-17 Texas Instruments Incorporated Cache inspection with inspection bypass feature
US7616218B1 (en) * 2005-12-05 2009-11-10 Nvidia Corporation Apparatus, system, and method for clipping graphics primitives
US8347064B1 (en) 2006-09-19 2013-01-01 Nvidia Corporation Memory access techniques in an aperture mapped memory space
US8601223B1 (en) 2006-09-19 2013-12-03 Nvidia Corporation Techniques for servicing fetch requests utilizing coalesing page table entries
US8543792B1 (en) 2006-09-19 2013-09-24 Nvidia Corporation Memory access techniques including coalesing page table entries
US8352709B1 (en) 2006-09-19 2013-01-08 Nvidia Corporation Direct memory access techniques that include caching segmentation data
US8707011B1 (en) 2006-10-24 2014-04-22 Nvidia Corporation Memory access techniques utilizing a set-associative translation lookaside buffer
US8700883B1 (en) 2006-10-24 2014-04-15 Nvidia Corporation Memory access techniques providing for override of a page table
US8706975B1 (en) 2006-11-01 2014-04-22 Nvidia Corporation Memory access management block bind system and method
US8347065B1 (en) * 2006-11-01 2013-01-01 Glasco David B System and method for concurrently managing memory access requests
US8504794B1 (en) 2006-11-01 2013-08-06 Nvidia Corporation Override system and method for memory access management
US8533425B1 (en) 2006-11-01 2013-09-10 Nvidia Corporation Age based miss replay system and method
US8700865B1 (en) 2006-11-02 2014-04-15 Nvidia Corporation Compressed data access system and method
US10146545B2 (en) 2012-03-13 2018-12-04 Nvidia Corporation Translation address cache for a microprocessor
US9880846B2 (en) 2012-04-11 2018-01-30 Nvidia Corporation Improving hit rate of code translation redirection table with replacement strategy based on usage history table of evicted entries
US10241810B2 (en) 2012-05-18 2019-03-26 Nvidia Corporation Instruction-optimizing processor with branch-count table in hardware
US20140189310A1 (en) 2012-12-27 2014-07-03 Nvidia Corporation Fault detection in instruction translations
US10108424B2 (en) 2013-03-14 2018-10-23 Nvidia Corporation Profiling code portions to generate translations
CN111240908B (en) * 2019-12-31 2023-07-25 西安翔腾微电子科技有限公司 Verification method and verification system for processor interface, electronic equipment and storage medium

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5293586A (en) 1988-09-30 1994-03-08 Hitachi, Ltd. Data processing system for development of outline fonts
US5642057A (en) 1990-12-13 1997-06-24 Lsi Logic Corporation Testable embedded microprocessor and method of testing same
US5649184A (en) * 1989-03-20 1997-07-15 Fujitsu Limited Symmetric/asymmetric shared processing operation in a tightly coupled multiprocessor
US5887146A (en) * 1995-08-14 1999-03-23 Data General Corporation Symmetric multiprocessing computer with non-uniform memory access architecture
US6016525A (en) * 1997-03-17 2000-01-18 Lsi Logic Corporation Inter-bus bridge circuit with integrated loopback capability and method for use of same
US6161162A (en) * 1993-12-08 2000-12-12 Nec Corporation Multiprocessor system for enabling shared access to a memory
US6163828A (en) * 1998-05-22 2000-12-19 Lucent Technologies Inc. Methods and apparatus for providing multi-processor access to shared memory
US6240492B1 (en) * 1998-05-22 2001-05-29 International Business Machines Corporation Memory interface for functional unit of integrated system allowing access to dedicated memory and shared memory, and speculative generation of lookahead fetch requests
US6604189B1 (en) * 2000-05-22 2003-08-05 Lsi Logic Corporation Master/slave processor memory inter accessability in an integrated embedded system

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5293586A (en) 1988-09-30 1994-03-08 Hitachi, Ltd. Data processing system for development of outline fonts
US5649184A (en) * 1989-03-20 1997-07-15 Fujitsu Limited Symmetric/asymmetric shared processing operation in a tightly coupled multiprocessor
US5642057A (en) 1990-12-13 1997-06-24 Lsi Logic Corporation Testable embedded microprocessor and method of testing same
US6161162A (en) * 1993-12-08 2000-12-12 Nec Corporation Multiprocessor system for enabling shared access to a memory
US5887146A (en) * 1995-08-14 1999-03-23 Data General Corporation Symmetric multiprocessing computer with non-uniform memory access architecture
US6016525A (en) * 1997-03-17 2000-01-18 Lsi Logic Corporation Inter-bus bridge circuit with integrated loopback capability and method for use of same
US6163828A (en) * 1998-05-22 2000-12-19 Lucent Technologies Inc. Methods and apparatus for providing multi-processor access to shared memory
US6240492B1 (en) * 1998-05-22 2001-05-29 International Business Machines Corporation Memory interface for functional unit of integrated system allowing access to dedicated memory and shared memory, and speculative generation of lookahead fetch requests
US6604189B1 (en) * 2000-05-22 2003-08-05 Lsi Logic Corporation Master/slave processor memory inter accessability in an integrated embedded system

Cited By (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8607008B1 (en) 2006-11-01 2013-12-10 Nvidia Corporation System and method for independent invalidation on a per engine basis
USRE46021E1 (en) * 2007-12-12 2016-05-31 Infineon Technologies Ag System-on-chip with master/slave debug interface
US8145749B2 (en) 2008-08-11 2012-03-27 International Business Machines Corporation Data processing in a hybrid computing environment
US20100036940A1 (en) * 2008-08-11 2010-02-11 International Business Machines Corporation Data Processing In A Hybrid Computing Environment
US8141102B2 (en) 2008-09-04 2012-03-20 International Business Machines Corporation Data processing in a hybrid computing environment
US20100058031A1 (en) * 2008-09-04 2010-03-04 International Business Machines Corporation Executing A Service Program For An Accelerator Application Program In A Hybrid Computing Environment
US20100058356A1 (en) * 2008-09-04 2010-03-04 International Business Machines Corporation Data Processing In A Hybrid Computing Environment
US7984267B2 (en) 2008-09-04 2011-07-19 International Business Machines Corporation Message passing module in hybrid computing system starting and sending operation information to service program for accelerator to execute application program
US20100064295A1 (en) * 2008-09-05 2010-03-11 International Business Machines Corporation Executing An Accelerator Application Program In A Hybrid Computing Environment
US8776084B2 (en) 2008-09-05 2014-07-08 International Business Machines Corporation Executing an accelerator application program in a hybrid computing environment
US8230442B2 (en) 2008-09-05 2012-07-24 International Business Machines Corporation Executing an accelerator application program in a hybrid computing environment
US8424018B2 (en) 2008-09-05 2013-04-16 International Business Machines Corporation Executing an accelerator application program in a hybrid computing environment
US8819389B2 (en) 2009-01-23 2014-08-26 International Business Machines Corporation Administering registered virtual addresses in a hybrid computing environment including maintaining a watch list of currently registered virtual addresses by an operating system
US8527734B2 (en) 2009-01-23 2013-09-03 International Business Machines Corporation Administering registered virtual addresses in a hybrid computing environment including maintaining a watch list of currently registered virtual addresses by an operating system
US20100191917A1 (en) * 2009-01-23 2010-07-29 International Business Machines Corporation Administering Registered Virtual Addresses In A Hybrid Computing Environment Including Maintaining A Watch List Of Currently Registered Virtual Addresses By An Operating System
US20100191909A1 (en) * 2009-01-26 2010-07-29 International Business Machines Corporation Administering Registered Virtual Addresses In A Hybrid Computing Environment Including Maintaining A Cache Of Ranges Of Currently Registered Virtual Addresses
US9286232B2 (en) 2009-01-26 2016-03-15 International Business Machines Corporation Administering registered virtual addresses in a hybrid computing environment including maintaining a cache of ranges of currently registered virtual addresses
US8843880B2 (en) 2009-01-27 2014-09-23 International Business Machines Corporation Software development for a hybrid computing environment
US20100191711A1 (en) * 2009-01-28 2010-07-29 International Business Machines Corporation Synchronizing Access To Resources In A Hybrid Computing Environment
US9158594B2 (en) 2009-01-28 2015-10-13 International Business Machines Corporation Synchronizing access to resources in a hybrid computing environment
US8255909B2 (en) 2009-01-28 2012-08-28 International Business Machines Corporation Synchronizing access to resources in a hybrid computing environment
US8001206B2 (en) 2009-01-29 2011-08-16 International Business Machines Corporation Broadcasting data in a hybrid computing environment
US9170864B2 (en) * 2009-01-29 2015-10-27 International Business Machines Corporation Data processing in a hybrid computing environment
US20100191923A1 (en) * 2009-01-29 2010-07-29 International Business Machines Corporation Data Processing In A Computing Environment
US20100191822A1 (en) * 2009-01-29 2010-07-29 International Business Machines Corporation Broadcasting Data In A Hybrid Computing Environment
US20100191823A1 (en) * 2009-01-29 2010-07-29 International Business Machines Corporation Data Processing In A Hybrid Computing Environment
US8010718B2 (en) 2009-02-03 2011-08-30 International Business Machines Corporation Direct memory access in a hybrid computing environment
US20100198997A1 (en) * 2009-02-03 2010-08-05 International Business Machines Corporation Direct Memory Access In A Hybrid Computing Environment
US8037217B2 (en) 2009-04-23 2011-10-11 International Business Machines Corporation Direct memory access in a hybrid computing environment
US20100274868A1 (en) * 2009-04-23 2010-10-28 International Business Machines Corporation Direct Memory Access In A Hybrid Computing Environment
US8539166B2 (en) 2009-08-07 2013-09-17 International Business Machines Corporation Reducing remote reads of memory in a hybrid computing environment by maintaining remote memory values locally
US8180972B2 (en) 2009-08-07 2012-05-15 International Business Machines Corporation Reducing remote reads of memory in a hybrid computing environment by maintaining remote memory values locally
US20110035556A1 (en) * 2009-08-07 2011-02-10 International Business Machines Corporation Reducing Remote Reads Of Memory In A Hybrid Computing Environment By Maintaining Remote Memory Values Locally
US20110191785A1 (en) * 2010-02-03 2011-08-04 International Business Machines Corporation Terminating An Accelerator Application Program In A Hybrid Computing Environment
US9417905B2 (en) 2010-02-03 2016-08-16 International Business Machines Corporation Terminating an accelerator application program in a hybrid computing environment
US8578132B2 (en) 2010-03-29 2013-11-05 International Business Machines Corporation Direct injection of data to be transferred in a hybrid computing environment
US20110239003A1 (en) * 2010-03-29 2011-09-29 International Business Machines Corporation Direct Injection of Data To Be Transferred In A Hybrid Computing Environment
US9015443B2 (en) 2010-04-30 2015-04-21 International Business Machines Corporation Reducing remote reads of memory in a hybrid computing environment
US10592393B1 (en) * 2017-02-28 2020-03-17 American Megatrends International, Llc Firmware debug trace capture

Also Published As

Publication number Publication date
EP1170665A1 (en) 2002-01-09
EP1170665B1 (en) 2004-02-04
DE60008088T2 (en) 2004-12-23
US20020004823A1 (en) 2002-01-10
ATE259081T1 (en) 2004-02-15
DE60008088D1 (en) 2004-03-11

Similar Documents

Publication Publication Date Title
US7469273B2 (en) Multi-processor system verification circuitry
CN113330322B (en) Automated test equipment using system-on-chip test controller
US7689867B2 (en) Multiprocessor breakpoint
US7003691B2 (en) Method and apparatus for seeding differences in lock-stepped processors
US8136001B2 (en) Technique for initializing data and instructions for core functional pattern generation in multi-core processor
US6424926B1 (en) Bus signature analyzer and behavioral functional test method
US7624312B2 (en) System, apparatus, computer program product for performing operational validation with limited CPU use of a communications network
US6983398B2 (en) Testing processors
KR20130101927A (en) Multi-core soc having a function of debugging
MX2008011173A (en) At-speed multi-port memory array test method and apparatus.
US9589672B2 (en) Power-aware memory self-test unit
GB2563970A (en) Data processing
US5610927A (en) Integrated circuit control
JP2004178590A (en) Address range comparator for detecting memory accesses of multi sizes by data matching qualification and full or partial ovrlap
US10489261B2 (en) Efficient testing of direct memory address translation
US5712822A (en) Microprocessor memory test circuit and method
Jone et al. An efficient BIST method for distributed small buffers
CN109213638B (en) Semiconductor device with a plurality of semiconductor chips
Floridia et al. Parallel software-based self-test suite for multi-core system-on-chip: Migration from single-core to multi-core automotive microcontrollers
KR20030055150A (en) Microprocessor and processing method of microprocessor
KR20210080398A (en) Read-only memory testing with built-in memory self-test controller
Peng et al. An on-chip debugging method based on bus access
KR20140113175A (en) Bus Protocol Checker, System on Chip having the same and Method for checking bus protocol
US20100079162A1 (en) Data processing device and methods thereof
US10120737B2 (en) Apparatus for detecting bugs in logic-based processing devices

Legal Events

Date Code Title Description
AS Assignment

Owner name: TEXAS INSTRUMENTS INCORPORATED, TEXAS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ANDERSON, MARQUETTE JOHN;BEDERR, HAKIM;REEL/FRAME:011537/0468

Effective date: 20000913

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 12