US7403620B2 - Cyphering/decyphering performed by an integrated circuit - Google Patents

Cyphering/decyphering performed by an integrated circuit Download PDF

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US7403620B2
US7403620B2 US10/611,254 US61125403A US7403620B2 US 7403620 B2 US7403620 B2 US 7403620B2 US 61125403 A US61125403 A US 61125403A US 7403620 B2 US7403620 B2 US 7403620B2
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cyphering
random number
block
code
blocks
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US20040028224A1 (en
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Pierre-Yvan Liardet
Fabrice Romain
Yannick Teglia
Laurence Sirtori
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STMicroelectronics SA
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STMicroelectronics SA
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
    • H04L9/0631—Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/002—Countermeasures against attacks on cryptographic mechanisms
    • H04L9/003—Countermeasures against attacks on cryptographic mechanisms for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/04—Masking or blinding
    • H04L2209/046—Masking or blinding of operations, operands or results of the operations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/08—Randomization, e.g. dummy operations or using noise

Definitions

  • the present invention relates to the cyphering of digital data by means of algorithms intended to mask original data to make them undetectable by a possible pirate.
  • the present invention more specifically relates to algorithms implementing a same transformation on different parts of the data to be coded.
  • the cyphering/decyphering algorithms to which the present invention applies are generally executed by integrated circuits, either by means of state machines in wired logic, or by means of microprocessors executing a program in memory (generally a ROM). Such algorithms use secret keys specific to integrated circuits or to the user, which are exploited by the algorithm to code the data.
  • AES Advanced Encryption Standard
  • FIG. 1 illustrates in a simplified flowchart the main steps of a conventional AES-type algorithm. Only the cyphering will be described, the decyphering using the inverse transformations.
  • This algorithm cyphers a word or code S 0 of a predetermined number of bits (generally, 128 bits) into another word or code S n of same size.
  • the data to be cyphered are in fact formed of several words or codes resulting from a previous division of the data into words all having the same size.
  • the cyphering and the decyphering are based on a secret key, the length of which (generally from 128 to 256 bits) conditions the cyphering security.
  • each step of an AES-type algorithm processes a matrix of four lines and four columns representing a word and each element of which is a byte or block of the processed 128-bit code.
  • each step to a state considered as being a matrix.
  • 11 sub-keys each also comprised of 128 bits are first generated based on the secret key over 128 bits. More generally, based on a secret key of a number m of bits, n+1 sub-keys K 0 , . . . Ki, . . . Kn of m bits each are derived. These sub-keys are intended to be used by the algorithm as will be described hereafter in relation with FIG. 1 .
  • the algorithm starts from an initial state (block 1 , STATE INIT) S 0 of the code or data word to be cyphered.
  • a first phase of the cyphering process is a so-called “bleaching” operation (block 2 , ADDROUNDKEY) which consists of performing an XOR-type combination of initial state S 0 with first sub-key K 0 .
  • a first intermediary state S 1 is obtained.
  • a second phase of the cyphering process consists of performing several turns or cycles of a same transformation T involving, at each turn, the state S i ⁇ 1 , obtained at the preceding turn and a current sub-key Ki.
  • the number of turns of transformation T corresponds to n ⁇ 1, that is, to the number of derived sub-keys, minus 2.
  • FIG. 2 illustrates in more detail these four operations on a matrix 20 of four lines and four columns of binary bytes to which an AES-type algorithm applies.
  • a first step (block 3 , SHIFTROWS) consists of performing a rotation on the last three lines of matrix 20 .
  • First line 201 of matrix 20 is left unchanged.
  • Second line 202 is rotated by one byte.
  • Third line 203 is rotated by two bytes.
  • Fourth line 204 is rotated by three bytes.
  • a second step (block 4 , SUBBYTES) of a turn of transformation T is a non-linear transformation in which each byte of matrix 20 ′ forming the current state is replaced with its image taken from a substitution box (SBOX).
  • substitution box SBOX is obtained by two successive transformations.
  • a first transformation (block 41 , INV) consists of inverting the considered byte (the element of matrix 20 ′) in the finite body of order 2 8 (to correspond to the byte), byte 00 forming its own image. This inversion is followed by an affine transformation (block 42 , AFFINE).
  • the third step (block 5 , MIXCOLUMNS) of the turn of transformation T consists of considering each column of matrix 20 ′′ resulting from the preceding step as a polynomial on the finite body of order 2 8 , and of multiplying each of these polynomials by a combination polynomial P[X] modulo a polynomial M[X].
  • the last and fourth step of the turn of transformation T of rank i consists of applying sub-key Ki to matrix 20 ′′ of the previous state to obtain a matrix 20 ′′′, in which each element of matrix 20 ′′ has been combined by XOR, bit to bit, with sub-key Ki (block 6 , ADDROUNDKEY).
  • Step 6 is the same as step 2 of the first cyphering phase, but performed with a different sub-key.
  • the four steps of the turn transformation are repeated n ⁇ 1 times, that is, after step 6 , it is returned to step 3 to perform a new turn with a next key.
  • the third phase of the cyphering algorithm ( FIG. 1 ) consists, in a way, in a last turn, slightly modified as compared to that illustrated in FIG. 2 .
  • the steps of the turn transformation are reproduced except for the third one (MIXCOLUMNS). This amounts to successively performing steps 7 , 8 , and 9 corresponding to previously-described steps 3 , 4 , and 6 with, as the key for step 9 , the last sub-key Kn.
  • Such an attack known as a DPA Differential Power Analysis
  • a DPA Different Power Analysis
  • a statistic correlation curve is established along time between the power consumption of the product for the message cyphering and an intermediary value calculated by the circuit.
  • a known solution to make the algorithms more resistant against differential power analysis attacks of the integrated circuit consists of involving a random number in the execution of the algorithm.
  • the use of a random value consists of masking the state at the beginning of the algorithm by this random value and of restoring the expected result at the end of the algorithm.
  • FIG. 3 partially and very schematically illustrates a first known technique of introduction of a random number Rd in the execution of an AES-type algorithm.
  • a bit-to-bit XOR type combination (block 12 , +) with a random number Rd is performed. This number is thus introduced before step 2 of combination with first sub-key K 0 .
  • This random number Rd must then be taken into account at some stages of the algorithm.
  • SUBBYTES non-linear transformation steps 4 and 8
  • SBOX Rd substitution box taking the random number into account must be used.
  • step 6 an XOR-type combination (block 13 , +) with number Rd must be performed. Moreover, after step 13 , the obtained result is combined (block 15 , +) by XOR with an amount MC(SR(Rd)) corresponding to the application of the row shifting SR (SHIFTROWS) and column mixing MC (MIXCOLUMNS) functions to number Rd.
  • substitution box SBOX Rd for each byte of the state requires 16 boxes of 256 bytes, which amounts to 4 kilobytes of memory. Such a memory is far from being negligible when integrated, for example, in a smart card.
  • FIG. 4 illustrates a second conventional solution to involve a random value in a cyphering algorithm of AES type. This solution is described in article “An implementation of DES and AES, secure against some attacks” by M. L. Akkar and C. Giraud, published at the CHES conference 2001 (Springer-Verlag editors).
  • Second random value Rd 2 is introduced into the turns of the transformation, be it the n ⁇ 1 identical transformations T or the last transformation T′.
  • a first transformation (block 241 , INV) consists of inverting each byte of the matrix resulting from step 25 . Then, the product (byte by byte modulo an irreducible polynomial) of initial state S i by the inverse (Rd 2 ⁇ 1 ) of the random value is added (XOR) to this inverse matrix (block 242 , +). The result is then multiplied (block 243 , X) by random value Rd 2 . There again, this is a polynomial multiplication. Finally, the last byte substitution step 24 of the matrix consists in an affine transformation 244 (AFFINE). At the end of step 24 , the resulting matrix is submitted to the step of addition of the corresponding sub-key (step 6 or 9 ).
  • AFFINE affine transformation 244
  • step 5 MIXCOLUMNS
  • step 6 the step following step 24 is step 5 (MIXCOLUMNS).
  • step 6 the obtained result is combined (block 26 , +) by XOR with value Rd 1 .
  • the result of addition 26 is combined (block 27 ), still by XOR, with result (MC(AF(SR(Rd 1 )))) of the polynomial column mixing processing (MC) of affine transformation AF applied to the row shifting SR applied to value Rd 1 .
  • step 9 the step following step 24 is step 9 with key Kn.
  • the obtained result is combined (block 29 , +) by XOR with the result (AF(SR(Rd 1 ))) of affine transformation AF applied to row shifting SR applied to value Rd 1 .
  • the output of block 29 provides the state to be set up by step 10 .
  • the problem of the processing by a random number is essentially due to the fact that, in an algorithm of the type to which the present invention applies, the substitution operation is a non-linear operation.
  • the present invention aims at providing a novel solution to the introduction of at least one random value in an AES-type cyphering algorithm which overcomes the disadvantages of known solutions. More generally, the present invention aims at providing the introduction of at least one random value in an algorithm submitting a code or input word, divided into blocks, several times to the same transformation (by a substitution matrix) with different keys.
  • the present invention also aims at providing a solution which reduces the number of times that a substitution box must be calculated and/or stored.
  • the present invention also aims at reducing the calculation time necessary to the execution of the algorithm after introduction of the random number.
  • the present invention provides a cyphering/decyphering method, by an integrated circuit, of a digital input code by means of several keys, comprising:
  • the operands being masked, upon execution of the method, by means of at least one first random number having the value of said code and all the blocks of which have the same size by combining, by an XOR-type function, the input and output blocks of the non-linear transformation with said random number.
  • the input code is combined with a second random number of same dimension as the code.
  • said non-linear transformation comprises using a box of substitution of the input code blocks, calculated with a third random number of same length as said code and all the blocks of which have the same value.
  • said box respects the fact that the transformation of an input code, previously combined by XOR with the first random number, corresponds to the result of the combination by XOR of this input code with said third random number.
  • the method is applied to an AES-type cyphering algorithm.
  • said first random number is changed at each cyphering turn.
  • said second random number is changed at each cyphering of new data.
  • said third random number is changed at each cyphering turn.
  • the present invention also provides an integrated circuit comprising a block for cyphering/deciphering by turn input data divided into blocks of same dimensions, comprising:
  • FIG. 1 previously described, illustrates in a simplified flowchart a conventional cyphering method of the type to which the present invention applies;
  • FIG. 2 previously described, illustrates the processings performed on a matrix state in a turn of a transformation of the method of FIG. 1 ;
  • FIG. 3 shows the steps of a first conventional method of taking into account of a random number in a cyphering algorithm of the type illustrated in FIG. 1 ;
  • FIG. 4 shows a second conventional solution of introduction of random numbers in a cyphering algorithm of the type shown in FIG. 1 ;
  • FIG. 5 illustrates in a simplified flowchart an embodiment of a cyphering algorithm according to the present invention.
  • FIG. 6 shows, in a simplified flowchart, an embodiment of a decyphering method according to the present invention.
  • a random value having the same size as the state to be cyphered (the matrix) is used for the transformations processing several bytes at the same time or which mix them together, as is the case for transformations of column mixing, sub-key introduction, and row shifting type.
  • this random value is not used for non-linear functions, such as those implemented for the byte substitution by a substitution box in the considered case.
  • a substitution box is masked by another random value, the bytes of which (or more generally, the blocks of a size corresponding to the size of the blocks of the code taken into account in the substitution box) are all identical.
  • a masking operation is efficient since, due to the complete masking of the functions operating over the entire block, it is not possible for a pirate to exploit this specificity through a correlation function.
  • a pseudo-random value linked to this random value, is also used to mask the substitution box.
  • FIG. 5 shows a flowchart of an implementation mode of an AES-type algorithm, masked by means of random and/or pseudo-random values according to the present invention.
  • State S 0 corresponds to the code (data) to be cyphered by the algorithm.
  • First step 41 comprises performing an XOR-type combination of state S 0 with a random value R having the same size as state S 0 (for example, 128 bits).
  • a conventional step 32 of sub-key addition (block 32 , ADDROUNDKEY) by an XOR-type combination of first sub-key K 0 with the result of the preceding step is executed.
  • the obtained state corresponds to state S i +R.
  • the second phase of the cyphering method comprising executing n ⁇ 1 turns of a same transformation T is then entered.
  • This transformation involves the steps of the conventional process (for example, AES) which are desired to be masked by at least one random value.
  • these are row shifting step 33 (SHIFTROWS), step 34 (SUBBYTES) of byte substitution by means of a substitution box SBOX, column mixing step 35 (MIXCOLUMNS), and step 36 of XOR combination (ADDROUNDKEY) with sub-key Ki of rank i.
  • the number (for example, 16) of bytes of each value corresponds to the number of bytes of a processed state (fore example, 128 bits).
  • state SR(S i )+SR(R) is combined (block 42 ) with a value of same size (R 1 +SR(R)) corresponding to the application of the row shifting to random value R (SR(R)) combined, byte by byte, by XOR with random value R 1 .
  • the state is masked by a value of same size, each byte of which has the same random value.
  • Step 34 of byte-by-byte substitution by means of substitution box SBOX R1,R2 is then performed.
  • This box is, according to the present invention, a function of value R 2 and is linked to value R 1 , respecting the following relation:
  • SB(S i +R 1 ) SBOX(S i )+R 2 , where SBOX represents the substitution box of the algorithm that is desired to be masked and SB designates the byte substitution function (SUBBYTES).
  • SUBBYTES byte substitution function
  • step 34 To the result (SB(SR(S i ))+R 2 ) of step 34 which corresponds to a state masked by value R 2 (each byte of the matrix is masked by a byte of same value), an XOR-type combination is applied (block 43 ) with XOR combination R 2 +R (byte by byte) of the value R over 128 bits and of byte R 2 .
  • step 44 ends with step 44 at the end of which, according to rank i, it is returned to step 33 for a new iteration, or it is proceeded to step row shifting 37 (SHIFTROWS) of the last transformation T′.
  • the present invention comprises interposing, between some steps of the algorithm, the execution of which is desired to be masked by random values, logic combinations of the matrixes processed by values R 1 and R 2 .
  • the transformation by substitution matrix 38 is identical to that described in relation with step 34 , but framed by combinations 45 and 46 . These combinations are identical to previously-described combinations 42 and 43 , upstream and downstream of transformation 34 .
  • An advantage of the present invention is that quantities R 1 and R 2 as well as substitution box SBOX can be recalculated at each turn T of the cyclic transformation or at each cyphering or decyphering of the input data by the complete algorithm.
  • Another advantage of the present invention is that a memory corresponding to twice the matrix to be processed is sufficient to store the new substitution boxes (the old one and the new one) since said matrixes are combined with a random value, the size of which corresponds to that of an element of the matrix.
  • FIG. 6 shows, in the form of a simplified flowchart, an embodiment of an algorithm for decyphering data Sn according to the present invention.
  • the decyphering resumes the steps inverse of those of the cyphering except for the step of introduction of the keys or sub-keys Ki, which are performed in the reverse order.
  • the initial state (block 51 , STATE INIT) here corresponds to a cyphered or encrypted state (S n ) of the data.
  • the initial state is first combined (block 61 ) with a random quantity R having the same size as the initial data. Then, the obtained state S n +R is combined (block 52 , ADDROUNDKEY) with the sub-key Kn which corresponds to the last portion of the cyphering key (in this example, the last byte). The obtained state S n ⁇ 1 +R is then submitted to n ⁇ 1 cycles of a same decyphering transformation taking into account at each turn a sub-key Ki of lower rank.
  • steps 57 , 58 , and 59 inverse of cyphering steps 37 , 38 , and 39 and corresponding to the conventional steps of the decyphering method are successively applied, interposing the same combination steps 65 , 66 , and 67 as upon cyphering.
  • the present invention is likely to have various alterations, modifications, and improvements which will readily occur to those skilled in the art.
  • the present invention which has been described hereabove in relation with the AES-type cyphering algorithm may be transposed to any cyphering algorithm, the input code of which is divided into blocks of identical sizes to be ciphered, each block being submitted to a same non-linear transformation.
  • the adaptation of the present invention and of the sizes of the random quantities and of the used keys is within the abilities of those skilled in the art. It will be ascertained to respect a number of sub-keys corresponding to the numbers of turns and a size of random quantity R corresponding to the size of the sub-keys, and thus of the blocks. Moreover, the numbers indicated as being random numbers may originate from a pseudo-random generator.
  • a specific example of application of the present invention relates to the implementation of an AES-type cyphering/decyphering algorithm in a smart card.

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EP1379023A1 (fr) 2004-01-07

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