US7368949B2 - Output driver and output driving method for enhancing initial output data using timing - Google Patents

Output driver and output driving method for enhancing initial output data using timing Download PDF

Info

Publication number
US7368949B2
US7368949B2 US11/561,765 US56176506A US7368949B2 US 7368949 B2 US7368949 B2 US 7368949B2 US 56176506 A US56176506 A US 56176506A US 7368949 B2 US7368949 B2 US 7368949B2
Authority
US
United States
Prior art keywords
data
output
selection signal
input data
logic state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US11/561,765
Other versions
US20070115752A1 (en
Inventor
Young-Soo Sohn
Jung-hwan Choi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Assigned to SAMSUNG ELECTRONICS CO., LTD reassignment SAMSUNG ELECTRONICS CO., LTD ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SOHN, YOUNG-SOO, CHOI, JUNG-HWAN
Publication of US20070115752A1 publication Critical patent/US20070115752A1/en
Application granted granted Critical
Publication of US7368949B2 publication Critical patent/US7368949B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069—I/O lines read out arrangements

Definitions

  • the present invention relates to a data output driver and output driving method, and more particularly to an output driver and output driving method, which compensate for the attenuation of transmission data during data communication.
  • Transmission data generated by a transmission device is transmitted to a reception device through a transmission line.
  • the transmission device is typically provided with an output driver for outputting the transmission data.
  • Transmission data is composed of a plurality of data bits to be consecutively transmitted.
  • the phenomenon due to the previous data bit, may be referred to as Inter-Symbol Interference (hereinafter referred to as “ISI”). Due to ISI, attenuation of transmission data may occur.
  • the ISI may further increase when the data bit having the logic state differing from that of the previous data bit is transmitted immediately after several data bits having the same logic state have been transmitted.
  • FIG. 1 is a diagram showing an example of an output driver.
  • FIG. 2 is a timing diagram showing the signals of the output driver of FIG. 1 .
  • a bit shifter 11 shifts input data IDAT 1 by one bit period and generates shifted data SDAT 1 .
  • a data adder 13 performs an operation of Equation [1] and generates output data ODAT 1 , V ( ODAT 1) ⁇ a*V ( SDAT 1) [1] where V(ODAT 1 ), V(IDAT 1 ) AND V(SDAT 1 ) denote the voltage levels of the output data ODAT 1 , the input data IDAT 1 and the shifted data SDAT 1 , respectively. Further, “a” denotes a positive constant.
  • the swing range of one bit value increases whenever the logic state of the output data ODAT 1 is transitioned. Therefore, the attenuation of the output data ODAT 1 is mitigated due to the increasing swing range.
  • FIG. 3 is a diagram showing another example of an output driver.
  • FIG. 4 is a timing diagram showing the signals of the output driver of FIG. 3 .
  • a delay unit 21 delays input data IDAT 2 and generates delayed data DDAT 2 .
  • the initial voltage level of the output data ODAT 2 is intensified whenever the logic state of the output data ODAT 2 is transitioned.
  • the attenuation of the output data ODAT 2 is mitigated due to the intensified initial voltage level.
  • the input data IDAT 1 and IDAT 2 and the output data ODAT 1 and ODAT 2 operate at a high voltage higher than a voltage level Vh in a logic H state, and at a low voltage lower than a voltage level V1 in a logic L state.
  • the output drivers of FIGS. 1 and 3 need to include circuits for generating the high voltage and the low voltage.
  • an output driver for generating output data comprises a selection signal generation unit for generating a selection signal based on input data having consecutively valid data bits during a plurality of consecutive bit periods, the selection signal being activated at a transition point of the input data, generated after being maintained in a same logic state during a number of bit periods that is equal to or greater than a predetermined duration number.
  • the output driver comprises a reference data generation unit for delaying the input data by a delay time shorter than one bit period, and generating reference data, and a selection unit, electrically coupled to the selection signal generation unit and the reference data generation unit, driven to transition a logic state of the output data depending on a transition of a logic state of any one of the input data and the reference data in response to the selection signal.
  • an output driving method of generating output data comprises generating a selection signal based on input data having a plurality of consecutive data bits, the selection signal being activated at a transition point of the input data, the transition point generated after the input data has been maintained in a same logic state during a number of bit periods that is equal to or greater than a predetermined duration number, generating reference data as the input data delayed by a delay time shorter than one bit period, and transitioning a logic state of the output data depending on a transition of a logic state of any one of the input data and the reference data in response to the selection signal.
  • FIG. 1 is a diagram showing an example of a conventional output driver
  • FIG. 2 is a timing diagram showing the principal signals of the output driver of FIG. 1 ;
  • FIG. 3 is a diagram showing another example of a conventional output driver
  • FIG. 4 is a timing diagram showing the principal signals of the output driver of FIG. 3 ;
  • FIG. 5 is a diagram showing an output driver according to an embodiment of the present invention.
  • FIG. 6 is a timing diagram showing the principal signals of the output driver of FIG. 5 ;
  • FIG. 7 is a graph showing the effect of the output driver according to an embodiment of the present invention.
  • FIG. 5 is a diagram showing an output driver 100 according to an embodiment of the present invention.
  • FIG. 6 is a timing diagram showing signals of the output driver 100 of FIG. 5 .
  • Reference character CLK denotes a clock signal used to indicate a bit period pBIT.
  • the output driver 100 drives output data ODAT corresponding to input data IDAT.
  • the input data IDAT has consecutively valid data bits for a plurality of consecutive bit periods.
  • a single data bit is assigned to a single bit period pBIT.
  • the output driver 100 includes a selection signal generation unit 110 , a reference data generation unit 130 and a selection unit 150 .
  • the selection signal generation unit 110 receives the input data IDAT, and generates a selection signal /TX based on the input data IDAT.
  • the selection signal /TX is activated to a logic L state at the transition point of the input data IDAT, generated after being maintained in the same logic state for a number of bit periods that is equal to or greater than a predetermined duration number, e.g., 2.
  • the selection signal generation unit 110 includes a bit shifter 111 and a logic operation means 113 .
  • the bit shifter 111 delays the received input data IDAT by one bit period pBIT.
  • the shifted data SDAT output from the bit shifter 111 is shifted from the input data IDAT by one bit period, as shown in FIG. 6 .
  • the logic operation means 113 performs a logic operation on the input data IDAT and the shifted data SDAT, thus generating the selection signal /TX.
  • the logic operation means 113 is an Exclusive-OR logic gate for performing an Exclusive-OR operation on the input data IDAT and the shifted data SDAT. In an interval during which the input data IDAT and the shifted data SDAT have the same logic state, the selection signal /TX is transitioned to a logic L state. Further, in an interval during which the input data IDAT and the shifted data SDAT have different logic states, the selection signal /TX is transitioned to a logic H state.
  • the transition of the logic state of the selection signal /TX occurs after being delayed from that of the input data IDAT or the shifted data SDA by a predetermined period (each “pd” in FIG. 6 ).
  • the selection signal /TX is activated to a logic L state.
  • the selection signal /TX is deactivated to a logic H state.
  • the reference data generation unit 130 delays the input data IDAT by a predetermined delay time (refer to td in FIG. 6 ), thus generating reference data RDAT.
  • the delay time td is shorter than the bit period pBIT.
  • the selection unit 150 generates output data ODAT that is transitioned depending on the transition of the logic state of any one of the input data IDAT and the reference data RDAT in response to the selection signal /TX.
  • the transition of the logic state of the output data ODAT follows the transition of the input data IDAT.
  • the logic state of the output data ODAT is also transitioned to a logic H state in response to the transition of the input data IDAT to a logic H state (refer to t 6 and t 7 in FIG. 6 ).
  • the logic state of the output data ODAT is also transitioned to a logic L state in response to the transition of the input data IDAT to a logic L state (refer to time t 8 in FIG. 6 ).
  • the transition of the logic state of the output data ODAT follows the transition of the reference data RDAT.
  • the logic state of the output data ODAT is also transitioned to a logic H state in response to the transition of the reference data RDAT to a logic H state (refer to t 9 in FIG. 6 ).
  • the logic state of the output data ODAT is transitioned to a logic L state in response to the transition of the reference data RDAT to a logic L state (refer to t 10 and t 11 in FIG. 6 ).
  • the logic state of the output data ODAT is transitioned in response to the input data IDAT. As shown in FIG. 6 , the logic state of the output data ODAT is transitioned earlier than the reference data RDAT by the delay time td. Accordingly, the attenuation of data that may occur in the output data ODAT can be mitigated.
  • the logic state of the input data IDAT is transitioned at each bit period, the logic state of the output data ODAT is transitioned depending on the reference data RDAT; the output data ODAT is not transitioned in advance.
  • Such an operation is performed in consideration of the fact that the attenuation of transmission data is relatively low when the logic state of the transmission data is transitioned at each bit. In this case, a period secured for data that is transitioned at each bit can be sufficiently assigned as one bit period.
  • FIG. 7 is a graph showing the effect of the output driver according to an embodiment of the present invention. As shown in FIG. 7 , the logic state of the output data ODAT is transitioned in advance in response to the input data IDAT, not the reference data RDAT. The eye window of the output data ODAT increases compared to that of the case where the enhancement of initial data is not performed.
  • the input data IDAT and the output data ODAT are not needed to be driven to a voltage level higher than the voltage level Vh in a logic H state, nor a voltage level lower than the voltage level Vl in a logic L state, so as to enhance the initial input or output data.
  • the output driver and output driving method according to an embodiment of the present invention cause the transition of the logic state of the output data ODAT in advance of the reference data RDAT, thus generating an effect similar to the enhancement of initial data. Therefore, the output driver does not require circuits for generating a high voltage higher than a typical high voltage level nor a low voltage lower than a typical low voltage level.
  • output data is generated by the selection unit. Therefore, the capacitance of the output stage of the output driver decreases compared to the conventional output drivers in FIGS. 1 and 3 .
  • the duration number is 2.
  • the number of bit periods shifted by the bit shifter and/or the construction of a logic operation means are changeable, so that the duration number can be changed to, for example, 1, or a number equal to or greater than 3.

Abstract

An output driver for enhancing initial output data using timing includes a selection signal generation unit for generating a selection signal, a reference data generation unit for generating reference data, and a selection unit. The selection signal is activated at the transition point of the input data, generated after being maintained in a same logic state during a number of bit periods that is equal to or greater than a predetermined duration number. The reference data is delayed from the input data by a delay time shorter than one bit period. The selection unit is driven to transition the logic state of the output data depending on the transition of the logic state of any one of the input data and the reference data in response to the selection signal.

Description

CROSS-REFERENCE TO RELATED APPLICATION
This application claims priority to Korean Patent Application No. 10-2005-110518, filed on Nov. 18, 2005, in the Korean Intellectual Property Office, the disclosure of which is herein incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data output driver and output driving method, and more particularly to an output driver and output driving method, which compensate for the attenuation of transmission data during data communication.
2. Description of Related Art
Transmission data generated by a transmission device is transmitted to a reception device through a transmission line. The transmission device is typically provided with an output driver for outputting the transmission data. Transmission data is composed of a plurality of data bits to be consecutively transmitted. In the case of a data bit having a logic state differing from that of a previous data bit, there may occur a phenomenon where a rising or falling edge of the data bit is not sufficiently developed. The phenomenon, due to the previous data bit, may be referred to as Inter-Symbol Interference (hereinafter referred to as “ISI”). Due to ISI, attenuation of transmission data may occur. The ISI may further increase when the data bit having the logic state differing from that of the previous data bit is transmitted immediately after several data bits having the same logic state have been transmitted.
Various types of output drivers for compensating for the attenuation of transmission data caused by ISI have been developed.
FIG. 1 is a diagram showing an example of an output driver. FIG. 2 is a timing diagram showing the signals of the output driver of FIG. 1.
In an output driver 10 in FIG. 1, a bit shifter 11 shifts input data IDAT1 by one bit period and generates shifted data SDAT1. Further, a data adder 13 performs an operation of Equation [1] and generates output data ODAT1,
V(ODAT1)−a*V(SDAT1)   [1]
where V(ODAT1), V(IDAT1) AND V(SDAT1) denote the voltage levels of the output data ODAT1, the input data IDAT1 and the shifted data SDAT1, respectively. Further, “a” denotes a positive constant.
As shown in FIG. 2, in the output data ODAT1, the swing range of one bit value increases whenever the logic state of the output data ODAT1 is transitioned. Therefore, the attenuation of the output data ODAT1 is mitigated due to the increasing swing range.
FIG. 3 is a diagram showing another example of an output driver. FIG. 4 is a timing diagram showing the signals of the output driver of FIG. 3.
In the output driver 20 of FIG. 3, a delay unit 21 delays input data IDAT2 and generates delayed data DDAT2. Further, a data adder 23 performs an operation of Equation [2] and generates output data ODAT2,
V(ODAT2)=V(IDAT2)−b*V(DDAT2)   [2]
where V(ODAT2, V(IDAT2) and V(DDAT2) denote the voltage levels of the output data ODAT2, the input data IDAT2 and the delayed data DDAT2, respectively. Further, “b” denotes a positive constant.
As shown in FIG. 4, the initial voltage level of the output data ODAT2 is intensified whenever the logic state of the output data ODAT2 is transitioned. The attenuation of the output data ODAT2 is mitigated due to the intensified initial voltage level.
In the output drivers shown in FIGS. 1 and 3, the input data IDAT1 and IDAT2 and the output data ODAT1 and ODAT2 operate at a high voltage higher than a voltage level Vh in a logic H state, and at a low voltage lower than a voltage level V1 in a logic L state. The output drivers of FIGS. 1 and 3 need to include circuits for generating the high voltage and the low voltage.
Therefore, a need exists for an output driver and output driving method that compensate for the attenuation of transmission data during data communication without circuits for generating the high voltage and the low voltage.
SUMMARY OF THE INVENTION
In accordance with an embodiment of the present invention an output driver for generating output data comprises a selection signal generation unit for generating a selection signal based on input data having consecutively valid data bits during a plurality of consecutive bit periods, the selection signal being activated at a transition point of the input data, generated after being maintained in a same logic state during a number of bit periods that is equal to or greater than a predetermined duration number. The output driver comprises a reference data generation unit for delaying the input data by a delay time shorter than one bit period, and generating reference data, and a selection unit, electrically coupled to the selection signal generation unit and the reference data generation unit, driven to transition a logic state of the output data depending on a transition of a logic state of any one of the input data and the reference data in response to the selection signal.
In accordance with an embodiment of the present invention an output driving method of generating output data comprises generating a selection signal based on input data having a plurality of consecutive data bits, the selection signal being activated at a transition point of the input data, the transition point generated after the input data has been maintained in a same logic state during a number of bit periods that is equal to or greater than a predetermined duration number, generating reference data as the input data delayed by a delay time shorter than one bit period, and transitioning a logic state of the output data depending on a transition of a logic state of any one of the input data and the reference data in response to the selection signal.
BRIEF DESCRIPTION OF THE DRAWINGS
Embodiments of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a diagram showing an example of a conventional output driver;
FIG. 2 is a timing diagram showing the principal signals of the output driver of FIG. 1;
FIG. 3 is a diagram showing another example of a conventional output driver;
FIG. 4 is a timing diagram showing the principal signals of the output driver of FIG. 3;
FIG. 5 is a diagram showing an output driver according to an embodiment of the present invention;
FIG. 6 is a timing diagram showing the principal signals of the output driver of FIG. 5; and
FIG. 7 is a graph showing the effect of the output driver according to an embodiment of the present invention.
 DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
FIG. 5 is a diagram showing an output driver 100 according to an embodiment of the present invention. FIG. 6 is a timing diagram showing signals of the output driver 100 of FIG. 5.
Reference character CLK denotes a clock signal used to indicate a bit period pBIT.
The output driver 100 drives output data ODAT corresponding to input data IDAT. In this case, the input data IDAT has consecutively valid data bits for a plurality of consecutive bit periods. According to an embodiment of the present invention, a single data bit is assigned to a single bit period pBIT.
Referring to FIG. 5, the output driver 100 includes a selection signal generation unit 110, a reference data generation unit 130 and a selection unit 150.
The selection signal generation unit 110 receives the input data IDAT, and generates a selection signal /TX based on the input data IDAT. The selection signal /TX is activated to a logic L state at the transition point of the input data IDAT, generated after being maintained in the same logic state for a number of bit periods that is equal to or greater than a predetermined duration number, e.g., 2.
In detail, the selection signal generation unit 110 includes a bit shifter 111 and a logic operation means 113.
The bit shifter 111 delays the received input data IDAT by one bit period pBIT. The shifted data SDAT output from the bit shifter 111 is shifted from the input data IDAT by one bit period, as shown in FIG. 6.
The logic operation means 113 performs a logic operation on the input data IDAT and the shifted data SDAT, thus generating the selection signal /TX. Preferably, the logic operation means 113 is an Exclusive-OR logic gate for performing an Exclusive-OR operation on the input data IDAT and the shifted data SDAT. In an interval during which the input data IDAT and the shifted data SDAT have the same logic state, the selection signal /TX is transitioned to a logic L state. Further, in an interval during which the input data IDAT and the shifted data SDAT have different logic states, the selection signal /TX is transitioned to a logic H state.
The transition of the logic state of the selection signal /TX occurs after being delayed from that of the input data IDAT or the shifted data SDA by a predetermined period (each “pd” in FIG. 6).
At the point at which the input data IDAT is transitioned after being maintained in the same logic state for two or more bit periods (refer to t1 and t2 in FIG. 6) the selection signal /TX is activated to a logic L state. At the point at which the input data IDAT is transitioned again after one bit period (refer to t3, t4 and t5 in FIG. 6) the selection signal /TX is deactivated to a logic H state.
Referring to FIG. 5, the reference data generation unit 130 delays the input data IDAT by a predetermined delay time (refer to td in FIG. 6), thus generating reference data RDAT. The delay time td is shorter than the bit period pBIT.
The selection unit 150 generates output data ODAT that is transitioned depending on the transition of the logic state of any one of the input data IDAT and the reference data RDAT in response to the selection signal /TX.
According to an embodiment of the present invention, when the selection signal /TX is in a logic L state, the transition of the logic state of the output data ODAT follows the transition of the input data IDAT. The logic state of the output data ODAT is also transitioned to a logic H state in response to the transition of the input data IDAT to a logic H state (refer to t6 and t7 in FIG. 6). Further, the logic state of the output data ODAT is also transitioned to a logic L state in response to the transition of the input data IDAT to a logic L state (refer to time t8 in FIG. 6).
When the selection signal /TX is in a logic H state, the transition of the logic state of the output data ODAT follows the transition of the reference data RDAT. The logic state of the output data ODAT is also transitioned to a logic H state in response to the transition of the reference data RDAT to a logic H state (refer to t9 in FIG. 6). The logic state of the output data ODAT is transitioned to a logic L state in response to the transition of the reference data RDAT to a logic L state (refer to t10 and t11 in FIG. 6).
If the input data IDAT is transitioned after being maintained in the same logic state for a number of bit periods that is equal to or greater than the duration number (e.g., ‘2’ in the above example), the logic state of the output data ODAT is transitioned in response to the input data IDAT. As shown in FIG. 6, the logic state of the output data ODAT is transitioned earlier than the reference data RDAT by the delay time td. Accordingly, the attenuation of data that may occur in the output data ODAT can be mitigated.
If the logic state of the input data IDAT is transitioned at each bit period, the logic state of the output data ODAT is transitioned depending on the reference data RDAT; the output data ODAT is not transitioned in advance. Such an operation is performed in consideration of the fact that the attenuation of transmission data is relatively low when the logic state of the transmission data is transitioned at each bit. In this case, a period secured for data that is transitioned at each bit can be sufficiently assigned as one bit period.
FIG. 7 is a graph showing the effect of the output driver according to an embodiment of the present invention. As shown in FIG. 7, the logic state of the output data ODAT is transitioned in advance in response to the input data IDAT, not the reference data RDAT. The eye window of the output data ODAT increases compared to that of the case where the enhancement of initial data is not performed.
In the above-described output driver and output driving method according to an embodiment of the present invention, the input data IDAT and the output data ODAT are not needed to be driven to a voltage level higher than the voltage level Vh in a logic H state, nor a voltage level lower than the voltage level Vl in a logic L state, so as to enhance the initial input or output data. The output driver and output driving method according to an embodiment of the present invention cause the transition of the logic state of the output data ODAT in advance of the reference data RDAT, thus generating an effect similar to the enhancement of initial data. Therefore, the output driver does not require circuits for generating a high voltage higher than a typical high voltage level nor a low voltage lower than a typical low voltage level.
Further, in the output driver according to an embodiment of the present invention output data is generated by the selection unit. Therefore, the capacitance of the output stage of the output driver decreases compared to the conventional output drivers in FIGS. 1 and 3.
Although preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the disclosure.
For example, according to an embodiment of the present specification, the duration number is 2. The number of bit periods shifted by the bit shifter and/or the construction of a logic operation means are changeable, so that the duration number can be changed to, for example, 1, or a number equal to or greater than 3.

Claims (14)

1. An output driver of generating output data, comprising:
a selection signal generation unit for generating a selection signal based on input data having consecutively valid data bits during a plurality of consecutive bit periods, the selection signal being activated at a transition point of the input data, generated after being maintained in a same logic state during a number of bit periods that is equal to or greater than a predetermined duration number;
a reference data generation unit for delaying the input data by a delay time shorter than one bit period, and generating reference data as delayed input data; and
a selection unit, electrically coupled to the selection signal generation unit and the reference data generation unit, driven to transition a logic state of the output data depending on a transition of a logic state of any one of the input data and the reference data in response to the selection signal.
2. The output driver according to claim 1, wherein the selection unit is driven to transition the logic state of the output data depending on the transition of the logic state of the input data in response to a deactivated selection signal.
3. The output driver according to claim 1, wherein the selection unit is driven to transition the logic state of the output data depending on the transition of the logic state of the reference data in response to an activated selection signal.
4. The output driver according to claim 1, wherein the predetermined duration number is 2 bit periods.
5. The output driver according to claim 1, wherein the predetermined duration number is a multiple of one bit period.
6. The output driver according to claim 5, wherein the selection signal generation unit comprises:
a bit shifter for shifting the input data by one bit period and generating shifted data; and
logic operation means for performing a logic operation on the input data and the shifted data to generate the selection signal.
7. The output driver according to claim 6, wherein the logic operation means comprises an Exclusive-OR logic gate for performing an Exclusive-OR operation on the input data and the shifted data.
8. An output driving method of generating output data, comprising:
generating a selection signal based on input data having a plurality of consecutive data bits, the selection signal being activated at a transition point of the input data, the transition point generated after the input data has been maintained in a same logic state during a number of bit periods that is equal to or greater than a predetermined duration number;
generating reference data as the input data delayed by a delay time shorter than one bit period; and
transitioning a logic state of the output data depending on a transition of a logic state of any one of the input data and the reference data in response to the selection signal.
9. The output driving method according to claim 8, wherein the transitioning of the logic state comprises performing driving to transition the logic state of the output data depending on the transition of the logic state of the input data in response to a deactivated selection signal.
10. The output driving method according to claim 8, wherein the transitioning of the logic state comprises performing driving to transition the logic state of the output data depending on the transition of the logic state of the reference data in response to an activated selection signal.
11. The output driving method according to claim 8, wherein the predetermined duration number is 2 bit periods.
12. The output driver method according to claim 8, wherein the predetermined duration number is a multiple of one bit period.
13. The output driving method according to claim 12, wherein the generating of the selection signal comprises:
generating shifted data by shifting the input data by one bit period; and
performing a logic operation on the input data and the shifted data to generate the selection signal.
14. The output driving method according to claim 13, wherein the performing of the logic operation is executed to perform an Exclusive-OR operation on the input data and the shifted data.
US11/561,765 2005-11-18 2006-11-20 Output driver and output driving method for enhancing initial output data using timing Active US7368949B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2005-110518 2005-11-18
KR1020050110518A KR100666179B1 (en) 2005-11-18 2005-11-18 Output driver and output driving method for preemphasis in output data with timing

Publications (2)

Publication Number Publication Date
US20070115752A1 US20070115752A1 (en) 2007-05-24
US7368949B2 true US7368949B2 (en) 2008-05-06

Family

ID=37867306

Family Applications (1)

Application Number Title Priority Date Filing Date
US11/561,765 Active US7368949B2 (en) 2005-11-18 2006-11-20 Output driver and output driving method for enhancing initial output data using timing

Country Status (4)

Country Link
US (1) US7368949B2 (en)
JP (1) JP4964566B2 (en)
KR (1) KR100666179B1 (en)
DE (1) DE102006054999B4 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6623798B2 (en) 2016-02-02 2019-12-25 富士通株式会社 Light emitting element drive circuit

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6064356A (en) * 1996-10-22 2000-05-16 Pioneer Electronics Corporation Driving system for a self-luminous display
US6185716B1 (en) * 1998-01-30 2001-02-06 Maxtor Corporation Dual detector read channel with semi-soft detection
KR20020083329A (en) 2001-04-27 2002-11-02 주식회사 하이닉스반도체 Cmos output driving circuit
JP2002368600A (en) 2001-06-08 2002-12-20 Mitsubishi Electric Corp Pre-emphasis circuit
US20030099310A1 (en) * 1999-05-12 2003-05-29 Zoran Zvonar Method for correcting DC offsets in a receiver
JP2003243940A (en) 2002-01-21 2003-08-29 Evolium Sas Method and apparatus for preparing signals compared at pre-emphasis setting at input of amplifier
US7126394B2 (en) * 2004-05-17 2006-10-24 Micron Technology, Inc. History-based slew rate control to reduce intersymbol interference
US7277499B2 (en) * 2002-02-01 2007-10-02 Nxp B.V. Additive DC component detection included in an input burst signal

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002039629A2 (en) * 2000-10-31 2002-05-16 Igor Anatolievich Abrosimov Channel time calibration means

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6064356A (en) * 1996-10-22 2000-05-16 Pioneer Electronics Corporation Driving system for a self-luminous display
US6185716B1 (en) * 1998-01-30 2001-02-06 Maxtor Corporation Dual detector read channel with semi-soft detection
US20030099310A1 (en) * 1999-05-12 2003-05-29 Zoran Zvonar Method for correcting DC offsets in a receiver
KR20020083329A (en) 2001-04-27 2002-11-02 주식회사 하이닉스반도체 Cmos output driving circuit
JP2002368600A (en) 2001-06-08 2002-12-20 Mitsubishi Electric Corp Pre-emphasis circuit
JP2003243940A (en) 2002-01-21 2003-08-29 Evolium Sas Method and apparatus for preparing signals compared at pre-emphasis setting at input of amplifier
US7277499B2 (en) * 2002-02-01 2007-10-02 Nxp B.V. Additive DC component detection included in an input burst signal
US7126394B2 (en) * 2004-05-17 2006-10-24 Micron Technology, Inc. History-based slew rate control to reduce intersymbol interference

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
English Abstract for Publication No.: 1020020083329, filing date: Apr. 27, 2001, pub date: Nov. 2, 2002.
English Abstract for Publication No.: JP2002368600, pub date: Dec. 20, 2002.
English Abstract for Publication No.: JP2003243940, pub date: Aug. 29, 2003.

Also Published As

Publication number Publication date
DE102006054999B4 (en) 2011-12-15
JP4964566B2 (en) 2012-07-04
US20070115752A1 (en) 2007-05-24
KR100666179B1 (en) 2007-01-09
DE102006054999A1 (en) 2007-07-19
JP2007143159A (en) 2007-06-07

Similar Documents

Publication Publication Date Title
US7391238B2 (en) Semiconductor memory device having pre-emphasis signal generator
US7701257B2 (en) Data receiver and semiconductor device including the data receiver
US9722582B2 (en) Semiconductor device with output driver pre-emphasis scheme
US8630336B2 (en) Partial response receiver and related method
US9203606B2 (en) Clock recovery circuit, data receiving device, and data sending and receiving system
US8362996B2 (en) Display with CLK phase auto-adjusting mechanism and method of driving same
US20100117702A1 (en) Duty cycle correction apparatus and semiconductor integrated circuit having the same
US7545164B2 (en) Output driver for controlling impedance and intensity of pre-emphasis driver using mode register set
KR101839884B1 (en) Semiconductor device
KR20090024444A (en) Receiver circuit
US8604830B2 (en) Semiconductor device
KR100640593B1 (en) Output driver circuit with cascaded pre-emphasis function
US10944600B2 (en) Data transmission circuit
US20080191763A1 (en) Clock control circuit and semiconductor integrated circuit using the same
US7368949B2 (en) Output driver and output driving method for enhancing initial output data using timing
KR102021336B1 (en) Semiconductor device and operating methode for the same
KR20070109418A (en) Serial transmitter with pre-emphasis
KR20090039295A (en) Data transfer circuit
US7830166B2 (en) Pulse shift modulation for reducing cross-talk of single ended I/O interconnects
US8243868B2 (en) Method and apparatus for duty cycle pre-distortion and two-dimensional modulation
KR102271075B1 (en) Signal receiving circuit and method for adjusting weight of compensator
US7221182B2 (en) Open drain type output buffer
US6384661B1 (en) Multi level jitter pre-compensation logic circuit for high speed data links
KR100524947B1 (en) Open drain output buffer
KR20060058841A (en) Output driver controlling slew rate in designated region of output signal

Legal Events

Date Code Title Description
AS Assignment

Owner name: SAMSUNG ELECTRONICS CO., LTD, KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SOHN, YOUNG-SOO;CHOI, JUNG-HWAN;REEL/FRAME:018829/0577;SIGNING DATES FROM 20061227 TO 20070117

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 12