US7363602B2  Computersupported, automated method for the verification of analog circuits  Google Patents
Computersupported, automated method for the verification of analog circuits Download PDFInfo
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 US7363602B2 US7363602B2 US11/085,595 US8559505A US7363602B2 US 7363602 B2 US7363602 B2 US 7363602B2 US 8559505 A US8559505 A US 8559505A US 7363602 B2 US7363602 B2 US 7363602B2
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 G06—COMPUTING; CALCULATING; COUNTING
 G06F—ELECTRIC DIGITAL DATA PROCESSING
 G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
 G06F17/50—Computeraided design
 G06F17/5009—Computeraided design using simulation
 G06F17/5036—Computeraided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
Abstract
Description
This application claims priority to German Application No. 10 2004 014 178.9 filed Mar. 23, 2004, which is incorporated herein, in its entirety, by reference.
The invention relates to a computersupported, automated method for the verification of analog circuits, and to a storage medium on which a computer software program for performing such method is stored.
Due to further augmented integration densities and functionalities, the design of analog circuits has become increasingly complex.
Due to the complexity of the circuits, a structured circuit design—following, for instance, the “topdown”, “bottomup”, or some other common approach—has become indispensable.
In the case of the topdown approach, the design of the corresponding circuit is, for instance, started on a relatively high abstraction level; subsequently, the corresponding design is—on ever lower abstraction levels—increasingly refined (e.g. —functionally—starting out from a “system level” to a “circuit level”, etc., or—structurally—starting out from an “overall system level” via corresponding “subsystem” or “module” levels to the “individual circuit element level” with the various individual devices (transistors, diodes, resistors, capacitors, etc.).
Appropriate tests or simulations, respectively, take place (on every abstraction level) after every design step. In the case of fault, the design result will have to be modified, or the corresponding design step will have to be repeated, or the design will have to be started anew on some higher level.
The circuit models are available either e.g. structurally in the form of network lists with analog circuit elements (transistors, diodes, resistors, capacitors, etc.), or e.g. functionally in the form of an analog description language such as VHDLAMS, or in mixed forms of structural and functional description.
The abovementioned proceeding (performing of simulations after every design step on every abstraction level) is to ensure—despite the increased circuit complexity caused by increased integration densities and functionalities—that the designed circuit works without fault.
In the case of the common circuit simulation methods, the circuit behavior (input/output behavior)—in the time range—is examined at different test input signals, which may involve great efforts, and (since the circuit can, within a justifiable time, be tested for a limited number of different test input signals only) does not always furnish the desired certainty with respect to receiving all and any circuit states that are practically existing.
The invention to provides a novel, automated method for the verification of circuits, and a storage medium on which a computer software program for performing such method is stored.
In the following, the invention will be explained in more detail with reference to the exemplary embodiments and drawings. The drawings show:
The behavior of analog circuits may—in the scope of the socalled modified node analysis—be described by means of the following equation system:
C(x)·{dot over (x)}+f(x,t)=0
The vector x here comprises (corresponding to the “common” node analysis)—as an unknown—the node voltages searched, and (other than with the “common” node analysis)—as an additional unknown—all the currents flowing through voltage sources or coils, respectively, available in the circuit.
The concept of the modified node analysis is, for instance, described in Chung W. Ho, Albert E. Ruehli, Pierce A. Brennan, The modified nodal approach to network analysis, Proceedings of 1974 IEEE International Symposium on Circuits and Systems, April 1974, pp. 505509.
A circuit description by means of the abovementioned modified node analyses is not sufficient for most of the industrially relevant circuits since their behavior can only be described in compliance with reality in an enlarged charge/floworiented form that takes, in particular, the charges of the capacities into additional account.
A charge/floworiented form of the circuit description results in differentialalgebraic equation systems of index 1 or larger, e.g. of the type:
A·{dot over (q)}+f(x,t)=0
q−f _{q}(x,t)=0
This will be explained by way of example in more detail in the following by means of the circuit 1 illustrated in
The circuit 1 comprises one diode 2, two capacitors 3, 4, two resistors 5, 6, and one voltage source 7.
The circuit 1 comprises three nodes n1, n2, n3, the potentials of which are assumed to be unknown quantities (“node voltages”). In addition there is—as additional unknown quantity—the current Iv flowing through the voltage source 7.
Furthermore, the circuit 1 comprises two state variables given by the two capacitor voltages.
For the circuit 1, the node equations and the equations for the independent currents (flowing through voltage sources) read—corresponding to the abovementioned charge/floworiented form (here: viewed—structurally—in the form of an appropriate network list description)—as follows:
The vector of the unknown quantities reads:
The theory of the charge/floworiented circuit description is described in detail, for instance, in Michael Günther, Uwe Feldmann, CADbased electriccircuit modeling in industry, I. Mathematical structure and index of network equations, Surveys on Mathematics for Industry, 1999, vol. 8, pp. 97129.
In the case of the present embodiment, it is verified—in a computersupported, automated manner—whether—in the scope of respectively predetermined tolerances—two circuit descriptions assigned e.g. to two different (topdown or bottomup, etc.) abstraction levels for one and the same circuit i) have an identical inputoutput behavior, and—as will be explained in more detail further below—ii) have an identical dynamic behavior (also in the scope of respectively predetermined tolerances).
One can, for instance, verify whether a corresponding structural—charge/floworiented—network list description of a circuit (explained by way of example by means of the abovementioned circuit 1) has—within corresponding tolerances—an identical dynamical behavior and an identical inputoutput behavior as a corresponding—e.g. functional—description of the circuit (e.g. in VHDLAMS, etc.) (or e.g. a mixed, structural/functional circuit description, etc., etc., or a—further—structural network list description).
The equation systems to be compared
A _{1} ·{dot over (q)} _{1} +f _{1}(x _{1} ,t)=0
q _{1} −f _{q1}(x _{1} ,t)=0
and
A _{2} ·{dot over (q)} _{2} +f _{2}(x _{2} ,t)=0
q _{2} −f _{q2}(x _{2} ,t)=0
or e.g.
C(x)·{dot over (x)}+f(x,t)=0
in general have different dimensions.
The reading of the network list or of the network lists, respectively, into the computer 8—performing the verification method described here and illustrated schematically in FIG. 3—, and the drafting of the corresponding equation systems can, for instance—in an automated manner—be performed by means of an appropriate circuit simulator, e.g. Titan (circuit simulator of the Company Infineon).
To this end, a check program stored on the computer 8 sends, via the socket interface, a corresponding initialization command to Titan which will then return the list of the names of the variables and the number of the variables.
The appropriate computer software programs required for performing the circuit verification method illustrated here (check program, Titan) may be stored on a storage device 9—which is also illustrated schematically in FIG. 3—of the computer 8.
Next—for the two circuit descriptions to be compared—a balanced state is considered for a particular, predetermined (initial) input, or at a particular DC working point, respectively, e.g. at a working point characterized by i_{q}=dq/dt=0 (cf. also step S1 illustrated in
To this end, the check program sends the value of the (initial) input via a socket to Titan which performs—for the (initial) input or at an (initial) working point, respectively—a DC simulation for both circuit descriptions and returns a corresponding solution vector x that preferably contains the output directly (cf. e.g. also step S2 illustrated in
The outputs resulting for the two circuit descriptions (or—more exactly—for both descriptions the quantities x_{1,1 }and x_{2,1}, as well as x_{1,2 }and x_{2,2}, etc. that correspond to one another, respectively (or y_{—}1εx_{—}1, y_{—}2εx_{—}2)) are compared to each other. It is in particular examined whether these are identical, or whether deviations between the resulting values of the outputs are within the abovementioned, predetermined tolerances (i.e. a “circuit equivalence test” is performed in the original space (cf. also step S3 illustrated in
In parallel, a linearization is performed in Titan for both circuit descriptions and at the abovementioned (initial) working point (or at the resulting quantities for the unknown x=(x_{old}, i_{q,old}), respectively) (cf. also step S4 illustrated in
The calculated G, C, Fmatrices are—via the socket interface—transferred to the check program.
By means of the Fmatrix (or its inverse F^{−1}, respectively)—as will be explained in more detail in the following—the abovementioned circuit descriptions—in particular the vector x=(x, i_{q}) of the unknown quantities (first of all at the initial working point x=(x_{old}, i_{q,old}))—are transformed from the original space to a virtual, redundancyfree, linearized subspace, e.g. by means of the image
z=F ^{−1} x
By that, a—transformed—state vector z is obtained; the values contained therein are—via the socket—transferred to the check program (cf. also step S6 illustrated in
The FMatrix may—as will also be explained in more detail further below—be obtained e.g. by means of a QZ method from the abovementioned charge/floworiented circuit description equations.
For the calculation of the FMatrix—as will also be explained in more detail further below—the eigenvalues λ and the right eigenvectors Vr are required, which are determined from the generalized eigenvalue problem by means of Titan.
After the determination of the FMatrix (and of the state vectors z) the state quantities contained in the vector z are—for the two circuit descriptions to be compared—changed in the abovementioned virtual, redundancyfree, linearized subspace—each by a particular, fixed increment—, e.g. are increased (wherein the following applies: Δz=z_{new}−z_{old})—in other words, the condition z_{old }obtained for the system with the abovementioned calculation is “deflected” (cf. also step S7 illustrated in
To this end, the check program sends, as described above, the vector values increased by the abovementioned increments to Titan via the socket.
Subsequently—in the abovementioned, transformed state space—a “circuit equivalence test” is performed (cf. also step S8 illustrated in
As an error measure, Titan forms—for both circuit descriptions—the respective time derivative of the abovementioned, new (“deflected”) state variables z_{new }and transmits same—via the socket—to the check program.
The time derivative of the abovementioned, new (“deflected”) state variables z_{new }can be determined by means of Titan by solving the following equation system:
C·F·ż _{new} =A·i _{qnew }
C is the Jacobi matrix
in the place x_{old}.
Furthermore—from the (new) state vector z_{new }(or the vector Δz=z_{new}−z_{old}, respectively)—the—new—vector x=(x_{new}, i_{q,new}) resulting therefrom in the original space is calculated, namely (by means of Titan) by solving the equation system—resulting from the abovementioned equation system for charge/floworiented circuit descriptions:
A·i _{qnew} +f(x _{new})=0
q _{new} −f _{q}(x _{new})=f _{q}(x _{old} +F·Δz)−f _{q}(x _{new})=0
Newly developed methods for calculating consistent initial values may be employed to this end, such as described, for example, in Estevez Schwarz, D.: Consistent initialization for index2 differential algebraic equations and its application to circuit simulation, HumboldtUniv. Berlin, PhD Thesis, 2000.
Subsequently, again and correspondingly similar as described above, a new balanced state is—for the two circuit descriptions to be compared—taken into account at a new working point, e.g. at a new working point characterized by i_{q}=i_{q,new }(or a working point that has been changed by increments, in particular has been increased) (correspondingly similar to step S1 illustrated in
The values determined—for the two circuit descriptions—for the outputs are again (correspondingly similar to step S3 illustrated in
Furthermore—again as described above—a linearization is performed for both circuit descriptions and at the abovementioned new working point (or at the quantities for the unknowns x resulting therefrom, respectively) (cf. also step S4 illustrated in
By means of the F (or F^{−1}) matrix—corresponding to step S6 illustrated in
Subsequently, the state quantities contained in the vector z are again changed—each again by the abovementioned particular, fixed increment (corresponding to step S7 illustrated in
The abovementioned steps S1 to S8—illustrated schematically in FIG. 2—are repeated for all the working points predetermined by the check program (each determined and run through step by step in accordance with the description above).
If it is determined in all the tests performed in the original and in the transformed state space (steps S3 or S8, respectively) that the corresponding quantities lie within the abovementioned tolerance ranges, the two circuit descriptions are considered to be “equivalent” or sufficiently equivalent, respectively. If this is not the case, the computer 8 may—controlled by the check program—e.g. output an appropriate error message.
The following is a brief explanation about how the matrices required for the abovementioned verification method (in particular the G, C, and Fmatrices) can be calculated.
Starting point for the considerations is the generalized eigenvalue problem:
(Cα+Gβ)x=0
with the eigenvalues λ=α/β.
The matrices G and C correspond to the leading value and capacity matrix of the respective linearized system.
For solving the abovementioned generalized eigenvalue problem, e.g. the QZ algorithm that has already been mentioned above may be employed.
For the further calculation, the following assumptions are made:
Assumption 1: G is regular, invertible

 all eigenvalues λ are ≠0;
Assumption 2: The number of the eigenvectors corresponds to the number of the eigenvalues  the algebraic and geometric multiplicity are identical;
 index ≦1;
 no secondary diagonal elements in G and C;
Assumption 3: E and F are invertible.
 all eigenvalues λ are ≠0;
Searched are the two transformation matrices E and F, for which the following shall apply:
The QZ algorithm returns the right eigenvectors in matrix form. The right eigenvectors are deposited in the corresponding matrix column by column:
V _{r} =[v _{r}(λ1)v _{r}(λ2) . . . v _{r}(λn)]
Taking into account this equation, the solution of the generalized eigenvalue problems can be represented as follows:
CVr
Furthermore, there follows from the abovementioned equations by multiplication with E^{−1 }from the left:
GF=E ^{−1}
and
CF=E ^{−1}
The transformation matrices E and F can be determined by means of coefficient comparison. To this end, the negative summand of the abovementioned equation CVr
As a result, one obtains:
F=Vr
E ^{−1} =CVr
F=Vr
E ^{−1} =GVr
The abovementioned equation F=Vr
This is not the case with the equations F=Vr
Since the matrices G and V_{r }have full rank, they can be inverted and dissolved to:
F=Vr
E=V _{r} ^{−1} G ^{−1 }
Since both
F=Vr
E=
For systems with an index >1, a correspondingly enlarged approach can be used.
For the abovementioned exemplary circuit 1 illustrated in
The finite eigenvalues of the circuit 1 are symbolically for R1=R2 and C1=C2:
Additionally, there are two infinite eigenvalues. The matrix of the right eigenvectors is calculated for equal Rs and Cs symbolically as follows:
Claims (18)
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2004
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Title 

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